1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 6 7 #include <linux/debugfs.h> 8 #include <linux/errno.h> 9 #include <linux/mutex.h> 10 #include <linux/sort.h> 11 #include <linux/clk.h> 12 #include <linux/bitmap.h> 13 14 #include "dpu_kms.h" 15 #include "dpu_trace.h" 16 #include "dpu_crtc.h" 17 #include "dpu_core_perf.h" 18 19 /** 20 * enum dpu_perf_mode - performance tuning mode 21 * @DPU_PERF_MODE_NORMAL: performance controlled by user mode client 22 * @DPU_PERF_MODE_MINIMUM: performance bounded by minimum setting 23 * @DPU_PERF_MODE_FIXED: performance bounded by fixed setting 24 */ 25 enum dpu_perf_mode { 26 DPU_PERF_MODE_NORMAL, 27 DPU_PERF_MODE_MINIMUM, 28 DPU_PERF_MODE_FIXED, 29 DPU_PERF_MODE_MAX 30 }; 31 32 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 33 { 34 struct msm_drm_private *priv; 35 36 if (!crtc->dev || !crtc->dev->dev_private) { 37 DPU_ERROR("invalid device\n"); 38 return NULL; 39 } 40 41 priv = crtc->dev->dev_private; 42 if (!priv || !priv->kms) { 43 DPU_ERROR("invalid kms\n"); 44 return NULL; 45 } 46 47 return to_dpu_kms(priv->kms); 48 } 49 50 static bool _dpu_core_video_mode_intf_connected(struct drm_crtc *crtc) 51 { 52 struct drm_crtc *tmp_crtc; 53 54 drm_for_each_crtc(tmp_crtc, crtc->dev) { 55 if ((dpu_crtc_get_intf_mode(tmp_crtc) == INTF_MODE_VIDEO) && 56 tmp_crtc->enabled) { 57 DPU_DEBUG("video interface connected crtc:%d\n", 58 tmp_crtc->base.id); 59 return true; 60 } 61 } 62 63 return false; 64 } 65 66 static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, 67 struct drm_crtc *crtc, 68 struct drm_crtc_state *state, 69 struct dpu_core_perf_params *perf) 70 { 71 struct dpu_crtc_state *dpu_cstate; 72 73 if (!kms || !kms->catalog || !crtc || !state || !perf) { 74 DPU_ERROR("invalid parameters\n"); 75 return; 76 } 77 78 dpu_cstate = to_dpu_crtc_state(state); 79 memset(perf, 0, sizeof(struct dpu_core_perf_params)); 80 81 if (!dpu_cstate->bw_control) { 82 perf->bw_ctl = kms->catalog->perf.max_bw_high * 83 1000ULL; 84 perf->max_per_pipe_ib = perf->bw_ctl; 85 perf->core_clk_rate = kms->perf.max_core_clk_rate; 86 } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) { 87 perf->bw_ctl = 0; 88 perf->max_per_pipe_ib = 0; 89 perf->core_clk_rate = 0; 90 } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) { 91 perf->bw_ctl = kms->perf.fix_core_ab_vote; 92 perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote; 93 perf->core_clk_rate = kms->perf.fix_core_clk_rate; 94 } 95 96 DPU_DEBUG( 97 "crtc=%d clk_rate=%llu core_ib=%llu core_ab=%llu\n", 98 crtc->base.id, perf->core_clk_rate, 99 perf->max_per_pipe_ib, perf->bw_ctl); 100 } 101 102 int dpu_core_perf_crtc_check(struct drm_crtc *crtc, 103 struct drm_crtc_state *state) 104 { 105 u32 bw, threshold; 106 u64 bw_sum_of_intfs = 0; 107 enum dpu_crtc_client_type curr_client_type; 108 bool is_video_mode; 109 struct dpu_crtc_state *dpu_cstate; 110 struct drm_crtc *tmp_crtc; 111 struct dpu_kms *kms; 112 113 if (!crtc || !state) { 114 DPU_ERROR("invalid crtc\n"); 115 return -EINVAL; 116 } 117 118 kms = _dpu_crtc_get_kms(crtc); 119 if (!kms || !kms->catalog) { 120 DPU_ERROR("invalid parameters\n"); 121 return 0; 122 } 123 124 /* we only need bandwidth check on real-time clients (interfaces) */ 125 if (dpu_crtc_get_client_type(crtc) == NRT_CLIENT) 126 return 0; 127 128 dpu_cstate = to_dpu_crtc_state(state); 129 130 /* obtain new values */ 131 _dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf); 132 133 bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl; 134 curr_client_type = dpu_crtc_get_client_type(crtc); 135 136 drm_for_each_crtc(tmp_crtc, crtc->dev) { 137 if (tmp_crtc->enabled && 138 (dpu_crtc_get_client_type(tmp_crtc) == 139 curr_client_type) && (tmp_crtc != crtc)) { 140 struct dpu_crtc_state *tmp_cstate = 141 to_dpu_crtc_state(tmp_crtc->state); 142 143 DPU_DEBUG("crtc:%d bw:%llu ctrl:%d\n", 144 tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, 145 tmp_cstate->bw_control); 146 /* 147 * For bw check only use the bw if the 148 * atomic property has been already set 149 */ 150 if (tmp_cstate->bw_control) 151 bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl; 152 } 153 154 /* convert bandwidth to kb */ 155 bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000); 156 DPU_DEBUG("calculated bandwidth=%uk\n", bw); 157 158 is_video_mode = dpu_crtc_get_intf_mode(crtc) == INTF_MODE_VIDEO; 159 threshold = (is_video_mode || 160 _dpu_core_video_mode_intf_connected(crtc)) ? 161 kms->catalog->perf.max_bw_low : 162 kms->catalog->perf.max_bw_high; 163 164 DPU_DEBUG("final threshold bw limit = %d\n", threshold); 165 166 if (!dpu_cstate->bw_control) { 167 DPU_DEBUG("bypass bandwidth check\n"); 168 } else if (!threshold) { 169 DPU_ERROR("no bandwidth limits specified\n"); 170 return -E2BIG; 171 } else if (bw > threshold) { 172 DPU_ERROR("exceeds bandwidth: %ukb > %ukb\n", bw, 173 threshold); 174 return -E2BIG; 175 } 176 } 177 178 return 0; 179 } 180 181 static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, 182 struct drm_crtc *crtc) 183 { 184 struct dpu_core_perf_params perf = { 0 }; 185 enum dpu_crtc_client_type curr_client_type 186 = dpu_crtc_get_client_type(crtc); 187 struct drm_crtc *tmp_crtc; 188 struct dpu_crtc_state *dpu_cstate; 189 int ret = 0; 190 191 drm_for_each_crtc(tmp_crtc, crtc->dev) { 192 if (tmp_crtc->enabled && 193 curr_client_type == 194 dpu_crtc_get_client_type(tmp_crtc)) { 195 dpu_cstate = to_dpu_crtc_state(tmp_crtc->state); 196 197 perf.max_per_pipe_ib = max(perf.max_per_pipe_ib, 198 dpu_cstate->new_perf.max_per_pipe_ib); 199 200 DPU_DEBUG("crtc=%d bw=%llu\n", tmp_crtc->base.id, 201 dpu_cstate->new_perf.bw_ctl); 202 } 203 } 204 return ret; 205 } 206 207 /** 208 * @dpu_core_perf_crtc_release_bw() - request zero bandwidth 209 * @crtc - pointer to a crtc 210 * 211 * Function checks a state variable for the crtc, if all pending commit 212 * requests are done, meaning no more bandwidth is needed, release 213 * bandwidth request. 214 */ 215 void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) 216 { 217 struct dpu_crtc *dpu_crtc; 218 struct dpu_crtc_state *dpu_cstate; 219 struct dpu_kms *kms; 220 221 if (!crtc) { 222 DPU_ERROR("invalid crtc\n"); 223 return; 224 } 225 226 kms = _dpu_crtc_get_kms(crtc); 227 if (!kms || !kms->catalog) { 228 DPU_ERROR("invalid kms\n"); 229 return; 230 } 231 232 dpu_crtc = to_dpu_crtc(crtc); 233 dpu_cstate = to_dpu_crtc_state(crtc->state); 234 235 if (atomic_dec_return(&kms->bandwidth_ref) > 0) 236 return; 237 238 /* Release the bandwidth */ 239 if (kms->perf.enable_bw_release) { 240 trace_dpu_cmd_release_bw(crtc->base.id); 241 DPU_DEBUG("Release BW crtc=%d\n", crtc->base.id); 242 dpu_crtc->cur_perf.bw_ctl = 0; 243 _dpu_core_perf_crtc_update_bus(kms, crtc); 244 } 245 } 246 247 static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate) 248 { 249 struct dss_clk *core_clk = kms->perf.core_clk; 250 251 if (core_clk->max_rate && (rate > core_clk->max_rate)) 252 rate = core_clk->max_rate; 253 254 core_clk->rate = rate; 255 return msm_dss_clk_set_rate(core_clk, 1); 256 } 257 258 static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) 259 { 260 u64 clk_rate = kms->perf.perf_tune.min_core_clk; 261 struct drm_crtc *crtc; 262 struct dpu_crtc_state *dpu_cstate; 263 264 drm_for_each_crtc(crtc, kms->dev) { 265 if (crtc->enabled) { 266 dpu_cstate = to_dpu_crtc_state(crtc->state); 267 clk_rate = max(dpu_cstate->new_perf.core_clk_rate, 268 clk_rate); 269 clk_rate = clk_round_rate(kms->perf.core_clk->clk, 270 clk_rate); 271 } 272 } 273 274 if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) 275 clk_rate = kms->perf.fix_core_clk_rate; 276 277 DPU_DEBUG("clk:%llu\n", clk_rate); 278 279 return clk_rate; 280 } 281 282 int dpu_core_perf_crtc_update(struct drm_crtc *crtc, 283 int params_changed, bool stop_req) 284 { 285 struct dpu_core_perf_params *new, *old; 286 bool update_bus = false, update_clk = false; 287 u64 clk_rate = 0; 288 struct dpu_crtc *dpu_crtc; 289 struct dpu_crtc_state *dpu_cstate; 290 struct msm_drm_private *priv; 291 struct dpu_kms *kms; 292 int ret; 293 294 if (!crtc) { 295 DPU_ERROR("invalid crtc\n"); 296 return -EINVAL; 297 } 298 299 kms = _dpu_crtc_get_kms(crtc); 300 if (!kms || !kms->catalog) { 301 DPU_ERROR("invalid kms\n"); 302 return -EINVAL; 303 } 304 priv = kms->dev->dev_private; 305 306 dpu_crtc = to_dpu_crtc(crtc); 307 dpu_cstate = to_dpu_crtc_state(crtc->state); 308 309 DPU_DEBUG("crtc:%d stop_req:%d core_clk:%llu\n", 310 crtc->base.id, stop_req, kms->perf.core_clk_rate); 311 312 old = &dpu_crtc->cur_perf; 313 new = &dpu_cstate->new_perf; 314 315 if (crtc->enabled && !stop_req) { 316 /* 317 * cases for bus bandwidth update. 318 * 1. new bandwidth vote - "ab or ib vote" is higher 319 * than current vote for update request. 320 * 2. new bandwidth vote - "ab or ib vote" is lower 321 * than current vote at end of commit or stop. 322 */ 323 if ((params_changed && ((new->bw_ctl > old->bw_ctl) || 324 (new->max_per_pipe_ib > old->max_per_pipe_ib))) || 325 (!params_changed && ((new->bw_ctl < old->bw_ctl) || 326 (new->max_per_pipe_ib < old->max_per_pipe_ib)))) { 327 DPU_DEBUG("crtc=%d p=%d new_bw=%llu,old_bw=%llu\n", 328 crtc->base.id, params_changed, 329 new->bw_ctl, old->bw_ctl); 330 old->bw_ctl = new->bw_ctl; 331 old->max_per_pipe_ib = new->max_per_pipe_ib; 332 update_bus = true; 333 } 334 335 if ((params_changed && 336 (new->core_clk_rate > old->core_clk_rate)) || 337 (!params_changed && 338 (new->core_clk_rate < old->core_clk_rate))) { 339 old->core_clk_rate = new->core_clk_rate; 340 update_clk = true; 341 } 342 } else { 343 DPU_DEBUG("crtc=%d disable\n", crtc->base.id); 344 memset(old, 0, sizeof(*old)); 345 memset(new, 0, sizeof(*new)); 346 update_bus = true; 347 update_clk = true; 348 } 349 350 trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl, 351 new->core_clk_rate, stop_req, update_bus, update_clk); 352 353 if (update_bus) { 354 ret = _dpu_core_perf_crtc_update_bus(kms, crtc); 355 if (ret) { 356 DPU_ERROR("crtc-%d: failed to update bus bw vote\n", 357 crtc->base.id); 358 return ret; 359 } 360 } 361 362 /* 363 * Update the clock after bandwidth vote to ensure 364 * bandwidth is available before clock rate is increased. 365 */ 366 if (update_clk) { 367 clk_rate = _dpu_core_perf_get_core_clk_rate(kms); 368 369 trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate); 370 371 ret = _dpu_core_perf_set_core_clk_rate(kms, clk_rate); 372 if (ret) { 373 DPU_ERROR("failed to set %s clock rate %llu\n", 374 kms->perf.core_clk->clk_name, clk_rate); 375 return ret; 376 } 377 378 kms->perf.core_clk_rate = clk_rate; 379 DPU_DEBUG("update clk rate = %lld HZ\n", clk_rate); 380 } 381 return 0; 382 } 383 384 #ifdef CONFIG_DEBUG_FS 385 386 static ssize_t _dpu_core_perf_mode_write(struct file *file, 387 const char __user *user_buf, size_t count, loff_t *ppos) 388 { 389 struct dpu_core_perf *perf = file->private_data; 390 struct dpu_perf_cfg *cfg = &perf->catalog->perf; 391 u32 perf_mode = 0; 392 int ret; 393 394 ret = kstrtouint_from_user(user_buf, count, 0, &perf_mode); 395 if (ret) 396 return ret; 397 398 if (perf_mode >= DPU_PERF_MODE_MAX) 399 return -EINVAL; 400 401 if (perf_mode == DPU_PERF_MODE_FIXED) { 402 DRM_INFO("fix performance mode\n"); 403 } else if (perf_mode == DPU_PERF_MODE_MINIMUM) { 404 /* run the driver with max clk and BW vote */ 405 perf->perf_tune.min_core_clk = perf->max_core_clk_rate; 406 perf->perf_tune.min_bus_vote = 407 (u64) cfg->max_bw_high * 1000; 408 DRM_INFO("minimum performance mode\n"); 409 } else if (perf_mode == DPU_PERF_MODE_NORMAL) { 410 /* reset the perf tune params to 0 */ 411 perf->perf_tune.min_core_clk = 0; 412 perf->perf_tune.min_bus_vote = 0; 413 DRM_INFO("normal performance mode\n"); 414 } 415 perf->perf_tune.mode = perf_mode; 416 417 return count; 418 } 419 420 static ssize_t _dpu_core_perf_mode_read(struct file *file, 421 char __user *buff, size_t count, loff_t *ppos) 422 { 423 struct dpu_core_perf *perf = file->private_data; 424 int len; 425 char buf[128]; 426 427 len = scnprintf(buf, sizeof(buf), 428 "mode %d min_mdp_clk %llu min_bus_vote %llu\n", 429 perf->perf_tune.mode, 430 perf->perf_tune.min_core_clk, 431 perf->perf_tune.min_bus_vote); 432 433 return simple_read_from_buffer(buff, count, ppos, buf, len); 434 } 435 436 static const struct file_operations dpu_core_perf_mode_fops = { 437 .open = simple_open, 438 .read = _dpu_core_perf_mode_read, 439 .write = _dpu_core_perf_mode_write, 440 }; 441 442 int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) 443 { 444 struct dpu_core_perf *perf = &dpu_kms->perf; 445 struct dpu_mdss_cfg *catalog = perf->catalog; 446 struct dentry *entry; 447 448 entry = debugfs_create_dir("core_perf", parent); 449 450 debugfs_create_u64("max_core_clk_rate", 0600, entry, 451 &perf->max_core_clk_rate); 452 debugfs_create_u64("core_clk_rate", 0600, entry, 453 &perf->core_clk_rate); 454 debugfs_create_u32("enable_bw_release", 0600, entry, 455 (u32 *)&perf->enable_bw_release); 456 debugfs_create_u32("threshold_low", 0600, entry, 457 (u32 *)&catalog->perf.max_bw_low); 458 debugfs_create_u32("threshold_high", 0600, entry, 459 (u32 *)&catalog->perf.max_bw_high); 460 debugfs_create_u32("min_core_ib", 0600, entry, 461 (u32 *)&catalog->perf.min_core_ib); 462 debugfs_create_u32("min_llcc_ib", 0600, entry, 463 (u32 *)&catalog->perf.min_llcc_ib); 464 debugfs_create_u32("min_dram_ib", 0600, entry, 465 (u32 *)&catalog->perf.min_dram_ib); 466 debugfs_create_file("perf_mode", 0600, entry, 467 (u32 *)perf, &dpu_core_perf_mode_fops); 468 debugfs_create_u64("fix_core_clk_rate", 0600, entry, 469 &perf->fix_core_clk_rate); 470 debugfs_create_u64("fix_core_ib_vote", 0600, entry, 471 &perf->fix_core_ib_vote); 472 debugfs_create_u64("fix_core_ab_vote", 0600, entry, 473 &perf->fix_core_ab_vote); 474 475 return 0; 476 } 477 #endif 478 479 void dpu_core_perf_destroy(struct dpu_core_perf *perf) 480 { 481 if (!perf) { 482 DPU_ERROR("invalid parameters\n"); 483 return; 484 } 485 486 perf->max_core_clk_rate = 0; 487 perf->core_clk = NULL; 488 perf->catalog = NULL; 489 perf->dev = NULL; 490 } 491 492 int dpu_core_perf_init(struct dpu_core_perf *perf, 493 struct drm_device *dev, 494 struct dpu_mdss_cfg *catalog, 495 struct dss_clk *core_clk) 496 { 497 perf->dev = dev; 498 perf->catalog = catalog; 499 perf->core_clk = core_clk; 500 501 perf->max_core_clk_rate = core_clk->max_rate; 502 if (!perf->max_core_clk_rate) { 503 DPU_DEBUG("optional max core clk rate, use default\n"); 504 perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE; 505 } 506 507 return 0; 508 } 509