1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. 3 */ 4 5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 6 #include "dpu_encoder_phys.h" 7 #include "dpu_hw_interrupts.h" 8 #include "dpu_hw_merge3d.h" 9 #include "dpu_core_irq.h" 10 #include "dpu_formats.h" 11 #include "dpu_trace.h" 12 #include "disp/msm_disp_snapshot.h" 13 14 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ 15 (e) && (e)->parent ? \ 16 (e)->parent->base.id : -1, \ 17 (e) && (e)->hw_intf ? \ 18 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) 19 20 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \ 21 (e) && (e)->parent ? \ 22 (e)->parent->base.id : -1, \ 23 (e) && (e)->hw_intf ? \ 24 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) 25 26 #define to_dpu_encoder_phys_vid(x) \ 27 container_of(x, struct dpu_encoder_phys_vid, base) 28 29 static bool dpu_encoder_phys_vid_is_master( 30 struct dpu_encoder_phys *phys_enc) 31 { 32 bool ret = false; 33 34 if (phys_enc->split_role != ENC_ROLE_SLAVE) 35 ret = true; 36 37 return ret; 38 } 39 40 static void drm_mode_to_intf_timing_params( 41 const struct dpu_encoder_phys *phys_enc, 42 const struct drm_display_mode *mode, 43 struct dpu_hw_intf_timing_params *timing) 44 { 45 memset(timing, 0, sizeof(*timing)); 46 47 if ((mode->htotal < mode->hsync_end) 48 || (mode->hsync_start < mode->hdisplay) 49 || (mode->vtotal < mode->vsync_end) 50 || (mode->vsync_start < mode->vdisplay) 51 || (mode->hsync_end < mode->hsync_start) 52 || (mode->vsync_end < mode->vsync_start)) { 53 DPU_ERROR( 54 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n", 55 mode->hsync_start, mode->hsync_end, 56 mode->htotal, mode->hdisplay); 57 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n", 58 mode->vsync_start, mode->vsync_end, 59 mode->vtotal, mode->vdisplay); 60 return; 61 } 62 63 /* 64 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html 65 * Active Region Front Porch Sync Back Porch 66 * <-----------------><------------><-----><-----------> 67 * <- [hv]display ---> 68 * <--------- [hv]sync_start ------> 69 * <----------------- [hv]sync_end -------> 70 * <---------------------------- [hv]total -------------> 71 */ 72 timing->width = mode->hdisplay; /* active width */ 73 timing->height = mode->vdisplay; /* active height */ 74 timing->xres = timing->width; 75 timing->yres = timing->height; 76 timing->h_back_porch = mode->htotal - mode->hsync_end; 77 timing->h_front_porch = mode->hsync_start - mode->hdisplay; 78 timing->v_back_porch = mode->vtotal - mode->vsync_end; 79 timing->v_front_porch = mode->vsync_start - mode->vdisplay; 80 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start; 81 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start; 82 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0; 83 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 84 timing->border_clr = 0; 85 timing->underflow_clr = 0xff; 86 timing->hsync_skew = mode->hskew; 87 88 /* DSI controller cannot handle active-low sync signals. */ 89 if (phys_enc->hw_intf->cap->type == INTF_DSI) { 90 timing->hsync_polarity = 0; 91 timing->vsync_polarity = 0; 92 } 93 94 /* for DP/EDP, Shift timings to align it to bottom right */ 95 if (phys_enc->hw_intf->cap->type == INTF_DP) { 96 timing->h_back_porch += timing->h_front_porch; 97 timing->h_front_porch = 0; 98 timing->v_back_porch += timing->v_front_porch; 99 timing->v_front_porch = 0; 100 } 101 102 timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); 103 104 /* 105 * for DP, divide the horizonal parameters by 2 when 106 * widebus is enabled 107 */ 108 if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) { 109 timing->width = timing->width >> 1; 110 timing->xres = timing->xres >> 1; 111 timing->h_back_porch = timing->h_back_porch >> 1; 112 timing->h_front_porch = timing->h_front_porch >> 1; 113 timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; 114 } 115 } 116 117 static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) 118 { 119 u32 active = timing->xres; 120 u32 inactive = 121 timing->h_back_porch + timing->h_front_porch + 122 timing->hsync_pulse_width; 123 return active + inactive; 124 } 125 126 static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing) 127 { 128 u32 active = timing->yres; 129 u32 inactive = 130 timing->v_back_porch + timing->v_front_porch + 131 timing->vsync_pulse_width; 132 return active + inactive; 133 } 134 135 /* 136 * programmable_fetch_get_num_lines: 137 * Number of fetch lines in vertical front porch 138 * @timing: Pointer to the intf timing information for the requested mode 139 * 140 * Returns the number of fetch lines in vertical front porch at which mdp 141 * can start fetching the next frame. 142 * 143 * Number of needed prefetch lines is anything that cannot be absorbed in the 144 * start of frame time (back porch + vsync pulse width). 145 * 146 * Some panels have very large VFP, however we only need a total number of 147 * lines based on the chip worst case latencies. 148 */ 149 static u32 programmable_fetch_get_num_lines( 150 struct dpu_encoder_phys *phys_enc, 151 const struct dpu_hw_intf_timing_params *timing) 152 { 153 u32 worst_case_needed_lines = 154 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; 155 u32 start_of_frame_lines = 156 timing->v_back_porch + timing->vsync_pulse_width; 157 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines; 158 u32 actual_vfp_lines = 0; 159 160 /* Fetch must be outside active lines, otherwise undefined. */ 161 if (start_of_frame_lines >= worst_case_needed_lines) { 162 DPU_DEBUG_VIDENC(phys_enc, 163 "prog fetch is not needed, large vbp+vsw\n"); 164 actual_vfp_lines = 0; 165 } else if (timing->v_front_porch < needed_vfp_lines) { 166 /* Warn fetch needed, but not enough porch in panel config */ 167 pr_warn_once 168 ("low vbp+vfp may lead to perf issues in some cases\n"); 169 DPU_DEBUG_VIDENC(phys_enc, 170 "less vfp than fetch req, using entire vfp\n"); 171 actual_vfp_lines = timing->v_front_porch; 172 } else { 173 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n"); 174 actual_vfp_lines = needed_vfp_lines; 175 } 176 177 DPU_DEBUG_VIDENC(phys_enc, 178 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n", 179 timing->v_front_porch, timing->v_back_porch, 180 timing->vsync_pulse_width); 181 DPU_DEBUG_VIDENC(phys_enc, 182 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n", 183 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines); 184 185 return actual_vfp_lines; 186 } 187 188 /* 189 * programmable_fetch_config: Programs HW to prefetch lines by offsetting 190 * the start of fetch into the vertical front porch for cases where the 191 * vsync pulse width and vertical back porch time is insufficient 192 * 193 * Gets # of lines to pre-fetch, then calculate VSYNC counter value. 194 * HW layer requires VSYNC counter of first pixel of tgt VFP line. 195 * 196 * @timing: Pointer to the intf timing information for the requested mode 197 */ 198 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, 199 const struct dpu_hw_intf_timing_params *timing) 200 { 201 struct dpu_hw_intf_prog_fetch f = { 0 }; 202 u32 vfp_fetch_lines = 0; 203 u32 horiz_total = 0; 204 u32 vert_total = 0; 205 u32 vfp_fetch_start_vsync_counter = 0; 206 unsigned long lock_flags; 207 208 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) 209 return; 210 211 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); 212 if (vfp_fetch_lines) { 213 vert_total = get_vertical_total(timing); 214 horiz_total = get_horizontal_total(timing); 215 vfp_fetch_start_vsync_counter = 216 (vert_total - vfp_fetch_lines) * horiz_total + 1; 217 f.enable = 1; 218 f.fetch_start = vfp_fetch_start_vsync_counter; 219 } 220 221 DPU_DEBUG_VIDENC(phys_enc, 222 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n", 223 vfp_fetch_lines, vfp_fetch_start_vsync_counter); 224 225 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 226 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); 227 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 228 } 229 230 static void dpu_encoder_phys_vid_setup_timing_engine( 231 struct dpu_encoder_phys *phys_enc) 232 { 233 struct drm_display_mode mode; 234 struct dpu_hw_intf_timing_params timing_params = { 0 }; 235 const struct dpu_format *fmt = NULL; 236 u32 fmt_fourcc = DRM_FORMAT_RGB888; 237 unsigned long lock_flags; 238 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 239 240 drm_mode_init(&mode, &phys_enc->cached_mode); 241 242 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { 243 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); 244 return; 245 } 246 247 if (!phys_enc->hw_intf->ops.setup_timing_gen) { 248 DPU_ERROR("timing engine setup is not supported\n"); 249 return; 250 } 251 252 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); 253 drm_mode_debug_printmodeline(&mode); 254 255 if (phys_enc->split_role != ENC_ROLE_SOLO) { 256 mode.hdisplay >>= 1; 257 mode.htotal >>= 1; 258 mode.hsync_start >>= 1; 259 mode.hsync_end >>= 1; 260 261 DPU_DEBUG_VIDENC(phys_enc, 262 "split_role %d, halve horizontal %d %d %d %d\n", 263 phys_enc->split_role, 264 mode.hdisplay, mode.htotal, 265 mode.hsync_start, mode.hsync_end); 266 } 267 268 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); 269 270 fmt = dpu_get_dpu_format(fmt_fourcc); 271 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); 272 273 intf_cfg.intf = phys_enc->hw_intf->idx; 274 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; 275 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 276 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 277 intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); 278 if (phys_enc->hw_pp->merge_3d) 279 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 280 281 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 282 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, 283 &timing_params, fmt); 284 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); 285 286 /* setup which pp blk will connect to this intf */ 287 if (phys_enc->hw_intf->ops.bind_pingpong_blk) 288 phys_enc->hw_intf->ops.bind_pingpong_blk( 289 phys_enc->hw_intf, 290 phys_enc->hw_pp->idx); 291 292 if (phys_enc->hw_pp->merge_3d) 293 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); 294 295 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 296 297 programmable_fetch_config(phys_enc, &timing_params); 298 } 299 300 static void dpu_encoder_phys_vid_vblank_irq(void *arg) 301 { 302 struct dpu_encoder_phys *phys_enc = arg; 303 struct dpu_hw_ctl *hw_ctl; 304 unsigned long lock_flags; 305 u32 flush_register = 0; 306 307 hw_ctl = phys_enc->hw_ctl; 308 309 DPU_ATRACE_BEGIN("vblank_irq"); 310 311 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc); 312 313 atomic_read(&phys_enc->pending_kickoff_cnt); 314 315 /* 316 * only decrement the pending flush count if we've actually flushed 317 * hardware. due to sw irq latency, vblank may have already happened 318 * so we need to double-check with hw that it accepted the flush bits 319 */ 320 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 321 if (hw_ctl->ops.get_flush_register) 322 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); 323 324 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) 325 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); 326 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 327 328 /* Signal any waiting atomic commit thread */ 329 wake_up_all(&phys_enc->pending_kickoff_wq); 330 331 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, 332 DPU_ENCODER_FRAME_EVENT_DONE); 333 334 DPU_ATRACE_END("vblank_irq"); 335 } 336 337 static void dpu_encoder_phys_vid_underrun_irq(void *arg) 338 { 339 struct dpu_encoder_phys *phys_enc = arg; 340 341 dpu_encoder_underrun_callback(phys_enc->parent, phys_enc); 342 } 343 344 static bool dpu_encoder_phys_vid_needs_single_flush( 345 struct dpu_encoder_phys *phys_enc) 346 { 347 return phys_enc->split_role != ENC_ROLE_SOLO; 348 } 349 350 static void dpu_encoder_phys_vid_atomic_mode_set( 351 struct dpu_encoder_phys *phys_enc, 352 struct drm_crtc_state *crtc_state, 353 struct drm_connector_state *conn_state) 354 { 355 phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; 356 357 phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; 358 } 359 360 static int dpu_encoder_phys_vid_control_vblank_irq( 361 struct dpu_encoder_phys *phys_enc, 362 bool enable) 363 { 364 int ret = 0; 365 int refcount; 366 367 refcount = atomic_read(&phys_enc->vblank_refcount); 368 369 /* Slave encoders don't report vblank */ 370 if (!dpu_encoder_phys_vid_is_master(phys_enc)) 371 goto end; 372 373 /* protect against negative */ 374 if (!enable && refcount == 0) { 375 ret = -EINVAL; 376 goto end; 377 } 378 379 DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, 380 atomic_read(&phys_enc->vblank_refcount)); 381 382 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) 383 ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, 384 phys_enc->irq[INTR_IDX_VSYNC], 385 dpu_encoder_phys_vid_vblank_irq, 386 phys_enc); 387 else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0) 388 ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 389 phys_enc->irq[INTR_IDX_VSYNC]); 390 391 end: 392 if (ret) { 393 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n", 394 DRMID(phys_enc->parent), 395 phys_enc->hw_intf->idx - INTF_0, ret, enable, 396 refcount); 397 } 398 return ret; 399 } 400 401 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) 402 { 403 struct dpu_hw_ctl *ctl; 404 405 ctl = phys_enc->hw_ctl; 406 407 DPU_DEBUG_VIDENC(phys_enc, "\n"); 408 409 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) 410 return; 411 412 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); 413 414 dpu_encoder_phys_vid_setup_timing_engine(phys_enc); 415 416 /* 417 * For single flush cases (dual-ctl or pp-split), skip setting the 418 * flush bit for the slave intf, since both intfs use same ctl 419 * and HW will only flush the master. 420 */ 421 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) && 422 !dpu_encoder_phys_vid_is_master(phys_enc)) 423 goto skip_flush; 424 425 ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); 426 if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) 427 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); 428 429 skip_flush: 430 DPU_DEBUG_VIDENC(phys_enc, 431 "update pending flush ctl %d intf %d\n", 432 ctl->idx - CTL_0, phys_enc->hw_intf->idx); 433 434 atomic_set(&phys_enc->underrun_cnt, 0); 435 436 /* ctl_flush & timing engine enable will be triggered by framework */ 437 if (phys_enc->enable_state == DPU_ENC_DISABLED) 438 phys_enc->enable_state = DPU_ENC_ENABLING; 439 } 440 441 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) 442 { 443 DPU_DEBUG_VIDENC(phys_enc, "\n"); 444 kfree(phys_enc); 445 } 446 447 static int dpu_encoder_phys_vid_wait_for_vblank( 448 struct dpu_encoder_phys *phys_enc) 449 { 450 struct dpu_encoder_wait_info wait_info; 451 int ret; 452 453 wait_info.wq = &phys_enc->pending_kickoff_wq; 454 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; 455 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; 456 457 if (!dpu_encoder_phys_vid_is_master(phys_enc)) { 458 return 0; 459 } 460 461 /* Wait for kickoff to complete */ 462 ret = dpu_encoder_helper_wait_for_irq(phys_enc, 463 phys_enc->irq[INTR_IDX_VSYNC], 464 dpu_encoder_phys_vid_vblank_irq, 465 &wait_info); 466 467 if (ret == -ETIMEDOUT) { 468 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC); 469 } 470 471 return ret; 472 } 473 474 static int dpu_encoder_phys_vid_wait_for_commit_done( 475 struct dpu_encoder_phys *phys_enc) 476 { 477 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; 478 int ret; 479 480 if (!hw_ctl) 481 return 0; 482 483 ret = wait_event_timeout(phys_enc->pending_kickoff_wq, 484 (hw_ctl->ops.get_flush_register(hw_ctl) == 0), 485 msecs_to_jiffies(50)); 486 if (ret <= 0) { 487 DPU_ERROR("vblank timeout\n"); 488 return -ETIMEDOUT; 489 } 490 491 return 0; 492 } 493 494 static void dpu_encoder_phys_vid_prepare_for_kickoff( 495 struct dpu_encoder_phys *phys_enc) 496 { 497 struct dpu_hw_ctl *ctl; 498 int rc; 499 struct drm_encoder *drm_enc; 500 501 drm_enc = phys_enc->parent; 502 503 ctl = phys_enc->hw_ctl; 504 if (!ctl->ops.wait_reset_status) 505 return; 506 507 /* 508 * hw supports hardware initiated ctl reset, so before we kickoff a new 509 * frame, need to check and wait for hw initiated ctl reset completion 510 */ 511 rc = ctl->ops.wait_reset_status(ctl); 512 if (rc) { 513 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n", 514 ctl->idx, rc); 515 msm_disp_snapshot_state(drm_enc->dev); 516 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 517 phys_enc->irq[INTR_IDX_VSYNC]); 518 } 519 } 520 521 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) 522 { 523 unsigned long lock_flags; 524 int ret; 525 struct dpu_hw_intf_status intf_status = {0}; 526 527 if (!phys_enc->parent || !phys_enc->parent->dev) { 528 DPU_ERROR("invalid encoder/device\n"); 529 return; 530 } 531 532 if (!phys_enc->hw_intf) { 533 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n", 534 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL); 535 return; 536 } 537 538 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) 539 return; 540 541 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 542 DPU_ERROR("already disabled\n"); 543 return; 544 } 545 546 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 547 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); 548 if (dpu_encoder_phys_vid_is_master(phys_enc)) 549 dpu_encoder_phys_inc_pending(phys_enc); 550 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 551 552 /* 553 * Wait for a vsync so we know the ENABLE=0 latched before 554 * the (connector) source of the vsync's gets disabled, 555 * otherwise we end up in a funny state if we re-enable 556 * before the disable latches, which results that some of 557 * the settings changes for the new modeset (like new 558 * scanout buffer) don't latch properly.. 559 */ 560 if (dpu_encoder_phys_vid_is_master(phys_enc)) { 561 ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); 562 if (ret) { 563 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 564 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", 565 DRMID(phys_enc->parent), 566 phys_enc->hw_intf->idx - INTF_0, ret); 567 } 568 } 569 570 if (phys_enc->hw_intf && phys_enc->hw_intf->ops.get_status) 571 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &intf_status); 572 573 /* 574 * Wait for a vsync if timing en status is on after timing engine 575 * is disabled. 576 */ 577 if (intf_status.is_en && dpu_encoder_phys_vid_is_master(phys_enc)) { 578 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 579 dpu_encoder_phys_inc_pending(phys_enc); 580 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 581 ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); 582 if (ret) { 583 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 584 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", 585 DRMID(phys_enc->parent), 586 phys_enc->hw_intf->idx - INTF_0, ret); 587 } 588 } 589 590 dpu_encoder_helper_phys_cleanup(phys_enc); 591 phys_enc->enable_state = DPU_ENC_DISABLED; 592 } 593 594 static void dpu_encoder_phys_vid_handle_post_kickoff( 595 struct dpu_encoder_phys *phys_enc) 596 { 597 unsigned long lock_flags; 598 599 /* 600 * Video mode must flush CTL before enabling timing engine 601 * Video encoders need to turn on their interfaces now 602 */ 603 if (phys_enc->enable_state == DPU_ENC_ENABLING) { 604 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), 605 phys_enc->hw_intf->idx - INTF_0); 606 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 607 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); 608 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 609 phys_enc->enable_state = DPU_ENC_ENABLED; 610 } 611 } 612 613 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, 614 bool enable) 615 { 616 int ret; 617 618 trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), 619 phys_enc->hw_intf->idx - INTF_0, 620 enable, 621 atomic_read(&phys_enc->vblank_refcount)); 622 623 if (enable) { 624 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); 625 if (WARN_ON(ret)) 626 return; 627 628 dpu_core_irq_register_callback(phys_enc->dpu_kms, 629 phys_enc->irq[INTR_IDX_UNDERRUN], 630 dpu_encoder_phys_vid_underrun_irq, 631 phys_enc); 632 } else { 633 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); 634 dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 635 phys_enc->irq[INTR_IDX_UNDERRUN]); 636 } 637 } 638 639 static int dpu_encoder_phys_vid_get_line_count( 640 struct dpu_encoder_phys *phys_enc) 641 { 642 if (!dpu_encoder_phys_vid_is_master(phys_enc)) 643 return -EINVAL; 644 645 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) 646 return -EINVAL; 647 648 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); 649 } 650 651 static int dpu_encoder_phys_vid_get_frame_count( 652 struct dpu_encoder_phys *phys_enc) 653 { 654 struct dpu_hw_intf_status s = {0}; 655 u32 fetch_start = 0; 656 struct drm_display_mode mode; 657 658 drm_mode_init(&mode, &phys_enc->cached_mode); 659 660 if (!dpu_encoder_phys_vid_is_master(phys_enc)) 661 return -EINVAL; 662 663 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status) 664 return -EINVAL; 665 666 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s); 667 668 if (s.is_prog_fetch_en && s.is_en) { 669 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay); 670 if ((s.line_count > fetch_start) && 671 (s.line_count <= mode.vtotal)) 672 return s.frame_count + 1; 673 } 674 675 return s.frame_count; 676 } 677 678 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) 679 { 680 ops->is_master = dpu_encoder_phys_vid_is_master; 681 ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; 682 ops->enable = dpu_encoder_phys_vid_enable; 683 ops->disable = dpu_encoder_phys_vid_disable; 684 ops->destroy = dpu_encoder_phys_vid_destroy; 685 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; 686 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; 687 ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; 688 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank; 689 ops->irq_control = dpu_encoder_phys_vid_irq_control; 690 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; 691 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; 692 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; 693 ops->get_line_count = dpu_encoder_phys_vid_get_line_count; 694 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; 695 } 696 697 struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 698 struct dpu_enc_phys_init_params *p) 699 { 700 struct dpu_encoder_phys *phys_enc = NULL; 701 702 if (!p) { 703 DPU_ERROR("failed to create encoder due to invalid parameter\n"); 704 return ERR_PTR(-EINVAL); 705 } 706 707 phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL); 708 if (!phys_enc) { 709 DPU_ERROR("failed to create encoder due to memory allocation error\n"); 710 return ERR_PTR(-ENOMEM); 711 } 712 713 DPU_DEBUG_VIDENC(phys_enc, "\n"); 714 715 dpu_encoder_phys_init(phys_enc, p); 716 717 dpu_encoder_phys_vid_init_ops(&phys_enc->ops); 718 phys_enc->intf_mode = INTF_MODE_VIDEO; 719 720 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx); 721 722 return phys_enc; 723 } 724