1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8998_MASK \ 25 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 26 27 #define VIG_SDM845_MASK \ 28 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 29 30 #define VIG_SDM845_MASK_SDMA \ 31 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 32 33 #define VIG_SC7180_MASK \ 34 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 35 36 #define VIG_SC7180_MASK_SDMA \ 37 (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 38 39 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 40 41 #define DMA_MSM8998_MASK \ 42 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 43 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 44 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 45 46 #define VIG_SC7280_MASK \ 47 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 48 49 #define VIG_SC7280_MASK_SDMA \ 50 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 51 52 #define DMA_SDM845_MASK \ 53 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 54 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 55 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 56 57 #define DMA_CURSOR_SDM845_MASK \ 58 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 59 60 #define DMA_SDM845_MASK_SDMA \ 61 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 62 63 #define DMA_CURSOR_SDM845_MASK_SDMA \ 64 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 65 66 #define DMA_CURSOR_MSM8998_MASK \ 67 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 68 69 #define MIXER_MSM8998_MASK \ 70 (BIT(DPU_MIXER_SOURCESPLIT)) 71 72 #define MIXER_SDM845_MASK \ 73 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 74 75 #define MIXER_QCM2290_MASK \ 76 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 77 78 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) 79 80 #define PINGPONG_SDM845_SPLIT_MASK \ 81 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 82 83 #define CTL_SC7280_MASK \ 84 (BIT(DPU_CTL_ACTIVE_CFG) | \ 85 BIT(DPU_CTL_FETCH_ACTIVE) | \ 86 BIT(DPU_CTL_VM_CFG) | \ 87 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 88 89 #define CTL_SM8550_MASK \ 90 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 91 92 #define MERGE_3D_SM8150_MASK (0) 93 94 #define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) 95 96 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 97 98 #define INTF_SDM845_MASK (0) 99 100 #define INTF_SC7180_MASK \ 101 (BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) | BIT(DPU_INTF_STATUS_SUPPORTED)) 102 103 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) 104 105 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 106 BIT(DPU_WB_UBWC) | \ 107 BIT(DPU_WB_YUV_CONFIG) | \ 108 BIT(DPU_WB_PIPE_ALPHA) | \ 109 BIT(DPU_WB_XY_ROI_OFFSET) | \ 110 BIT(DPU_WB_QOS) | \ 111 BIT(DPU_WB_QOS_8LVL) | \ 112 BIT(DPU_WB_CDP) | \ 113 BIT(DPU_WB_INPUT_CTRL)) 114 115 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 116 #define DEFAULT_DPU_LINE_WIDTH 2048 117 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 118 119 #define MAX_HORZ_DECIMATION 4 120 #define MAX_VERT_DECIMATION 4 121 122 #define MAX_UPSCALE_RATIO 20 123 #define MAX_DOWNSCALE_RATIO 4 124 #define SSPP_UNITY_SCALE 1 125 126 #define STRCAT(X, Y) (X Y) 127 128 static const uint32_t plane_formats[] = { 129 DRM_FORMAT_ARGB8888, 130 DRM_FORMAT_ABGR8888, 131 DRM_FORMAT_RGBA8888, 132 DRM_FORMAT_BGRA8888, 133 DRM_FORMAT_XRGB8888, 134 DRM_FORMAT_RGBX8888, 135 DRM_FORMAT_BGRX8888, 136 DRM_FORMAT_XBGR8888, 137 DRM_FORMAT_ARGB2101010, 138 DRM_FORMAT_XRGB2101010, 139 DRM_FORMAT_RGB888, 140 DRM_FORMAT_BGR888, 141 DRM_FORMAT_RGB565, 142 DRM_FORMAT_BGR565, 143 DRM_FORMAT_ARGB1555, 144 DRM_FORMAT_ABGR1555, 145 DRM_FORMAT_RGBA5551, 146 DRM_FORMAT_BGRA5551, 147 DRM_FORMAT_XRGB1555, 148 DRM_FORMAT_XBGR1555, 149 DRM_FORMAT_RGBX5551, 150 DRM_FORMAT_BGRX5551, 151 DRM_FORMAT_ARGB4444, 152 DRM_FORMAT_ABGR4444, 153 DRM_FORMAT_RGBA4444, 154 DRM_FORMAT_BGRA4444, 155 DRM_FORMAT_XRGB4444, 156 DRM_FORMAT_XBGR4444, 157 DRM_FORMAT_RGBX4444, 158 DRM_FORMAT_BGRX4444, 159 }; 160 161 static const uint32_t plane_formats_yuv[] = { 162 DRM_FORMAT_ARGB8888, 163 DRM_FORMAT_ABGR8888, 164 DRM_FORMAT_RGBA8888, 165 DRM_FORMAT_BGRX8888, 166 DRM_FORMAT_BGRA8888, 167 DRM_FORMAT_ARGB2101010, 168 DRM_FORMAT_XRGB2101010, 169 DRM_FORMAT_XRGB8888, 170 DRM_FORMAT_XBGR8888, 171 DRM_FORMAT_RGBX8888, 172 DRM_FORMAT_RGB888, 173 DRM_FORMAT_BGR888, 174 DRM_FORMAT_RGB565, 175 DRM_FORMAT_BGR565, 176 DRM_FORMAT_ARGB1555, 177 DRM_FORMAT_ABGR1555, 178 DRM_FORMAT_RGBA5551, 179 DRM_FORMAT_BGRA5551, 180 DRM_FORMAT_XRGB1555, 181 DRM_FORMAT_XBGR1555, 182 DRM_FORMAT_RGBX5551, 183 DRM_FORMAT_BGRX5551, 184 DRM_FORMAT_ARGB4444, 185 DRM_FORMAT_ABGR4444, 186 DRM_FORMAT_RGBA4444, 187 DRM_FORMAT_BGRA4444, 188 DRM_FORMAT_XRGB4444, 189 DRM_FORMAT_XBGR4444, 190 DRM_FORMAT_RGBX4444, 191 DRM_FORMAT_BGRX4444, 192 193 DRM_FORMAT_P010, 194 DRM_FORMAT_NV12, 195 DRM_FORMAT_NV21, 196 DRM_FORMAT_NV16, 197 DRM_FORMAT_NV61, 198 DRM_FORMAT_VYUY, 199 DRM_FORMAT_UYVY, 200 DRM_FORMAT_YUYV, 201 DRM_FORMAT_YVYU, 202 DRM_FORMAT_YUV420, 203 DRM_FORMAT_YVU420, 204 }; 205 206 static const u32 rotation_v2_formats[] = { 207 DRM_FORMAT_NV12, 208 /* TODO add formats after validation */ 209 }; 210 211 static const uint32_t wb2_formats[] = { 212 DRM_FORMAT_RGB565, 213 DRM_FORMAT_BGR565, 214 DRM_FORMAT_RGB888, 215 DRM_FORMAT_ARGB8888, 216 DRM_FORMAT_RGBA8888, 217 DRM_FORMAT_ABGR8888, 218 DRM_FORMAT_XRGB8888, 219 DRM_FORMAT_RGBX8888, 220 DRM_FORMAT_XBGR8888, 221 DRM_FORMAT_ARGB1555, 222 DRM_FORMAT_RGBA5551, 223 DRM_FORMAT_XRGB1555, 224 DRM_FORMAT_RGBX5551, 225 DRM_FORMAT_ARGB4444, 226 DRM_FORMAT_RGBA4444, 227 DRM_FORMAT_RGBX4444, 228 DRM_FORMAT_XRGB4444, 229 DRM_FORMAT_BGR565, 230 DRM_FORMAT_BGR888, 231 DRM_FORMAT_ABGR8888, 232 DRM_FORMAT_BGRA8888, 233 DRM_FORMAT_BGRX8888, 234 DRM_FORMAT_XBGR8888, 235 DRM_FORMAT_ABGR1555, 236 DRM_FORMAT_BGRA5551, 237 DRM_FORMAT_XBGR1555, 238 DRM_FORMAT_BGRX5551, 239 DRM_FORMAT_ABGR4444, 240 DRM_FORMAT_BGRA4444, 241 DRM_FORMAT_BGRX4444, 242 DRM_FORMAT_XBGR4444, 243 }; 244 245 /************************************************************* 246 * SSPP sub blocks config 247 *************************************************************/ 248 249 /* SSPP common configuration */ 250 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \ 251 { \ 252 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 253 .maxupscale = MAX_UPSCALE_RATIO, \ 254 .smart_dma_priority = sdma_pri, \ 255 .src_blk = {.name = STRCAT("sspp_src_", num), \ 256 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 257 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 258 .id = qseed_ver, \ 259 .base = 0xa00, .len = 0xa0,}, \ 260 .csc_blk = {.name = STRCAT("sspp_csc", num), \ 261 .id = DPU_SSPP_CSC_10BIT, \ 262 .base = 0x1a00, .len = 0x100,}, \ 263 .format_list = plane_formats_yuv, \ 264 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 265 .virt_format_list = plane_formats, \ 266 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 267 .rotation_cfg = NULL, \ 268 } 269 270 #define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \ 271 { \ 272 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 273 .maxupscale = MAX_UPSCALE_RATIO, \ 274 .smart_dma_priority = sdma_pri, \ 275 .src_blk = {.name = STRCAT("sspp_src_", num), \ 276 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 277 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 278 .id = qseed_ver, \ 279 .base = 0xa00, .len = 0xa0,}, \ 280 .csc_blk = {.name = STRCAT("sspp_csc", num), \ 281 .id = DPU_SSPP_CSC_10BIT, \ 282 .base = 0x1a00, .len = 0x100,}, \ 283 .format_list = plane_formats_yuv, \ 284 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 285 .virt_format_list = plane_formats, \ 286 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 287 .rotation_cfg = rot_cfg, \ 288 } 289 290 #define _DMA_SBLK(num, sdma_pri) \ 291 { \ 292 .maxdwnscale = SSPP_UNITY_SCALE, \ 293 .maxupscale = SSPP_UNITY_SCALE, \ 294 .smart_dma_priority = sdma_pri, \ 295 .src_blk = {.name = STRCAT("sspp_src_", num), \ 296 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 297 .format_list = plane_formats, \ 298 .num_formats = ARRAY_SIZE(plane_formats), \ 299 .virt_format_list = plane_formats, \ 300 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 301 } 302 303 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = 304 _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); 305 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = 306 _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); 307 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = 308 _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); 309 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = 310 _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); 311 312 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 313 .rot_maxheight = 1088, 314 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 315 .rot_format_list = rotation_v2_formats, 316 }; 317 318 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 319 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); 320 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 321 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); 322 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 323 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); 324 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 325 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); 326 327 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); 328 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); 329 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); 330 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); 331 332 #define SSPP_BLK(_name, _id, _base, _len, _features, \ 333 _sblk, _xinid, _type, _clkctrl) \ 334 { \ 335 .name = _name, .id = _id, \ 336 .base = _base, .len = _len, \ 337 .features = _features, \ 338 .sblk = &_sblk, \ 339 .xin_id = _xinid, \ 340 .type = _type, \ 341 .clk_ctrl = _clkctrl \ 342 } 343 344 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 345 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); 346 347 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 348 _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); 349 350 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = 351 _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); 352 353 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = 354 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); 355 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = 356 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4); 357 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = 358 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4); 359 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = 360 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); 361 362 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = 363 _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4); 364 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = 365 _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED4); 366 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = 367 _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4); 368 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = 369 _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED4); 370 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5); 371 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); 372 373 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ 374 { \ 375 .maxdwnscale = SSPP_UNITY_SCALE, \ 376 .maxupscale = SSPP_UNITY_SCALE, \ 377 .smart_dma_priority = sdma_pri, \ 378 .src_blk = {.name = STRCAT("sspp_src_", num), \ 379 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 380 .format_list = plane_formats_yuv, \ 381 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 382 .virt_format_list = plane_formats, \ 383 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 384 } 385 386 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2); 387 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); 388 389 /************************************************************* 390 * MIXER sub blocks config 391 *************************************************************/ 392 393 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ 394 { \ 395 .name = _name, .id = _id, \ 396 .base = _base, .len = 0x320, \ 397 .features = _fmask, \ 398 .sblk = _sblk, \ 399 .pingpong = _pp, \ 400 .lm_pair_mask = (1 << _lmpair), \ 401 .dspp = _dspp \ 402 } 403 404 /* MSM8998 */ 405 406 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 407 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 408 .maxblendstages = 7, /* excluding base layer */ 409 .blendstage_base = { /* offsets relative to mixer base */ 410 0x20, 0x50, 0x80, 0xb0, 0x230, 411 0x260, 0x290 412 }, 413 }; 414 415 /* SDM845 */ 416 417 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 418 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 419 .maxblendstages = 11, /* excluding base layer */ 420 .blendstage_base = { /* offsets relative to mixer base */ 421 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 422 0xb0, 0xc8, 0xe0, 0xf8, 0x110 423 }, 424 }; 425 426 /* SC7180 */ 427 428 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 429 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 430 .maxblendstages = 7, /* excluding base layer */ 431 .blendstage_base = { /* offsets relative to mixer base */ 432 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 433 }, 434 }; 435 436 /* QCM2290 */ 437 438 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 439 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 440 .maxblendstages = 4, /* excluding base layer */ 441 .blendstage_base = { /* offsets relative to mixer base */ 442 0x20, 0x38, 0x50, 0x68 443 }, 444 }; 445 446 /************************************************************* 447 * DSPP sub blocks config 448 *************************************************************/ 449 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 450 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 451 .len = 0x90, .version = 0x10007}, 452 .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, 453 .len = 0x90, .version = 0x10007}, 454 }; 455 456 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { 457 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 458 .len = 0x90, .version = 0x10000}, 459 }; 460 461 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { 462 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 463 .len = 0x90, .version = 0x40000}, 464 }; 465 466 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \ 467 {\ 468 .name = _name, .id = _id, \ 469 .base = _base, .len = 0x1800, \ 470 .features = _mask, \ 471 .sblk = _sblk \ 472 } 473 474 /************************************************************* 475 * PINGPONG sub blocks config 476 *************************************************************/ 477 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 478 .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 479 .version = 0x1}, 480 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 481 .len = 0x20, .version = 0x10000}, 482 }; 483 484 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 485 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 486 .len = 0x20, .version = 0x10000}, 487 }; 488 489 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 490 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, 491 .len = 0x20, .version = 0x20000}, 492 }; 493 494 #define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 495 {\ 496 .name = _name, .id = _id, \ 497 .base = _base, .len = 0, \ 498 .features = BIT(DPU_PINGPONG_DITHER), \ 499 .merge_3d = _merge_3d, \ 500 .sblk = &_sblk, \ 501 .intr_done = _done, \ 502 .intr_rdptr = _rdptr, \ 503 } 504 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 505 {\ 506 .name = _name, .id = _id, \ 507 .base = _base, .len = 0xd4, \ 508 .features = PINGPONG_SDM845_SPLIT_MASK, \ 509 .merge_3d = _merge_3d, \ 510 .sblk = &_sblk, \ 511 .intr_done = _done, \ 512 .intr_rdptr = _rdptr, \ 513 } 514 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 515 {\ 516 .name = _name, .id = _id, \ 517 .base = _base, .len = 0xd4, \ 518 .features = PINGPONG_SDM845_MASK, \ 519 .merge_3d = _merge_3d, \ 520 .sblk = &_sblk, \ 521 .intr_done = _done, \ 522 .intr_rdptr = _rdptr, \ 523 } 524 525 /************************************************************* 526 * MERGE_3D sub blocks config 527 *************************************************************/ 528 #define MERGE_3D_BLK(_name, _id, _base) \ 529 {\ 530 .name = _name, .id = _id, \ 531 .base = _base, .len = 0x100, \ 532 .features = MERGE_3D_SM8150_MASK, \ 533 .sblk = NULL \ 534 } 535 536 /************************************************************* 537 * DSC sub blocks config 538 *************************************************************/ 539 #define DSC_BLK(_name, _id, _base, _features) \ 540 {\ 541 .name = _name, .id = _id, \ 542 .base = _base, .len = 0x140, \ 543 .features = _features, \ 544 } 545 546 /************************************************************* 547 * INTF sub blocks config 548 *************************************************************/ 549 #define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ 550 {\ 551 .name = _name, .id = _id, \ 552 .base = _base, .len = _len, \ 553 .features = _features, \ 554 .type = _type, \ 555 .controller_id = _ctrl_id, \ 556 .prog_fetch_lines_worst_case = _progfetch, \ 557 .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \ 558 .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ 559 } 560 561 /************************************************************* 562 * Writeback blocks config 563 *************************************************************/ 564 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \ 565 __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \ 566 { \ 567 .name = _name, .id = _id, \ 568 .base = _base, .len = 0x2c8, \ 569 .features = _features, \ 570 .format_list = wb2_formats, \ 571 .num_formats = ARRAY_SIZE(wb2_formats), \ 572 .clk_ctrl = _clk_ctrl, \ 573 .xin_id = __xin_id, \ 574 .vbif_idx = vbif_id, \ 575 .maxlinewidth = _max_linewidth, \ 576 .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \ 577 } 578 579 /************************************************************* 580 * VBIF sub blocks config 581 *************************************************************/ 582 /* VBIF QOS remap */ 583 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 584 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 585 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 586 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 587 588 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 589 { 590 .pps = 1920 * 1080 * 30, 591 .ot_limit = 2, 592 }, 593 { 594 .pps = 1920 * 1080 * 60, 595 .ot_limit = 4, 596 }, 597 { 598 .pps = 3840 * 2160 * 30, 599 .ot_limit = 16, 600 }, 601 }; 602 603 static const struct dpu_vbif_cfg msm8998_vbif[] = { 604 { 605 .name = "vbif_rt", .id = VBIF_RT, 606 .base = 0, .len = 0x1040, 607 .default_ot_rd_limit = 32, 608 .default_ot_wr_limit = 32, 609 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 610 .xin_halt_timeout = 0x4000, 611 .qos_rp_remap_size = 0x20, 612 .dynamic_ot_rd_tbl = { 613 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 614 .cfg = msm8998_ot_rdwr_cfg, 615 }, 616 .dynamic_ot_wr_tbl = { 617 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 618 .cfg = msm8998_ot_rdwr_cfg, 619 }, 620 .qos_rt_tbl = { 621 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 622 .priority_lvl = msm8998_rt_pri_lvl, 623 }, 624 .qos_nrt_tbl = { 625 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 626 .priority_lvl = msm8998_nrt_pri_lvl, 627 }, 628 .memtype_count = 14, 629 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 630 }, 631 }; 632 633 static const struct dpu_vbif_cfg sdm845_vbif[] = { 634 { 635 .name = "vbif_rt", .id = VBIF_RT, 636 .base = 0, .len = 0x1040, 637 .features = BIT(DPU_VBIF_QOS_REMAP), 638 .xin_halt_timeout = 0x4000, 639 .qos_rp_remap_size = 0x40, 640 .qos_rt_tbl = { 641 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 642 .priority_lvl = sdm845_rt_pri_lvl, 643 }, 644 .qos_nrt_tbl = { 645 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 646 .priority_lvl = sdm845_nrt_pri_lvl, 647 }, 648 .memtype_count = 14, 649 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 650 }, 651 }; 652 653 static const struct dpu_reg_dma_cfg sc8280xp_regdma = { 654 .base = 0x0, 655 .version = 0x00020000, 656 .trigger_sel_off = 0x119c, 657 .xin_id = 7, 658 .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 659 }; 660 661 static const struct dpu_reg_dma_cfg sdm845_regdma = { 662 .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c 663 }; 664 665 static const struct dpu_reg_dma_cfg sm8150_regdma = { 666 .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c 667 }; 668 669 static const struct dpu_reg_dma_cfg sm8250_regdma = { 670 .base = 0x0, 671 .version = 0x00010002, 672 .trigger_sel_off = 0x119c, 673 .xin_id = 7, 674 .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 675 }; 676 677 static const struct dpu_reg_dma_cfg sm8350_regdma = { 678 .base = 0x400, 679 .version = 0x00020000, 680 .trigger_sel_off = 0x119c, 681 .xin_id = 7, 682 .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 683 }; 684 685 static const struct dpu_reg_dma_cfg sm8450_regdma = { 686 .base = 0x0, 687 .version = 0x00020000, 688 .trigger_sel_off = 0x119c, 689 .xin_id = 7, 690 .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 691 }; 692 693 /************************************************************* 694 * PERF data config 695 *************************************************************/ 696 697 /* SSPP QOS LUTs */ 698 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 699 {.fl = 4, .lut = 0x1b}, 700 {.fl = 5, .lut = 0x5b}, 701 {.fl = 6, .lut = 0x15b}, 702 {.fl = 7, .lut = 0x55b}, 703 {.fl = 8, .lut = 0x155b}, 704 {.fl = 9, .lut = 0x555b}, 705 {.fl = 10, .lut = 0x1555b}, 706 {.fl = 11, .lut = 0x5555b}, 707 {.fl = 12, .lut = 0x15555b}, 708 {.fl = 0, .lut = 0x55555b} 709 }; 710 711 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 712 {.fl = 4, .lut = 0x357}, 713 {.fl = 5, .lut = 0x3357}, 714 {.fl = 6, .lut = 0x23357}, 715 {.fl = 7, .lut = 0x223357}, 716 {.fl = 8, .lut = 0x2223357}, 717 {.fl = 9, .lut = 0x22223357}, 718 {.fl = 10, .lut = 0x222223357}, 719 {.fl = 11, .lut = 0x2222223357}, 720 {.fl = 12, .lut = 0x22222223357}, 721 {.fl = 13, .lut = 0x222222223357}, 722 {.fl = 14, .lut = 0x1222222223357}, 723 {.fl = 0, .lut = 0x11222222223357} 724 }; 725 726 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 727 {.fl = 10, .lut = 0x1aaff}, 728 {.fl = 11, .lut = 0x5aaff}, 729 {.fl = 12, .lut = 0x15aaff}, 730 {.fl = 0, .lut = 0x55aaff}, 731 }; 732 733 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 734 {.fl = 0, .lut = 0x0011222222335777}, 735 }; 736 737 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 738 {.fl = 0, .lut = 0x0011222222223357 }, 739 }; 740 741 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 742 {.fl = 4, .lut = 0x0000000000000357 }, 743 }; 744 745 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 746 {.fl = 0, .lut = 0x0011222222335777}, 747 }; 748 749 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 750 {.fl = 10, .lut = 0x344556677}, 751 {.fl = 11, .lut = 0x3344556677}, 752 {.fl = 12, .lut = 0x23344556677}, 753 {.fl = 13, .lut = 0x223344556677}, 754 {.fl = 14, .lut = 0x1223344556677}, 755 {.fl = 0, .lut = 0x112233344556677}, 756 }; 757 758 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 759 {.fl = 0, .lut = 0x0011223344556677}, 760 }; 761 762 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 763 {.fl = 10, .lut = 0x0000000344556677}, 764 }; 765 766 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 767 {.fl = 0, .lut = 0x0}, 768 }; 769 770 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 771 {.fl = 0, .lut = 0x0}, 772 }; 773 774 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 775 {.fl = 0, .lut = 0x0}, 776 }; 777 778 /************************************************************* 779 * Hardware catalog 780 *************************************************************/ 781 782 #include "catalog/dpu_3_0_msm8998.h" 783 784 #include "catalog/dpu_4_0_sdm845.h" 785 786 #include "catalog/dpu_5_0_sm8150.h" 787 #include "catalog/dpu_5_1_sc8180x.h" 788 789 #include "catalog/dpu_6_0_sm8250.h" 790 #include "catalog/dpu_6_2_sc7180.h" 791 #include "catalog/dpu_6_3_sm6115.h" 792 #include "catalog/dpu_6_5_qcm2290.h" 793 794 #include "catalog/dpu_7_0_sm8350.h" 795 #include "catalog/dpu_7_2_sc7280.h" 796 797 #include "catalog/dpu_8_0_sc8280xp.h" 798 #include "catalog/dpu_8_1_sm8450.h" 799 800 #include "catalog/dpu_9_0_sm8550.h" 801