1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_BASE_MASK \ 16 (BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MASK \ 21 (VIG_BASE_MASK | \ 22 BIT(DPU_SSPP_CSC_10BIT)) 23 24 #define VIG_MSM8998_MASK \ 25 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 26 27 #define VIG_SDM845_MASK \ 28 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 29 30 #define VIG_SDM845_MASK_SDMA \ 31 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 32 33 #define VIG_SC7180_MASK \ 34 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 35 36 #define VIG_SM6125_MASK \ 37 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) 38 39 #define VIG_SC7180_MASK_SDMA \ 40 (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 41 42 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) 43 44 #define DMA_MSM8998_MASK \ 45 (BIT(DPU_SSPP_QOS) |\ 46 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 47 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 48 49 #define VIG_SC7280_MASK \ 50 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 51 52 #define VIG_SC7280_MASK_SDMA \ 53 (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 54 55 #define DMA_SDM845_MASK \ 56 (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 57 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 58 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 59 60 #define DMA_CURSOR_SDM845_MASK \ 61 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 62 63 #define DMA_SDM845_MASK_SDMA \ 64 (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 65 66 #define DMA_CURSOR_SDM845_MASK_SDMA \ 67 (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 68 69 #define DMA_CURSOR_MSM8998_MASK \ 70 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 71 72 #define MIXER_MSM8998_MASK \ 73 (BIT(DPU_MIXER_SOURCESPLIT)) 74 75 #define MIXER_SDM845_MASK \ 76 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 77 78 #define MIXER_QCM2290_MASK \ 79 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 80 81 #define PINGPONG_SDM845_MASK \ 82 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 83 84 #define PINGPONG_SDM845_TE2_MASK \ 85 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 86 87 #define PINGPONG_SM8150_MASK \ 88 (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) 89 90 #define CTL_SC7280_MASK \ 91 (BIT(DPU_CTL_ACTIVE_CFG) | \ 92 BIT(DPU_CTL_FETCH_ACTIVE) | \ 93 BIT(DPU_CTL_VM_CFG) | \ 94 BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) 95 96 #define CTL_SM8550_MASK \ 97 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 98 99 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 100 101 #define INTF_SC7180_MASK \ 102 (BIT(DPU_INTF_INPUT_CTRL) | \ 103 BIT(DPU_INTF_STATUS_SUPPORTED) | \ 104 BIT(DPU_DATA_HCTL_EN)) 105 106 #define INTF_SC7280_MASK (INTF_SC7180_MASK) 107 108 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 109 BIT(DPU_WB_UBWC) | \ 110 BIT(DPU_WB_YUV_CONFIG) | \ 111 BIT(DPU_WB_PIPE_ALPHA) | \ 112 BIT(DPU_WB_XY_ROI_OFFSET) | \ 113 BIT(DPU_WB_QOS) | \ 114 BIT(DPU_WB_QOS_8LVL) | \ 115 BIT(DPU_WB_CDP) | \ 116 BIT(DPU_WB_INPUT_CTRL)) 117 118 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 119 #define DEFAULT_DPU_LINE_WIDTH 2048 120 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 121 122 #define MAX_HORZ_DECIMATION 4 123 #define MAX_VERT_DECIMATION 4 124 125 #define MAX_UPSCALE_RATIO 20 126 #define MAX_DOWNSCALE_RATIO 4 127 #define SSPP_UNITY_SCALE 1 128 129 #define STRCAT(X, Y) (X Y) 130 131 static const uint32_t plane_formats[] = { 132 DRM_FORMAT_ARGB8888, 133 DRM_FORMAT_ABGR8888, 134 DRM_FORMAT_RGBA8888, 135 DRM_FORMAT_BGRA8888, 136 DRM_FORMAT_XRGB8888, 137 DRM_FORMAT_RGBX8888, 138 DRM_FORMAT_BGRX8888, 139 DRM_FORMAT_XBGR8888, 140 DRM_FORMAT_ARGB2101010, 141 DRM_FORMAT_XRGB2101010, 142 DRM_FORMAT_RGB888, 143 DRM_FORMAT_BGR888, 144 DRM_FORMAT_RGB565, 145 DRM_FORMAT_BGR565, 146 DRM_FORMAT_ARGB1555, 147 DRM_FORMAT_ABGR1555, 148 DRM_FORMAT_RGBA5551, 149 DRM_FORMAT_BGRA5551, 150 DRM_FORMAT_XRGB1555, 151 DRM_FORMAT_XBGR1555, 152 DRM_FORMAT_RGBX5551, 153 DRM_FORMAT_BGRX5551, 154 DRM_FORMAT_ARGB4444, 155 DRM_FORMAT_ABGR4444, 156 DRM_FORMAT_RGBA4444, 157 DRM_FORMAT_BGRA4444, 158 DRM_FORMAT_XRGB4444, 159 DRM_FORMAT_XBGR4444, 160 DRM_FORMAT_RGBX4444, 161 DRM_FORMAT_BGRX4444, 162 }; 163 164 static const uint32_t plane_formats_yuv[] = { 165 DRM_FORMAT_ARGB8888, 166 DRM_FORMAT_ABGR8888, 167 DRM_FORMAT_RGBA8888, 168 DRM_FORMAT_BGRX8888, 169 DRM_FORMAT_BGRA8888, 170 DRM_FORMAT_ARGB2101010, 171 DRM_FORMAT_XRGB2101010, 172 DRM_FORMAT_XRGB8888, 173 DRM_FORMAT_XBGR8888, 174 DRM_FORMAT_RGBX8888, 175 DRM_FORMAT_RGB888, 176 DRM_FORMAT_BGR888, 177 DRM_FORMAT_RGB565, 178 DRM_FORMAT_BGR565, 179 DRM_FORMAT_ARGB1555, 180 DRM_FORMAT_ABGR1555, 181 DRM_FORMAT_RGBA5551, 182 DRM_FORMAT_BGRA5551, 183 DRM_FORMAT_XRGB1555, 184 DRM_FORMAT_XBGR1555, 185 DRM_FORMAT_RGBX5551, 186 DRM_FORMAT_BGRX5551, 187 DRM_FORMAT_ARGB4444, 188 DRM_FORMAT_ABGR4444, 189 DRM_FORMAT_RGBA4444, 190 DRM_FORMAT_BGRA4444, 191 DRM_FORMAT_XRGB4444, 192 DRM_FORMAT_XBGR4444, 193 DRM_FORMAT_RGBX4444, 194 DRM_FORMAT_BGRX4444, 195 196 DRM_FORMAT_P010, 197 DRM_FORMAT_NV12, 198 DRM_FORMAT_NV21, 199 DRM_FORMAT_NV16, 200 DRM_FORMAT_NV61, 201 DRM_FORMAT_VYUY, 202 DRM_FORMAT_UYVY, 203 DRM_FORMAT_YUYV, 204 DRM_FORMAT_YVYU, 205 DRM_FORMAT_YUV420, 206 DRM_FORMAT_YVU420, 207 }; 208 209 static const u32 rotation_v2_formats[] = { 210 DRM_FORMAT_NV12, 211 /* TODO add formats after validation */ 212 }; 213 214 static const uint32_t wb2_formats[] = { 215 DRM_FORMAT_RGB565, 216 DRM_FORMAT_BGR565, 217 DRM_FORMAT_RGB888, 218 DRM_FORMAT_ARGB8888, 219 DRM_FORMAT_RGBA8888, 220 DRM_FORMAT_ABGR8888, 221 DRM_FORMAT_XRGB8888, 222 DRM_FORMAT_RGBX8888, 223 DRM_FORMAT_XBGR8888, 224 DRM_FORMAT_ARGB1555, 225 DRM_FORMAT_RGBA5551, 226 DRM_FORMAT_XRGB1555, 227 DRM_FORMAT_RGBX5551, 228 DRM_FORMAT_ARGB4444, 229 DRM_FORMAT_RGBA4444, 230 DRM_FORMAT_RGBX4444, 231 DRM_FORMAT_XRGB4444, 232 DRM_FORMAT_BGR565, 233 DRM_FORMAT_BGR888, 234 DRM_FORMAT_ABGR8888, 235 DRM_FORMAT_BGRA8888, 236 DRM_FORMAT_BGRX8888, 237 DRM_FORMAT_XBGR8888, 238 DRM_FORMAT_ABGR1555, 239 DRM_FORMAT_BGRA5551, 240 DRM_FORMAT_XBGR1555, 241 DRM_FORMAT_BGRX5551, 242 DRM_FORMAT_ABGR4444, 243 DRM_FORMAT_BGRA4444, 244 DRM_FORMAT_BGRX4444, 245 DRM_FORMAT_XBGR4444, 246 }; 247 248 /************************************************************* 249 * SSPP sub blocks config 250 *************************************************************/ 251 252 /* SSPP common configuration */ 253 #define _VIG_SBLK(sdma_pri, qseed_ver) \ 254 { \ 255 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 256 .maxupscale = MAX_UPSCALE_RATIO, \ 257 .smart_dma_priority = sdma_pri, \ 258 .scaler_blk = {.name = "scaler", \ 259 .id = qseed_ver, \ 260 .base = 0xa00, .len = 0xa0,}, \ 261 .csc_blk = {.name = "csc", \ 262 .id = DPU_SSPP_CSC_10BIT, \ 263 .base = 0x1a00, .len = 0x100,}, \ 264 .format_list = plane_formats_yuv, \ 265 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 266 .virt_format_list = plane_formats, \ 267 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 268 .rotation_cfg = NULL, \ 269 } 270 271 #define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ 272 { \ 273 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 274 .maxupscale = MAX_UPSCALE_RATIO, \ 275 .smart_dma_priority = sdma_pri, \ 276 .scaler_blk = {.name = "scaler", \ 277 .id = qseed_ver, \ 278 .base = 0xa00, .len = 0xa0,}, \ 279 .csc_blk = {.name = "csc", \ 280 .id = DPU_SSPP_CSC_10BIT, \ 281 .base = 0x1a00, .len = 0x100,}, \ 282 .format_list = plane_formats_yuv, \ 283 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 284 .virt_format_list = plane_formats, \ 285 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 286 .rotation_cfg = rot_cfg, \ 287 } 288 289 #define _DMA_SBLK(sdma_pri) \ 290 { \ 291 .maxdwnscale = SSPP_UNITY_SCALE, \ 292 .maxupscale = SSPP_UNITY_SCALE, \ 293 .smart_dma_priority = sdma_pri, \ 294 .format_list = plane_formats, \ 295 .num_formats = ARRAY_SIZE(plane_formats), \ 296 .virt_format_list = plane_formats, \ 297 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 298 } 299 300 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = 301 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 302 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = 303 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 304 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = 305 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 306 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = 307 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); 308 309 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 310 .rot_maxheight = 1088, 311 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 312 .rot_format_list = rotation_v2_formats, 313 }; 314 315 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 316 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); 317 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 318 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); 319 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 320 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); 321 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 322 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); 323 324 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); 325 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); 326 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); 327 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); 328 329 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 330 _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); 331 332 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 333 _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); 334 335 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = 336 _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); 337 338 static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = 339 _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE); 340 341 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = 342 _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); 343 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = 344 _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); 345 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = 346 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); 347 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = 348 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); 349 350 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = 351 _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); 352 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = 353 _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); 354 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = 355 _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); 356 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = 357 _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); 358 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); 359 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); 360 361 #define _VIG_SBLK_NOSCALE(sdma_pri) \ 362 { \ 363 .maxdwnscale = SSPP_UNITY_SCALE, \ 364 .maxupscale = SSPP_UNITY_SCALE, \ 365 .smart_dma_priority = sdma_pri, \ 366 .format_list = plane_formats_yuv, \ 367 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 368 .virt_format_list = plane_formats, \ 369 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 370 } 371 372 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2); 373 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1); 374 375 /************************************************************* 376 * MIXER sub blocks config 377 *************************************************************/ 378 379 /* MSM8998 */ 380 381 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 382 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 383 .maxblendstages = 7, /* excluding base layer */ 384 .blendstage_base = { /* offsets relative to mixer base */ 385 0x20, 0x50, 0x80, 0xb0, 0x230, 386 0x260, 0x290 387 }, 388 }; 389 390 /* SDM845 */ 391 392 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 393 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 394 .maxblendstages = 11, /* excluding base layer */ 395 .blendstage_base = { /* offsets relative to mixer base */ 396 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 397 0xb0, 0xc8, 0xe0, 0xf8, 0x110 398 }, 399 }; 400 401 /* SC7180 */ 402 403 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 404 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 405 .maxblendstages = 7, /* excluding base layer */ 406 .blendstage_base = { /* offsets relative to mixer base */ 407 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 408 }, 409 }; 410 411 /* QCM2290 */ 412 413 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 414 .maxwidth = DEFAULT_DPU_LINE_WIDTH, 415 .maxblendstages = 4, /* excluding base layer */ 416 .blendstage_base = { /* offsets relative to mixer base */ 417 0x20, 0x38, 0x50, 0x68 418 }, 419 }; 420 421 /************************************************************* 422 * DSPP sub blocks config 423 *************************************************************/ 424 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 425 .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, 426 .len = 0x90, .version = 0x10007}, 427 }; 428 429 static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { 430 .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, 431 .len = 0x90, .version = 0x40000}, 432 }; 433 434 /************************************************************* 435 * PINGPONG sub blocks config 436 *************************************************************/ 437 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 438 .te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 439 .version = 0x1}, 440 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, 441 .len = 0x20, .version = 0x10000}, 442 }; 443 444 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 445 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, 446 .len = 0x20, .version = 0x10000}, 447 }; 448 449 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 450 .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0, 451 .len = 0x20, .version = 0x20000}, 452 }; 453 454 /************************************************************* 455 * DSC sub blocks config 456 *************************************************************/ 457 static const struct dpu_dsc_sub_blks dsc_sblk_0 = { 458 .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, 459 .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, 460 }; 461 462 static const struct dpu_dsc_sub_blks dsc_sblk_1 = { 463 .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, 464 .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, 465 }; 466 467 /************************************************************* 468 * VBIF sub blocks config 469 *************************************************************/ 470 /* VBIF QOS remap */ 471 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 472 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 473 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 474 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 475 476 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 477 { 478 .pps = 1920 * 1080 * 30, 479 .ot_limit = 2, 480 }, 481 { 482 .pps = 1920 * 1080 * 60, 483 .ot_limit = 4, 484 }, 485 { 486 .pps = 3840 * 2160 * 30, 487 .ot_limit = 16, 488 }, 489 }; 490 491 static const struct dpu_vbif_cfg msm8998_vbif[] = { 492 { 493 .name = "vbif_rt", .id = VBIF_RT, 494 .base = 0, .len = 0x1040, 495 .default_ot_rd_limit = 32, 496 .default_ot_wr_limit = 32, 497 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 498 .xin_halt_timeout = 0x4000, 499 .qos_rp_remap_size = 0x20, 500 .dynamic_ot_rd_tbl = { 501 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 502 .cfg = msm8998_ot_rdwr_cfg, 503 }, 504 .dynamic_ot_wr_tbl = { 505 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 506 .cfg = msm8998_ot_rdwr_cfg, 507 }, 508 .qos_rt_tbl = { 509 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 510 .priority_lvl = msm8998_rt_pri_lvl, 511 }, 512 .qos_nrt_tbl = { 513 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 514 .priority_lvl = msm8998_nrt_pri_lvl, 515 }, 516 .memtype_count = 14, 517 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 518 }, 519 }; 520 521 static const struct dpu_vbif_cfg sdm845_vbif[] = { 522 { 523 .name = "vbif_rt", .id = VBIF_RT, 524 .base = 0, .len = 0x1040, 525 .features = BIT(DPU_VBIF_QOS_REMAP), 526 .xin_halt_timeout = 0x4000, 527 .qos_rp_remap_size = 0x40, 528 .qos_rt_tbl = { 529 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 530 .priority_lvl = sdm845_rt_pri_lvl, 531 }, 532 .qos_nrt_tbl = { 533 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 534 .priority_lvl = sdm845_nrt_pri_lvl, 535 }, 536 .memtype_count = 14, 537 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 538 }, 539 }; 540 541 static const struct dpu_vbif_cfg sm8550_vbif[] = { 542 { 543 .name = "vbif_rt", .id = VBIF_RT, 544 .base = 0, .len = 0x1040, 545 .features = BIT(DPU_VBIF_QOS_REMAP), 546 .xin_halt_timeout = 0x4000, 547 .qos_rp_remap_size = 0x40, 548 .qos_rt_tbl = { 549 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 550 .priority_lvl = sdm845_rt_pri_lvl, 551 }, 552 .qos_nrt_tbl = { 553 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 554 .priority_lvl = sdm845_nrt_pri_lvl, 555 }, 556 .memtype_count = 16, 557 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 558 }, 559 }; 560 561 /************************************************************* 562 * PERF data config 563 *************************************************************/ 564 565 /* SSPP QOS LUTs */ 566 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 567 {.fl = 4, .lut = 0x1b}, 568 {.fl = 5, .lut = 0x5b}, 569 {.fl = 6, .lut = 0x15b}, 570 {.fl = 7, .lut = 0x55b}, 571 {.fl = 8, .lut = 0x155b}, 572 {.fl = 9, .lut = 0x555b}, 573 {.fl = 10, .lut = 0x1555b}, 574 {.fl = 11, .lut = 0x5555b}, 575 {.fl = 12, .lut = 0x15555b}, 576 {.fl = 0, .lut = 0x55555b} 577 }; 578 579 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 580 {.fl = 4, .lut = 0x357}, 581 {.fl = 5, .lut = 0x3357}, 582 {.fl = 6, .lut = 0x23357}, 583 {.fl = 7, .lut = 0x223357}, 584 {.fl = 8, .lut = 0x2223357}, 585 {.fl = 9, .lut = 0x22223357}, 586 {.fl = 10, .lut = 0x222223357}, 587 {.fl = 11, .lut = 0x2222223357}, 588 {.fl = 12, .lut = 0x22222223357}, 589 {.fl = 13, .lut = 0x222222223357}, 590 {.fl = 14, .lut = 0x1222222223357}, 591 {.fl = 0, .lut = 0x11222222223357} 592 }; 593 594 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 595 {.fl = 10, .lut = 0x1aaff}, 596 {.fl = 11, .lut = 0x5aaff}, 597 {.fl = 12, .lut = 0x15aaff}, 598 {.fl = 0, .lut = 0x55aaff}, 599 }; 600 601 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 602 {.fl = 0, .lut = 0x0011222222335777}, 603 }; 604 605 static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = { 606 {.fl = 0, .lut = 0x0011223445566777 }, 607 }; 608 609 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 610 {.fl = 0, .lut = 0x0011222222223357 }, 611 }; 612 613 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 614 {.fl = 4, .lut = 0x0000000000000357 }, 615 }; 616 617 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 618 {.fl = 0, .lut = 0x0011222222335777}, 619 }; 620 621 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 622 {.fl = 10, .lut = 0x344556677}, 623 {.fl = 11, .lut = 0x3344556677}, 624 {.fl = 12, .lut = 0x23344556677}, 625 {.fl = 13, .lut = 0x223344556677}, 626 {.fl = 14, .lut = 0x1223344556677}, 627 {.fl = 0, .lut = 0x112233344556677}, 628 }; 629 630 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 631 {.fl = 0, .lut = 0x0011223344556677}, 632 }; 633 634 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 635 {.fl = 10, .lut = 0x0000000344556677}, 636 }; 637 638 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 639 {.fl = 0, .lut = 0x0}, 640 }; 641 642 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 643 {.fl = 0, .lut = 0x0}, 644 }; 645 646 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 647 {.fl = 0, .lut = 0x0}, 648 }; 649 650 /************************************************************* 651 * Hardware catalog 652 *************************************************************/ 653 654 #include "catalog/dpu_3_0_msm8998.h" 655 656 #include "catalog/dpu_4_0_sdm845.h" 657 658 #include "catalog/dpu_5_0_sm8150.h" 659 #include "catalog/dpu_5_1_sc8180x.h" 660 #include "catalog/dpu_5_4_sm6125.h" 661 662 #include "catalog/dpu_6_0_sm8250.h" 663 #include "catalog/dpu_6_2_sc7180.h" 664 #include "catalog/dpu_6_3_sm6115.h" 665 #include "catalog/dpu_6_4_sm6350.h" 666 #include "catalog/dpu_6_5_qcm2290.h" 667 #include "catalog/dpu_6_9_sm6375.h" 668 669 #include "catalog/dpu_7_0_sm8350.h" 670 #include "catalog/dpu_7_2_sc7280.h" 671 672 #include "catalog/dpu_8_0_sc8280xp.h" 673 #include "catalog/dpu_8_1_sm8450.h" 674 675 #include "catalog/dpu_9_0_sm8550.h" 676