1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_BLK_NAME_LEN 16 23 24 #define MAX_IMG_WIDTH 0x3fff 25 #define MAX_IMG_HEIGHT 0x3fff 26 27 #define CRTC_DUAL_MIXERS 2 28 29 #define MAX_XIN_COUNT 16 30 31 /** 32 * MDP TOP BLOCK features 33 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 34 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 35 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results 36 * in a failure 37 * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register 38 * (moved into INTF block since DPU 5.0.0) 39 * @DPU_MDP_MAX Maximum value 40 41 */ 42 enum { 43 DPU_MDP_PANIC_PER_PIPE = 0x1, 44 DPU_MDP_10BIT_SUPPORT, 45 DPU_MDP_AUDIO_SELECT, 46 DPU_MDP_PERIPH_0_REMOVED, 47 DPU_MDP_VSYNC_SEL, 48 DPU_MDP_MAX 49 }; 50 51 /** 52 * SSPP sub-blocks/features 53 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 54 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 55 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 56 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 57 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 58 * @DPU_SSPP_CSC, Support of Color space converion 59 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 60 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 61 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 62 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 63 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 64 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 65 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 66 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 67 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 68 * @DPU_SSPP_CDP Supports client driven prefetch 69 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 70 * @DPU_SSPP_MAX maximum value 71 */ 72 enum { 73 DPU_SSPP_SCALER_QSEED2 = 0x1, 74 DPU_SSPP_SCALER_QSEED3, 75 DPU_SSPP_SCALER_QSEED3LITE, 76 DPU_SSPP_SCALER_QSEED4, 77 DPU_SSPP_SCALER_RGB, 78 DPU_SSPP_CSC, 79 DPU_SSPP_CSC_10BIT, 80 DPU_SSPP_CURSOR, 81 DPU_SSPP_QOS, 82 DPU_SSPP_QOS_8LVL, 83 DPU_SSPP_EXCL_RECT, 84 DPU_SSPP_SMART_DMA_V1, 85 DPU_SSPP_SMART_DMA_V2, 86 DPU_SSPP_TS_PREFILL, 87 DPU_SSPP_TS_PREFILL_REC1, 88 DPU_SSPP_CDP, 89 DPU_SSPP_INLINE_ROTATION, 90 DPU_SSPP_MAX 91 }; 92 93 /* 94 * MIXER sub-blocks/features 95 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 96 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 97 * @DPU_MIXER_GC Gamma correction block 98 * @DPU_DIM_LAYER Layer mixer supports dim layer 99 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 100 * @DPU_MIXER_MAX maximum value 101 */ 102 enum { 103 DPU_MIXER_LAYER = 0x1, 104 DPU_MIXER_SOURCESPLIT, 105 DPU_MIXER_GC, 106 DPU_DIM_LAYER, 107 DPU_MIXER_COMBINED_ALPHA, 108 DPU_MIXER_MAX 109 }; 110 111 /** 112 * DSPP sub-blocks 113 * @DPU_DSPP_PCC Panel color correction block 114 */ 115 enum { 116 DPU_DSPP_PCC = 0x1, 117 DPU_DSPP_MAX 118 }; 119 120 /** 121 * PINGPONG sub-blocks 122 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 123 * @DPU_PINGPONG_SPLIT PP block supports split fifo 124 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 125 * @DPU_PINGPONG_DITHER Dither blocks 126 * @DPU_PINGPONG_DSC PP block supports DSC 127 * @DPU_PINGPONG_MAX 128 */ 129 enum { 130 DPU_PINGPONG_TE2 = 0x1, 131 DPU_PINGPONG_SPLIT, 132 DPU_PINGPONG_SLAVE, 133 DPU_PINGPONG_DITHER, 134 DPU_PINGPONG_DSC, 135 DPU_PINGPONG_MAX 136 }; 137 138 /** 139 * CTL sub-blocks 140 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 141 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 142 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 143 * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register 144 * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush 145 * @DPU_CTL_MAX 146 */ 147 enum { 148 DPU_CTL_SPLIT_DISPLAY = 0x1, 149 DPU_CTL_ACTIVE_CFG, 150 DPU_CTL_FETCH_ACTIVE, 151 DPU_CTL_VM_CFG, 152 DPU_CTL_HAS_LAYER_EXT4, 153 DPU_CTL_DSPP_SUB_BLOCK_FLUSH, 154 DPU_CTL_MAX 155 }; 156 157 /** 158 * INTF sub-blocks 159 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 160 * pixel data arrives to this INTF 161 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 162 * than video timing 163 * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register 164 * @DPU_INTF_MAX 165 */ 166 enum { 167 DPU_INTF_INPUT_CTRL = 0x1, 168 DPU_DATA_HCTL_EN, 169 DPU_INTF_STATUS_SUPPORTED, 170 DPU_INTF_MAX 171 }; 172 173 /** 174 * WB sub-blocks and features 175 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 176 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 177 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 178 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 179 * @DPU_WB_DITHER, Dither block 180 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 181 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 182 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 183 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 184 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 185 * the destination image 186 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 187 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 188 * @DPU_WB_CDP Writeback supports client driven prefetch 189 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 190 * data arrives. 191 * @DPU_WB_CROP CWB supports cropping 192 * @DPU_WB_MAX maximum value 193 */ 194 enum { 195 DPU_WB_LINE_MODE = 0x1, 196 DPU_WB_BLOCK_MODE, 197 DPU_WB_UBWC, 198 DPU_WB_YUV_CONFIG, 199 DPU_WB_PIPE_ALPHA, 200 DPU_WB_XY_ROI_OFFSET, 201 DPU_WB_QOS, 202 DPU_WB_QOS_8LVL, 203 DPU_WB_CDP, 204 DPU_WB_INPUT_CTRL, 205 DPU_WB_CROP, 206 DPU_WB_MAX 207 }; 208 209 /** 210 * VBIF sub-blocks and features 211 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 212 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 213 * @DPU_VBIF_MAX maximum value 214 */ 215 enum { 216 DPU_VBIF_QOS_OTLIM = 0x1, 217 DPU_VBIF_QOS_REMAP, 218 DPU_VBIF_MAX 219 }; 220 221 /** 222 * DSC sub-blocks/features 223 * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets 224 * the pixel output from this DSC. 225 * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 226 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding 227 * @DPU_DSC_MAX 228 */ 229 enum { 230 DPU_DSC_OUTPUT_CTRL = 0x1, 231 DPU_DSC_HW_REV_1_2, 232 DPU_DSC_NATIVE_42x_EN, 233 DPU_DSC_MAX 234 }; 235 236 /** 237 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 238 * @name: string name for debug purposes 239 * @id: enum identifying this block 240 * @base: register base offset to mdss 241 * @len: length of hardware block 242 * @features bit mask identifying sub-blocks/features 243 */ 244 #define DPU_HW_BLK_INFO \ 245 char name[DPU_HW_BLK_NAME_LEN]; \ 246 u32 id; \ 247 u32 base; \ 248 u32 len; \ 249 unsigned long features 250 251 /** 252 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 253 * @name: string name for debug purposes 254 * @id: enum identifying this sub-block 255 * @base: offset of this sub-block relative to the block 256 * offset 257 * @len register block length of this sub-block 258 */ 259 #define DPU_HW_SUBBLK_INFO \ 260 char name[DPU_HW_BLK_NAME_LEN]; \ 261 u32 id; \ 262 u32 base; \ 263 u32 len 264 265 /** 266 * struct dpu_scaler_blk: Scaler information 267 * @info: HW register and features supported by this sub-blk 268 * @version: qseed block revision 269 */ 270 struct dpu_scaler_blk { 271 DPU_HW_SUBBLK_INFO; 272 u32 version; 273 }; 274 275 struct dpu_csc_blk { 276 DPU_HW_SUBBLK_INFO; 277 }; 278 279 /** 280 * struct dpu_pp_blk : Pixel processing sub-blk information 281 * @info: HW register and features supported by this sub-blk 282 * @version: HW Algorithm version 283 */ 284 struct dpu_pp_blk { 285 DPU_HW_SUBBLK_INFO; 286 u32 version; 287 }; 288 289 /** 290 * struct dpu_dsc_blk - DSC Encoder sub-blk information 291 * @info: HW register and features supported by this sub-blk 292 */ 293 struct dpu_dsc_blk { 294 DPU_HW_SUBBLK_INFO; 295 }; 296 297 /** 298 * enum dpu_qos_lut_usage - define QoS LUT use cases 299 */ 300 enum dpu_qos_lut_usage { 301 DPU_QOS_LUT_USAGE_LINEAR, 302 DPU_QOS_LUT_USAGE_MACROTILE, 303 DPU_QOS_LUT_USAGE_NRT, 304 DPU_QOS_LUT_USAGE_MAX, 305 }; 306 307 /** 308 * struct dpu_qos_lut_entry - define QoS LUT table entry 309 * @fl: fill level, or zero on last entry to indicate default lut 310 * @lut: lut to use if equal to or less than fill level 311 */ 312 struct dpu_qos_lut_entry { 313 u32 fl; 314 u64 lut; 315 }; 316 317 /** 318 * struct dpu_qos_lut_tbl - define QoS LUT table 319 * @nentry: number of entry in this table 320 * @entries: Pointer to table entries 321 */ 322 struct dpu_qos_lut_tbl { 323 u32 nentry; 324 const struct dpu_qos_lut_entry *entries; 325 }; 326 327 /** 328 * struct dpu_rotation_cfg - define inline rotation config 329 * @rot_maxheight: max pre rotated height allowed for rotation 330 * @rot_num_formats: number of elements in @rot_format_list 331 * @rot_format_list: list of supported rotator formats 332 */ 333 struct dpu_rotation_cfg { 334 u32 rot_maxheight; 335 size_t rot_num_formats; 336 const u32 *rot_format_list; 337 }; 338 339 /** 340 * struct dpu_caps - define DPU capabilities 341 * @max_mixer_width max layer mixer line width support. 342 * @max_mixer_blendstages max layer mixer blend stages or 343 * supported z order 344 * @qseed_type qseed2 or qseed3 support. 345 * @has_src_split source split feature status 346 * @has_dim_layer dim layer feature status 347 * @has_idle_pc indicate if idle power collapse feature is supported 348 * @has_3d_merge indicate if 3D merge is supported 349 * @max_linewidth max linewidth for sspp 350 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 351 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 352 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 353 */ 354 struct dpu_caps { 355 u32 max_mixer_width; 356 u32 max_mixer_blendstages; 357 u32 qseed_type; 358 bool has_src_split; 359 bool has_dim_layer; 360 bool has_idle_pc; 361 bool has_3d_merge; 362 /* SSPP limits */ 363 u32 max_linewidth; 364 u32 pixel_ram_size; 365 u32 max_hdeci_exp; 366 u32 max_vdeci_exp; 367 }; 368 369 /** 370 * struct dpu_sspp_sub_blks : SSPP sub-blocks 371 * common: Pointer to common configurations shared by sub blocks 372 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 373 * @maxupscale: maxupscale ratio supported 374 * @smart_dma_priority: hw priority of rect1 of multirect pipe 375 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 376 * @qseed_ver: qseed version 377 * @scaler_blk: 378 * @csc_blk: 379 * @format_list: Pointer to list of supported formats 380 * @num_formats: Number of supported formats 381 * @virt_format_list: Pointer to list of supported formats for virtual planes 382 * @virt_num_formats: Number of supported formats for virtual planes 383 * @dpu_rotation_cfg: inline rotation configuration 384 */ 385 struct dpu_sspp_sub_blks { 386 u32 maxdwnscale; 387 u32 maxupscale; 388 u32 smart_dma_priority; 389 u32 max_per_pipe_bw; 390 u32 qseed_ver; 391 struct dpu_scaler_blk scaler_blk; 392 struct dpu_pp_blk csc_blk; 393 394 const u32 *format_list; 395 u32 num_formats; 396 const u32 *virt_format_list; 397 u32 virt_num_formats; 398 const struct dpu_rotation_cfg *rotation_cfg; 399 }; 400 401 /** 402 * struct dpu_lm_sub_blks: information of mixer block 403 * @maxwidth: Max pixel width supported by this mixer 404 * @maxblendstages: Max number of blend-stages supported 405 * @blendstage_base: Blend-stage register base offset 406 */ 407 struct dpu_lm_sub_blks { 408 u32 maxwidth; 409 u32 maxblendstages; 410 u32 blendstage_base[MAX_BLOCKS]; 411 }; 412 413 /** 414 * struct dpu_dspp_sub_blks: Information of DSPP block 415 * @pcc: pixel color correction block 416 */ 417 struct dpu_dspp_sub_blks { 418 struct dpu_pp_blk pcc; 419 }; 420 421 struct dpu_pingpong_sub_blks { 422 struct dpu_pp_blk te; 423 struct dpu_pp_blk te2; 424 struct dpu_pp_blk dither; 425 }; 426 427 /** 428 * struct dpu_dsc_sub_blks - DSC sub-blks 429 * @enc: DSC encoder sub-block 430 * @ctl: DSC controller sub-block 431 */ 432 struct dpu_dsc_sub_blks { 433 struct dpu_dsc_blk enc; 434 struct dpu_dsc_blk ctl; 435 }; 436 437 /** 438 * dpu_clk_ctrl_type - Defines top level clock control signals 439 */ 440 enum dpu_clk_ctrl_type { 441 DPU_CLK_CTRL_NONE, 442 DPU_CLK_CTRL_VIG0, 443 DPU_CLK_CTRL_VIG1, 444 DPU_CLK_CTRL_VIG2, 445 DPU_CLK_CTRL_VIG3, 446 DPU_CLK_CTRL_VIG4, 447 DPU_CLK_CTRL_RGB0, 448 DPU_CLK_CTRL_RGB1, 449 DPU_CLK_CTRL_RGB2, 450 DPU_CLK_CTRL_RGB3, 451 DPU_CLK_CTRL_DMA0, 452 DPU_CLK_CTRL_DMA1, 453 DPU_CLK_CTRL_DMA2, 454 DPU_CLK_CTRL_DMA3, 455 DPU_CLK_CTRL_DMA4, 456 DPU_CLK_CTRL_DMA5, 457 DPU_CLK_CTRL_CURSOR0, 458 DPU_CLK_CTRL_CURSOR1, 459 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 460 DPU_CLK_CTRL_REG_DMA, 461 DPU_CLK_CTRL_WB2, 462 DPU_CLK_CTRL_MAX, 463 }; 464 465 /* struct dpu_clk_ctrl_reg : Clock control register 466 * @reg_off: register offset 467 * @bit_off: bit offset 468 */ 469 struct dpu_clk_ctrl_reg { 470 u32 reg_off; 471 u32 bit_off; 472 }; 473 474 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 475 * @id: index identifying this block 476 * @base: register base offset to mdss 477 * @features bit mask identifying sub-blocks/features 478 * @clk_ctrls clock control register definition 479 */ 480 struct dpu_mdp_cfg { 481 DPU_HW_BLK_INFO; 482 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 483 }; 484 485 /* struct dpu_ctl_cfg : MDP CTL instance info 486 * @id: index identifying this block 487 * @base: register base offset to mdss 488 * @features bit mask identifying sub-blocks/features 489 * @intr_start: interrupt index for CTL_START 490 */ 491 struct dpu_ctl_cfg { 492 DPU_HW_BLK_INFO; 493 unsigned int intr_start; 494 }; 495 496 /** 497 * struct dpu_sspp_cfg - information of source pipes 498 * @id: index identifying this block 499 * @base register offset of this block 500 * @features bit mask identifying sub-blocks/features 501 * @sblk: SSPP sub-blocks information 502 * @xin_id: bus client identifier 503 * @clk_ctrl clock control identifier 504 * @type sspp type identifier 505 */ 506 struct dpu_sspp_cfg { 507 DPU_HW_BLK_INFO; 508 const struct dpu_sspp_sub_blks *sblk; 509 u32 xin_id; 510 enum dpu_clk_ctrl_type clk_ctrl; 511 u32 type; 512 }; 513 514 /** 515 * struct dpu_lm_cfg - information of layer mixer blocks 516 * @id: index identifying this block 517 * @base register offset of this block 518 * @features bit mask identifying sub-blocks/features 519 * @sblk: LM Sub-blocks information 520 * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported 521 * @lm_pair: ID of LM that can be controlled by same CTL 522 */ 523 struct dpu_lm_cfg { 524 DPU_HW_BLK_INFO; 525 const struct dpu_lm_sub_blks *sblk; 526 u32 pingpong; 527 u32 dspp; 528 unsigned long lm_pair; 529 }; 530 531 /** 532 * struct dpu_dspp_cfg - information of DSPP blocks 533 * @id enum identifying this block 534 * @base register offset of this block 535 * @features bit mask identifying sub-blocks/features 536 * supported by this block 537 * @sblk sub-blocks information 538 */ 539 struct dpu_dspp_cfg { 540 DPU_HW_BLK_INFO; 541 const struct dpu_dspp_sub_blks *sblk; 542 }; 543 544 /** 545 * struct dpu_pingpong_cfg - information of PING-PONG blocks 546 * @id enum identifying this block 547 * @base register offset of this block 548 * @features bit mask identifying sub-blocks/features 549 * @intr_done: index for PINGPONG done interrupt 550 * @intr_rdptr: index for PINGPONG readpointer done interrupt 551 * @sblk sub-blocks information 552 */ 553 struct dpu_pingpong_cfg { 554 DPU_HW_BLK_INFO; 555 u32 merge_3d; 556 unsigned int intr_done; 557 unsigned int intr_rdptr; 558 const struct dpu_pingpong_sub_blks *sblk; 559 }; 560 561 /** 562 * struct dpu_merge_3d_cfg - information of DSPP blocks 563 * @id enum identifying this block 564 * @base register offset of this block 565 * @features bit mask identifying sub-blocks/features 566 * supported by this block 567 * @sblk sub-blocks information 568 */ 569 struct dpu_merge_3d_cfg { 570 DPU_HW_BLK_INFO; 571 const struct dpu_merge_3d_sub_blks *sblk; 572 }; 573 574 /** 575 * struct dpu_dsc_cfg - information of DSC blocks 576 * @id enum identifying this block 577 * @base register offset of this block 578 * @len: length of hardware block 579 * @features bit mask identifying sub-blocks/features 580 * @sblk: sub-blocks information 581 */ 582 struct dpu_dsc_cfg { 583 DPU_HW_BLK_INFO; 584 const struct dpu_dsc_sub_blks *sblk; 585 }; 586 587 /** 588 * struct dpu_intf_cfg - information of timing engine blocks 589 * @id enum identifying this block 590 * @base register offset of this block 591 * @features bit mask identifying sub-blocks/features 592 * @type: Interface type(DSI, DP, HDMI) 593 * @controller_id: Controller Instance ID in case of multiple of intf type 594 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 595 * @intr_underrun: index for INTF underrun interrupt 596 * @intr_vsync: index for INTF VSYNC interrupt 597 * @intr_tear_rd_ptr: Index for INTF TEAR_RD_PTR interrupt 598 */ 599 struct dpu_intf_cfg { 600 DPU_HW_BLK_INFO; 601 u32 type; /* interface type*/ 602 u32 controller_id; 603 u32 prog_fetch_lines_worst_case; 604 unsigned int intr_underrun; 605 unsigned int intr_vsync; 606 unsigned int intr_tear_rd_ptr; 607 }; 608 609 /** 610 * struct dpu_wb_cfg - information of writeback blocks 611 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 612 * @vbif_idx: vbif client index 613 * @maxlinewidth: max line width supported by writeback block 614 * @xin_id: bus client identifier 615 * @intr_wb_done: interrupt index for WB_DONE 616 * @format_list: list of formats supported by this writeback block 617 * @num_formats: number of formats supported by this writeback block 618 * @clk_ctrl: clock control identifier 619 */ 620 struct dpu_wb_cfg { 621 DPU_HW_BLK_INFO; 622 u8 vbif_idx; 623 u32 maxlinewidth; 624 u32 xin_id; 625 unsigned int intr_wb_done; 626 const u32 *format_list; 627 u32 num_formats; 628 enum dpu_clk_ctrl_type clk_ctrl; 629 }; 630 631 /** 632 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 633 * @pps pixel per seconds 634 * @ot_limit OT limit to use up to specified pixel per second 635 */ 636 struct dpu_vbif_dynamic_ot_cfg { 637 u64 pps; 638 u32 ot_limit; 639 }; 640 641 /** 642 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 643 * @count length of cfg 644 * @cfg pointer to array of configuration settings with 645 * ascending requirements 646 */ 647 struct dpu_vbif_dynamic_ot_tbl { 648 u32 count; 649 const struct dpu_vbif_dynamic_ot_cfg *cfg; 650 }; 651 652 /** 653 * struct dpu_vbif_qos_tbl - QoS priority table 654 * @npriority_lvl num of priority level 655 * @priority_lvl pointer to array of priority level in ascending order 656 */ 657 struct dpu_vbif_qos_tbl { 658 u32 npriority_lvl; 659 const u32 *priority_lvl; 660 }; 661 662 /** 663 * struct dpu_vbif_cfg - information of VBIF blocks 664 * @id enum identifying this block 665 * @base register offset of this block 666 * @features bit mask identifying sub-blocks/features 667 * @ot_rd_limit default OT read limit 668 * @ot_wr_limit default OT write limit 669 * @xin_halt_timeout maximum time (in usec) for xin to halt 670 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 671 * @dynamic_ot_rd_tbl dynamic OT read configuration table 672 * @dynamic_ot_wr_tbl dynamic OT write configuration table 673 * @qos_rt_tbl real-time QoS priority table 674 * @qos_nrt_tbl non-real-time QoS priority table 675 * @memtype_count number of defined memtypes 676 * @memtype array of xin memtype definitions 677 */ 678 struct dpu_vbif_cfg { 679 DPU_HW_BLK_INFO; 680 u32 default_ot_rd_limit; 681 u32 default_ot_wr_limit; 682 u32 xin_halt_timeout; 683 u32 qos_rp_remap_size; 684 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 685 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 686 struct dpu_vbif_qos_tbl qos_rt_tbl; 687 struct dpu_vbif_qos_tbl qos_nrt_tbl; 688 u32 memtype_count; 689 u32 memtype[MAX_XIN_COUNT]; 690 }; 691 692 /** 693 * Define CDP use cases 694 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 695 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 696 */ 697 enum { 698 DPU_PERF_CDP_USAGE_RT, 699 DPU_PERF_CDP_USAGE_NRT, 700 DPU_PERF_CDP_USAGE_MAX 701 }; 702 703 /** 704 * struct dpu_perf_cdp_cfg - define CDP use case configuration 705 * @rd_enable: true if read pipe CDP is enabled 706 * @wr_enable: true if write pipe CDP is enabled 707 */ 708 struct dpu_perf_cdp_cfg { 709 bool rd_enable; 710 bool wr_enable; 711 }; 712 713 /** 714 * struct dpu_mdss_version - DPU's major and minor versions 715 * @core_major_ver: DPU core's major version 716 * @core_minor_ver: DPU core's minor version 717 */ 718 struct dpu_mdss_version { 719 u8 core_major_ver; 720 u8 core_minor_ver; 721 }; 722 723 /** 724 * struct dpu_perf_cfg - performance control settings 725 * @max_bw_low low threshold of maximum bandwidth (kbps) 726 * @max_bw_high high threshold of maximum bandwidth (kbps) 727 * @min_core_ib minimum bandwidth for core (kbps) 728 * @min_core_ib minimum mnoc ib vote in kbps 729 * @min_llcc_ib minimum llcc ib vote in kbps 730 * @min_dram_ib minimum dram ib vote in kbps 731 * @undersized_prefill_lines undersized prefill in lines 732 * @xtra_prefill_lines extra prefill latency in lines 733 * @dest_scale_prefill_lines destination scaler latency in lines 734 * @macrotile_perfill_lines macrotile latency in lines 735 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 736 * @linear_prefill_lines linear latency in lines 737 * @downscaling_prefill_lines downscaling latency in lines 738 * @amortizable_theshold minimum y position for traffic shaping prefill 739 * @min_prefill_lines minimum pipeline latency in lines 740 * @clk_inefficiency_factor DPU src clock inefficiency factor 741 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 742 * @safe_lut_tbl: LUT tables for safe signals 743 * @danger_lut_tbl: LUT tables for danger signals 744 * @qos_lut_tbl: LUT tables for QoS signals 745 * @cdp_cfg cdp use case configurations 746 */ 747 struct dpu_perf_cfg { 748 u32 max_bw_low; 749 u32 max_bw_high; 750 u32 min_core_ib; 751 u32 min_llcc_ib; 752 u32 min_dram_ib; 753 u32 undersized_prefill_lines; 754 u32 xtra_prefill_lines; 755 u32 dest_scale_prefill_lines; 756 u32 macrotile_prefill_lines; 757 u32 yuv_nv12_prefill_lines; 758 u32 linear_prefill_lines; 759 u32 downscaling_prefill_lines; 760 u32 amortizable_threshold; 761 u32 min_prefill_lines; 762 u32 clk_inefficiency_factor; 763 u32 bw_inefficiency_factor; 764 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 765 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 766 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 767 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 768 }; 769 770 /** 771 * struct dpu_mdss_cfg - information of MDSS HW 772 * This is the main catalog data structure representing 773 * this HW version. Contains dpu's major and minor versions, 774 * number of instances, register offsets, capabilities of the 775 * all MDSS HW sub-blocks. 776 * 777 * @dma_formats Supported formats for dma pipe 778 * @cursor_formats Supported formats for cursor pipe 779 * @vig_formats Supported formats for vig pipe 780 */ 781 struct dpu_mdss_cfg { 782 const struct dpu_mdss_version *mdss_ver; 783 784 const struct dpu_caps *caps; 785 786 const struct dpu_mdp_cfg *mdp; 787 788 u32 ctl_count; 789 const struct dpu_ctl_cfg *ctl; 790 791 u32 sspp_count; 792 const struct dpu_sspp_cfg *sspp; 793 794 u32 mixer_count; 795 const struct dpu_lm_cfg *mixer; 796 797 u32 pingpong_count; 798 const struct dpu_pingpong_cfg *pingpong; 799 800 u32 merge_3d_count; 801 const struct dpu_merge_3d_cfg *merge_3d; 802 803 u32 dsc_count; 804 const struct dpu_dsc_cfg *dsc; 805 806 u32 intf_count; 807 const struct dpu_intf_cfg *intf; 808 809 u32 vbif_count; 810 const struct dpu_vbif_cfg *vbif; 811 812 u32 wb_count; 813 const struct dpu_wb_cfg *wb; 814 815 u32 ad_count; 816 817 u32 dspp_count; 818 const struct dpu_dspp_cfg *dspp; 819 820 /* Add additional block data structures here */ 821 822 const struct dpu_perf_cfg *perf; 823 const struct dpu_format_extended *dma_formats; 824 const struct dpu_format_extended *cursor_formats; 825 const struct dpu_format_extended *vig_formats; 826 }; 827 828 extern const struct dpu_mdss_cfg dpu_msm8998_cfg; 829 extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 830 extern const struct dpu_mdss_cfg dpu_sm8150_cfg; 831 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 832 extern const struct dpu_mdss_cfg dpu_sm8250_cfg; 833 extern const struct dpu_mdss_cfg dpu_sc7180_cfg; 834 extern const struct dpu_mdss_cfg dpu_sm6115_cfg; 835 extern const struct dpu_mdss_cfg dpu_sm6125_cfg; 836 extern const struct dpu_mdss_cfg dpu_sm6350_cfg; 837 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; 838 extern const struct dpu_mdss_cfg dpu_sm6375_cfg; 839 extern const struct dpu_mdss_cfg dpu_sm8350_cfg; 840 extern const struct dpu_mdss_cfg dpu_sc7280_cfg; 841 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; 842 extern const struct dpu_mdss_cfg dpu_sm8450_cfg; 843 extern const struct dpu_mdss_cfg dpu_sm8550_cfg; 844 845 #endif /* _DPU_HW_CATALOG_H */ 846