1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_CTL_H 6 #define _DPU_HW_CTL_H 7 8 #include "dpu_hw_mdss.h" 9 #include "dpu_hw_util.h" 10 #include "dpu_hw_catalog.h" 11 #include "dpu_hw_sspp.h" 12 #include "dpu_hw_blk.h" 13 14 /** 15 * dpu_ctl_mode_sel: Interface mode selection 16 * DPU_CTL_MODE_SEL_VID: Video mode interface 17 * DPU_CTL_MODE_SEL_CMD: Command mode interface 18 */ 19 enum dpu_ctl_mode_sel { 20 DPU_CTL_MODE_SEL_VID = 0, 21 DPU_CTL_MODE_SEL_CMD 22 }; 23 24 struct dpu_hw_ctl; 25 /** 26 * struct dpu_hw_stage_cfg - blending stage cfg 27 * @stage : SSPP_ID at each stage 28 * @multirect_index: index of the rectangle of SSPP. 29 */ 30 struct dpu_hw_stage_cfg { 31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 32 enum dpu_sspp_multirect_index multirect_index 33 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 34 }; 35 36 /** 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 * @intf : Interface id 39 * @mode_3d: 3d mux configuration 40 * @merge_3d: 3d merge block used 41 * @intf_mode_sel: Interface mode, cmd / vid 42 * @stream_sel: Stream selection for multi-stream interfaces 43 */ 44 struct dpu_hw_intf_cfg { 45 enum dpu_intf intf; 46 enum dpu_3d_blend_mode mode_3d; 47 enum dpu_merge_3d merge_3d; 48 enum dpu_ctl_mode_sel intf_mode_sel; 49 int stream_sel; 50 }; 51 52 /** 53 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 54 * Assumption is these functions will be called after clocks are enabled 55 */ 56 struct dpu_hw_ctl_ops { 57 /** 58 * kickoff hw operation for Sw controlled interfaces 59 * DSI cmd mode and WB interface are SW controlled 60 * @ctx : ctl path ctx pointer 61 */ 62 void (*trigger_start)(struct dpu_hw_ctl *ctx); 63 64 /** 65 * check if the ctl is started 66 * @ctx : ctl path ctx pointer 67 * @Return: true if started, false if stopped 68 */ 69 bool (*is_started)(struct dpu_hw_ctl *ctx); 70 71 /** 72 * kickoff prepare is in progress hw operation for sw 73 * controlled interfaces: DSI cmd mode and WB interface 74 * are SW controlled 75 * @ctx : ctl path ctx pointer 76 */ 77 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 78 79 /** 80 * Clear the value of the cached pending_flush_mask 81 * No effect on hardware 82 * @ctx : ctl path ctx pointer 83 */ 84 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 85 86 /** 87 * Query the value of the cached pending_flush_mask 88 * No effect on hardware 89 * @ctx : ctl path ctx pointer 90 */ 91 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 92 93 /** 94 * OR in the given flushbits to the cached pending_flush_mask 95 * No effect on hardware 96 * @ctx : ctl path ctx pointer 97 * @flushbits : module flushmask 98 */ 99 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 100 u32 flushbits); 101 102 /** 103 * OR in the given flushbits to the cached pending_(intf_)flush_mask 104 * No effect on hardware 105 * @ctx : ctl path ctx pointer 106 * @blk : interface block index 107 */ 108 void (*update_pending_flush_intf)(struct dpu_hw_ctl *ctx, 109 enum dpu_intf blk); 110 111 /** 112 * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask 113 * No effect on hardware 114 * @ctx : ctl path ctx pointer 115 * @blk : interface block index 116 */ 117 void (*update_pending_flush_merge_3d)(struct dpu_hw_ctl *ctx, 118 enum dpu_merge_3d blk); 119 120 /** 121 * Write the value of the pending_flush_mask to hardware 122 * @ctx : ctl path ctx pointer 123 */ 124 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 125 126 /** 127 * Read the value of the flush register 128 * @ctx : ctl path ctx pointer 129 * @Return: value of the ctl flush register. 130 */ 131 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 132 133 /** 134 * Setup ctl_path interface config 135 * @ctx 136 * @cfg : interface config structure pointer 137 */ 138 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 139 struct dpu_hw_intf_cfg *cfg); 140 141 int (*reset)(struct dpu_hw_ctl *c); 142 143 /* 144 * wait_reset_status - checks ctl reset status 145 * @ctx : ctl path ctx pointer 146 * 147 * This function checks the ctl reset status bit. 148 * If the reset bit is set, it keeps polling the status till the hw 149 * reset is complete. 150 * Returns: 0 on success or -error if reset incomplete within interval 151 */ 152 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 153 154 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, 155 enum dpu_sspp blk); 156 157 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, 158 enum dpu_lm blk); 159 160 uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx, 161 enum dpu_dspp blk); 162 163 /** 164 * Set all blend stages to disabled 165 * @ctx : ctl path ctx pointer 166 */ 167 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 168 169 /** 170 * Configure layer mixer to pipe configuration 171 * @ctx : ctl path ctx pointer 172 * @lm : layer mixer enumeration 173 * @cfg : blend stage configuration 174 */ 175 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 176 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 177 178 void (*set_active_pipes)(struct dpu_hw_ctl *ctx, 179 unsigned long *fetch_active); 180 }; 181 182 /** 183 * struct dpu_hw_ctl : CTL PATH driver object 184 * @base: hardware block base structure 185 * @hw: block register map object 186 * @idx: control path index 187 * @caps: control path capabilities 188 * @mixer_count: number of mixers 189 * @mixer_hw_caps: mixer hardware capabilities 190 * @pending_flush_mask: storage for pending ctl_flush managed via ops 191 * @pending_intf_flush_mask: pending INTF flush 192 * @ops: operation list 193 */ 194 struct dpu_hw_ctl { 195 struct dpu_hw_blk base; 196 struct dpu_hw_blk_reg_map hw; 197 198 /* ctl path */ 199 int idx; 200 const struct dpu_ctl_cfg *caps; 201 int mixer_count; 202 const struct dpu_lm_cfg *mixer_hw_caps; 203 u32 pending_flush_mask; 204 u32 pending_intf_flush_mask; 205 u32 pending_merge_3d_flush_mask; 206 207 /* ops */ 208 struct dpu_hw_ctl_ops ops; 209 }; 210 211 /** 212 * dpu_hw_ctl - convert base object dpu_hw_base to container 213 * @hw: Pointer to base hardware block 214 * return: Pointer to hardware block container 215 */ 216 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 217 { 218 return container_of(hw, struct dpu_hw_ctl, base); 219 } 220 221 /** 222 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object. 223 * should be called before accessing every ctl path registers. 224 * @idx: ctl_path index for which driver object is required 225 * @addr: mapped register io address of MDP 226 * @m : pointer to mdss catalog data 227 */ 228 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, 229 void __iomem *addr, 230 const struct dpu_mdss_cfg *m); 231 232 /** 233 * dpu_hw_ctl_destroy(): Destroys ctl driver context 234 * should be called to free the context 235 */ 236 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); 237 238 #endif /*_DPU_HW_CTL_H */ 239