1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020-2022, Linaro Limited 4 */ 5 6 #include <drm/drm_managed.h> 7 8 #include <drm/display/drm_dsc_helper.h> 9 10 #include "dpu_kms.h" 11 #include "dpu_hw_catalog.h" 12 #include "dpu_hwio.h" 13 #include "dpu_hw_mdss.h" 14 #include "dpu_hw_dsc.h" 15 16 #define DSC_COMMON_MODE 0x000 17 #define DSC_ENC 0x004 18 #define DSC_PICTURE 0x008 19 #define DSC_SLICE 0x00C 20 #define DSC_CHUNK_SIZE 0x010 21 #define DSC_DELAY 0x014 22 #define DSC_SCALE_INITIAL 0x018 23 #define DSC_SCALE_DEC_INTERVAL 0x01C 24 #define DSC_SCALE_INC_INTERVAL 0x020 25 #define DSC_FIRST_LINE_BPG_OFFSET 0x024 26 #define DSC_BPG_OFFSET 0x028 27 #define DSC_DSC_OFFSET 0x02C 28 #define DSC_FLATNESS 0x030 29 #define DSC_RC_MODEL_SIZE 0x034 30 #define DSC_RC 0x038 31 #define DSC_RC_BUF_THRESH 0x03C 32 #define DSC_RANGE_MIN_QP 0x074 33 #define DSC_RANGE_MAX_QP 0x0B0 34 #define DSC_RANGE_BPG_OFFSET 0x0EC 35 36 #define DSC_CTL(m) (0x1800 - 0x3FC * (m - DSC_0)) 37 38 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) 39 { 40 struct dpu_hw_blk_reg_map *c = &dsc->hw; 41 42 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); 43 } 44 45 static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, 46 struct drm_dsc_config *dsc, 47 u32 mode, 48 u32 initial_lines) 49 { 50 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 51 u32 data; 52 u32 slice_last_group_size; 53 u32 det_thresh_flatness; 54 bool is_cmd_mode = !(mode & DSC_MODE_VIDEO); 55 56 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); 57 58 if (is_cmd_mode) 59 initial_lines += 1; 60 61 slice_last_group_size = (dsc->slice_width + 2) % 3; 62 63 data = (initial_lines << 20); 64 data |= (slice_last_group_size << 18); 65 /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ 66 data |= (dsc->bits_per_pixel << 8); 67 data |= (dsc->block_pred_enable << 7); 68 data |= (dsc->line_buf_depth << 3); 69 data |= (dsc->simple_422 << 2); 70 data |= (dsc->convert_rgb << 1); 71 data |= dsc->bits_per_component; 72 73 DPU_REG_WRITE(c, DSC_ENC, data); 74 75 data = dsc->pic_width << 16; 76 data |= dsc->pic_height; 77 DPU_REG_WRITE(c, DSC_PICTURE, data); 78 79 data = dsc->slice_width << 16; 80 data |= dsc->slice_height; 81 DPU_REG_WRITE(c, DSC_SLICE, data); 82 83 data = dsc->slice_chunk_size << 16; 84 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); 85 86 data = dsc->initial_dec_delay << 16; 87 data |= dsc->initial_xmit_delay; 88 DPU_REG_WRITE(c, DSC_DELAY, data); 89 90 data = dsc->initial_scale_value; 91 DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data); 92 93 data = dsc->scale_decrement_interval; 94 DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data); 95 96 data = dsc->scale_increment_interval; 97 DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data); 98 99 data = dsc->first_line_bpg_offset; 100 DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data); 101 102 data = dsc->nfl_bpg_offset << 16; 103 data |= dsc->slice_bpg_offset; 104 DPU_REG_WRITE(c, DSC_BPG_OFFSET, data); 105 106 data = dsc->initial_offset << 16; 107 data |= dsc->final_offset; 108 DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); 109 110 det_thresh_flatness = drm_dsc_flatness_det_thresh(dsc); 111 data = det_thresh_flatness << 10; 112 data |= dsc->flatness_max_qp << 5; 113 data |= dsc->flatness_min_qp; 114 DPU_REG_WRITE(c, DSC_FLATNESS, data); 115 116 data = dsc->rc_model_size; 117 DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data); 118 119 data = dsc->rc_tgt_offset_low << 18; 120 data |= dsc->rc_tgt_offset_high << 14; 121 data |= dsc->rc_quant_incr_limit1 << 9; 122 data |= dsc->rc_quant_incr_limit0 << 4; 123 data |= dsc->rc_edge_factor; 124 DPU_REG_WRITE(c, DSC_RC, data); 125 } 126 127 static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc, 128 struct drm_dsc_config *dsc) 129 { 130 struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params; 131 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 132 u32 off; 133 int i; 134 135 off = DSC_RC_BUF_THRESH; 136 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) { 137 DPU_REG_WRITE(c, off, dsc->rc_buf_thresh[i]); 138 off += 4; 139 } 140 141 off = DSC_RANGE_MIN_QP; 142 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 143 DPU_REG_WRITE(c, off, rc[i].range_min_qp); 144 off += 4; 145 } 146 147 off = DSC_RANGE_MAX_QP; 148 for (i = 0; i < 15; i++) { 149 DPU_REG_WRITE(c, off, rc[i].range_max_qp); 150 off += 4; 151 } 152 153 off = DSC_RANGE_BPG_OFFSET; 154 for (i = 0; i < 15; i++) { 155 DPU_REG_WRITE(c, off, rc[i].range_bpg_offset); 156 off += 4; 157 } 158 } 159 160 static void dpu_hw_dsc_bind_pingpong_blk( 161 struct dpu_hw_dsc *hw_dsc, 162 const enum dpu_pingpong pp) 163 { 164 struct dpu_hw_blk_reg_map *c = &hw_dsc->hw; 165 int mux_cfg = 0xF; 166 u32 dsc_ctl_offset; 167 168 dsc_ctl_offset = DSC_CTL(hw_dsc->idx); 169 170 if (pp) 171 mux_cfg = (pp - PINGPONG_0) & 0x7; 172 173 if (pp) 174 DRM_DEBUG_KMS("Binding dsc:%d to pp:%d\n", 175 hw_dsc->idx - DSC_0, pp - PINGPONG_0); 176 else 177 DRM_DEBUG_KMS("Unbinding dsc:%d from any pp\n", 178 hw_dsc->idx - DSC_0); 179 180 DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); 181 } 182 183 static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, 184 unsigned long cap) 185 { 186 ops->dsc_disable = dpu_hw_dsc_disable; 187 ops->dsc_config = dpu_hw_dsc_config; 188 ops->dsc_config_thresh = dpu_hw_dsc_config_thresh; 189 if (cap & BIT(DPU_DSC_OUTPUT_CTRL)) 190 ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk; 191 }; 192 193 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, 194 const struct dpu_dsc_cfg *cfg, 195 void __iomem *addr) 196 { 197 struct dpu_hw_dsc *c; 198 199 c = drmm_kzalloc(dev, sizeof(*c), GFP_KERNEL); 200 if (!c) 201 return ERR_PTR(-ENOMEM); 202 203 c->hw.blk_addr = addr + cfg->base; 204 c->hw.log_mask = DPU_DBG_MASK_DSC; 205 206 c->idx = cfg->id; 207 c->caps = cfg; 208 _setup_dsc_ops(&c->ops, c->caps->features); 209 210 return c; 211 } 212