1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved 4 */ 5 6 #include "dpu_hw_mdss.h" 7 #include "dpu_hwio.h" 8 #include "dpu_hw_catalog.h" 9 #include "dpu_hw_wb.h" 10 #include "dpu_formats.h" 11 #include "dpu_kms.h" 12 13 #define WB_DST_FORMAT 0x000 14 #define WB_DST_OP_MODE 0x004 15 #define WB_DST_PACK_PATTERN 0x008 16 #define WB_DST0_ADDR 0x00C 17 #define WB_DST1_ADDR 0x010 18 #define WB_DST2_ADDR 0x014 19 #define WB_DST3_ADDR 0x018 20 #define WB_DST_YSTRIDE0 0x01C 21 #define WB_DST_YSTRIDE1 0x020 22 #define WB_DST_YSTRIDE1 0x020 23 #define WB_DST_DITHER_BITDEPTH 0x024 24 #define WB_DST_MATRIX_ROW0 0x030 25 #define WB_DST_MATRIX_ROW1 0x034 26 #define WB_DST_MATRIX_ROW2 0x038 27 #define WB_DST_MATRIX_ROW3 0x03C 28 #define WB_DST_WRITE_CONFIG 0x048 29 #define WB_ROTATION_DNSCALER 0x050 30 #define WB_ROTATOR_PIPE_DOWNSCALER 0x054 31 #define WB_N16_INIT_PHASE_X_C03 0x060 32 #define WB_N16_INIT_PHASE_X_C12 0x064 33 #define WB_N16_INIT_PHASE_Y_C03 0x068 34 #define WB_N16_INIT_PHASE_Y_C12 0x06C 35 #define WB_OUT_SIZE 0x074 36 #define WB_ALPHA_X_VALUE 0x078 37 #define WB_DANGER_LUT 0x084 38 #define WB_SAFE_LUT 0x088 39 #define WB_QOS_CTRL 0x090 40 #define WB_CREQ_LUT_0 0x098 41 #define WB_CREQ_LUT_1 0x09C 42 #define WB_UBWC_STATIC_CTRL 0x144 43 #define WB_MUX 0x150 44 #define WB_CROP_CTRL 0x154 45 #define WB_CROP_OFFSET 0x158 46 #define WB_CSC_BASE 0x260 47 #define WB_DST_ADDR_SW_STATUS 0x2B0 48 #define WB_CDP_CNTL 0x2B4 49 #define WB_OUT_IMAGE_SIZE 0x2C0 50 #define WB_OUT_XY 0x2C4 51 52 /* WB_QOS_CTRL */ 53 #define WB_QOS_CTRL_DANGER_SAFE_EN BIT(0) 54 55 static const struct dpu_wb_cfg *_wb_offset(enum dpu_wb wb, 56 const struct dpu_mdss_cfg *m, void __iomem *addr, 57 struct dpu_hw_blk_reg_map *b) 58 { 59 int i; 60 61 for (i = 0; i < m->wb_count; i++) { 62 if (wb == m->wb[i].id) { 63 b->blk_addr = addr + m->wb[i].base; 64 return &m->wb[i]; 65 } 66 } 67 return ERR_PTR(-EINVAL); 68 } 69 70 static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx, 71 struct dpu_hw_wb_cfg *data) 72 { 73 struct dpu_hw_blk_reg_map *c = &ctx->hw; 74 75 DPU_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]); 76 DPU_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]); 77 DPU_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]); 78 DPU_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]); 79 } 80 81 static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx, 82 struct dpu_hw_wb_cfg *data) 83 { 84 struct dpu_hw_blk_reg_map *c = &ctx->hw; 85 const struct dpu_format *fmt = data->dest.format; 86 u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp; 87 u32 write_config = 0; 88 u32 opmode = 0; 89 u32 dst_addr_sw = 0; 90 91 chroma_samp = fmt->chroma_sample; 92 93 dst_format = (chroma_samp << 23) | 94 (fmt->fetch_planes << 19) | 95 (fmt->bits[C3_ALPHA] << 6) | 96 (fmt->bits[C2_R_Cr] << 4) | 97 (fmt->bits[C1_B_Cb] << 2) | 98 (fmt->bits[C0_G_Y] << 0); 99 100 if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) { 101 dst_format |= BIT(8); /* DSTC3_EN */ 102 if (!fmt->alpha_enable || 103 !(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA))) 104 dst_format |= BIT(14); /* DST_ALPHA_X */ 105 } 106 107 pattern = (fmt->element[3] << 24) | 108 (fmt->element[2] << 16) | 109 (fmt->element[1] << 8) | 110 (fmt->element[0] << 0); 111 112 dst_format |= (fmt->unpack_align_msb << 18) | 113 (fmt->unpack_tight << 17) | 114 ((fmt->unpack_count - 1) << 12) | 115 ((fmt->bpp - 1) << 9); 116 117 ystride0 = data->dest.plane_pitch[0] | 118 (data->dest.plane_pitch[1] << 16); 119 ystride1 = data->dest.plane_pitch[2] | 120 (data->dest.plane_pitch[3] << 16); 121 122 if (drm_rect_height(&data->roi) && drm_rect_width(&data->roi)) 123 outsize = (drm_rect_height(&data->roi) << 16) | drm_rect_width(&data->roi); 124 else 125 outsize = (data->dest.height << 16) | data->dest.width; 126 127 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF); 128 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format); 129 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode); 130 DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern); 131 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0); 132 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1); 133 DPU_REG_WRITE(c, WB_OUT_SIZE, outsize); 134 DPU_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config); 135 DPU_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw); 136 } 137 138 static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb) 139 { 140 struct dpu_hw_blk_reg_map *c = &ctx->hw; 141 u32 image_size, out_size, out_xy; 142 143 image_size = (wb->dest.height << 16) | wb->dest.width; 144 out_xy = 0; 145 out_size = (drm_rect_height(&wb->roi) << 16) | drm_rect_width(&wb->roi); 146 147 DPU_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size); 148 DPU_REG_WRITE(c, WB_OUT_XY, out_xy); 149 DPU_REG_WRITE(c, WB_OUT_SIZE, out_size); 150 } 151 152 static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, 153 struct dpu_hw_wb_qos_cfg *cfg) 154 { 155 struct dpu_hw_blk_reg_map *c = &ctx->hw; 156 u32 qos_ctrl = 0; 157 158 if (!ctx || !cfg) 159 return; 160 161 DPU_REG_WRITE(c, WB_DANGER_LUT, cfg->danger_lut); 162 DPU_REG_WRITE(c, WB_SAFE_LUT, cfg->safe_lut); 163 164 /* 165 * for chipsets not using DPU_WB_QOS_8LVL but still using DPU 166 * driver such as msm8998, the reset value of WB_CREQ_LUT is 167 * sufficient for writeback to work. SW doesn't need to explicitly 168 * program a value. 169 */ 170 if (ctx->caps && test_bit(DPU_WB_QOS_8LVL, &ctx->caps->features)) { 171 DPU_REG_WRITE(c, WB_CREQ_LUT_0, cfg->creq_lut); 172 DPU_REG_WRITE(c, WB_CREQ_LUT_1, cfg->creq_lut >> 32); 173 } 174 175 if (cfg->danger_safe_en) 176 qos_ctrl |= WB_QOS_CTRL_DANGER_SAFE_EN; 177 178 DPU_REG_WRITE(c, WB_QOS_CTRL, qos_ctrl); 179 } 180 181 static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, 182 struct dpu_hw_cdp_cfg *cfg) 183 { 184 struct dpu_hw_blk_reg_map *c; 185 u32 cdp_cntl = 0; 186 187 if (!ctx || !cfg) 188 return; 189 190 c = &ctx->hw; 191 192 if (cfg->enable) 193 cdp_cntl |= BIT(0); 194 if (cfg->ubwc_meta_enable) 195 cdp_cntl |= BIT(1); 196 if (cfg->preload_ahead == DPU_WB_CDP_PRELOAD_AHEAD_64) 197 cdp_cntl |= BIT(3); 198 199 DPU_REG_WRITE(c, WB_CDP_CNTL, cdp_cntl); 200 } 201 202 static void dpu_hw_wb_bind_pingpong_blk( 203 struct dpu_hw_wb *ctx, 204 bool enable, const enum dpu_pingpong pp) 205 { 206 struct dpu_hw_blk_reg_map *c; 207 int mux_cfg; 208 209 if (!ctx) 210 return; 211 212 c = &ctx->hw; 213 214 mux_cfg = DPU_REG_READ(c, WB_MUX); 215 mux_cfg &= ~0xf; 216 217 if (enable) 218 mux_cfg |= (pp - PINGPONG_0) & 0x7; 219 else 220 mux_cfg |= 0xf; 221 222 DPU_REG_WRITE(c, WB_MUX, mux_cfg); 223 } 224 225 static void _setup_wb_ops(struct dpu_hw_wb_ops *ops, 226 unsigned long features) 227 { 228 ops->setup_outaddress = dpu_hw_wb_setup_outaddress; 229 ops->setup_outformat = dpu_hw_wb_setup_format; 230 231 if (test_bit(DPU_WB_XY_ROI_OFFSET, &features)) 232 ops->setup_roi = dpu_hw_wb_roi; 233 234 if (test_bit(DPU_WB_QOS, &features)) 235 ops->setup_qos_lut = dpu_hw_wb_setup_qos_lut; 236 237 if (test_bit(DPU_WB_CDP, &features)) 238 ops->setup_cdp = dpu_hw_wb_setup_cdp; 239 240 if (test_bit(DPU_WB_INPUT_CTRL, &features)) 241 ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk; 242 } 243 244 struct dpu_hw_wb *dpu_hw_wb_init(enum dpu_wb idx, 245 void __iomem *addr, const struct dpu_mdss_cfg *m) 246 { 247 struct dpu_hw_wb *c; 248 const struct dpu_wb_cfg *cfg; 249 250 if (!addr || !m) 251 return ERR_PTR(-EINVAL); 252 253 c = kzalloc(sizeof(*c), GFP_KERNEL); 254 if (!c) 255 return ERR_PTR(-ENOMEM); 256 257 cfg = _wb_offset(idx, m, addr, &c->hw); 258 if (IS_ERR(cfg)) { 259 WARN(1, "Unable to find wb idx=%d\n", idx); 260 kfree(c); 261 return ERR_PTR(-EINVAL); 262 } 263 264 /* Assign ops */ 265 c->mdp = &m->mdp[0]; 266 c->idx = idx; 267 c->caps = cfg; 268 _setup_wb_ops(&c->ops, c->caps->features); 269 270 return c; 271 } 272 273 void dpu_hw_wb_destroy(struct dpu_hw_wb *hw_wb) 274 { 275 kfree(hw_wb); 276 } 277