1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <drm/drm_crtc.h>
7 #include <drm/drm_probe_helper.h>
8 
9 #include "mdp5_kms.h"
10 
11 static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
12 {
13 	struct msm_drm_private *priv = encoder->dev->dev_private;
14 	return to_mdp5_kms(to_mdp_kms(priv->kms));
15 }
16 
17 #define VSYNC_CLK_RATE 19200000
18 static int pingpong_tearcheck_setup(struct drm_encoder *encoder,
19 				    struct drm_display_mode *mode)
20 {
21 	struct mdp5_kms *mdp5_kms = get_kms(encoder);
22 	struct device *dev = encoder->dev->dev;
23 	u32 total_lines, vclks_line, cfg;
24 	long vsync_clk_speed;
25 	struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
26 	int pp_id = mixer->pp;
27 
28 	if (IS_ERR_OR_NULL(mdp5_kms->vsync_clk)) {
29 		DRM_DEV_ERROR(dev, "vsync_clk is not initialized\n");
30 		return -EINVAL;
31 	}
32 
33 	total_lines = mode->vtotal * drm_mode_vrefresh(mode);
34 	if (!total_lines) {
35 		DRM_DEV_ERROR(dev, "%s: vtotal(%d) or vrefresh(%d) is 0\n",
36 			      __func__, mode->vtotal, drm_mode_vrefresh(mode));
37 		return -EINVAL;
38 	}
39 
40 	vsync_clk_speed = clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE);
41 	if (vsync_clk_speed <= 0) {
42 		DRM_DEV_ERROR(dev, "vsync_clk round rate failed %ld\n",
43 							vsync_clk_speed);
44 		return -EINVAL;
45 	}
46 	vclks_line = vsync_clk_speed / total_lines;
47 
48 	cfg = MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN
49 		| MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN;
50 	cfg |= MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(vclks_line);
51 
52 	/*
53 	 * Tearcheck emits a blanking signal every vclks_line * vtotal * 2 ticks on
54 	 * the vsync_clk equating to roughly half the desired panel refresh rate.
55 	 * This is only necessary as stability fallback if interrupts from the
56 	 * panel arrive too late or not at all, but is currently used by default
57 	 * because these panel interrupts are not wired up yet.
58 	 */
59 	mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_CONFIG_VSYNC(pp_id), cfg);
60 	mdp5_write(mdp5_kms,
61 		REG_MDP5_PP_SYNC_CONFIG_HEIGHT(pp_id), (2 * mode->vtotal));
62 
63 	mdp5_write(mdp5_kms,
64 		REG_MDP5_PP_VSYNC_INIT_VAL(pp_id), mode->vdisplay);
65 	mdp5_write(mdp5_kms, REG_MDP5_PP_RD_PTR_IRQ(pp_id), mode->vdisplay + 1);
66 	mdp5_write(mdp5_kms, REG_MDP5_PP_START_POS(pp_id), mode->vdisplay);
67 	mdp5_write(mdp5_kms, REG_MDP5_PP_SYNC_THRESH(pp_id),
68 			MDP5_PP_SYNC_THRESH_START(4) |
69 			MDP5_PP_SYNC_THRESH_CONTINUE(4));
70 	mdp5_write(mdp5_kms, REG_MDP5_PP_AUTOREFRESH_CONFIG(pp_id), 0x0);
71 
72 	return 0;
73 }
74 
75 static int pingpong_tearcheck_enable(struct drm_encoder *encoder)
76 {
77 	struct mdp5_kms *mdp5_kms = get_kms(encoder);
78 	struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
79 	int pp_id = mixer->pp;
80 	int ret;
81 
82 	ret = clk_set_rate(mdp5_kms->vsync_clk,
83 		clk_round_rate(mdp5_kms->vsync_clk, VSYNC_CLK_RATE));
84 	if (ret) {
85 		DRM_DEV_ERROR(encoder->dev->dev,
86 			"vsync_clk clk_set_rate failed, %d\n", ret);
87 		return ret;
88 	}
89 	ret = clk_prepare_enable(mdp5_kms->vsync_clk);
90 	if (ret) {
91 		DRM_DEV_ERROR(encoder->dev->dev,
92 			"vsync_clk clk_prepare_enable failed, %d\n", ret);
93 		return ret;
94 	}
95 
96 	mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 1);
97 
98 	return 0;
99 }
100 
101 static void pingpong_tearcheck_disable(struct drm_encoder *encoder)
102 {
103 	struct mdp5_kms *mdp5_kms = get_kms(encoder);
104 	struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
105 	int pp_id = mixer->pp;
106 
107 	mdp5_write(mdp5_kms, REG_MDP5_PP_TEAR_CHECK_EN(pp_id), 0);
108 	clk_disable_unprepare(mdp5_kms->vsync_clk);
109 }
110 
111 void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder,
112 			       struct drm_display_mode *mode,
113 			       struct drm_display_mode *adjusted_mode)
114 {
115 	mode = adjusted_mode;
116 
117 	DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
118 	pingpong_tearcheck_setup(encoder, mode);
119 	mdp5_crtc_set_pipeline(encoder->crtc);
120 }
121 
122 void mdp5_cmd_encoder_disable(struct drm_encoder *encoder)
123 {
124 	struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
125 	struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
126 	struct mdp5_interface *intf = mdp5_cmd_enc->intf;
127 	struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
128 
129 	if (WARN_ON(!mdp5_cmd_enc->enabled))
130 		return;
131 
132 	pingpong_tearcheck_disable(encoder);
133 
134 	mdp5_ctl_set_encoder_state(ctl, pipeline, false);
135 	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
136 
137 	mdp5_cmd_enc->enabled = false;
138 }
139 
140 void mdp5_cmd_encoder_enable(struct drm_encoder *encoder)
141 {
142 	struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
143 	struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl;
144 	struct mdp5_interface *intf = mdp5_cmd_enc->intf;
145 	struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
146 
147 	if (WARN_ON(mdp5_cmd_enc->enabled))
148 		return;
149 
150 	if (pingpong_tearcheck_enable(encoder))
151 		return;
152 
153 	mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
154 
155 	mdp5_ctl_set_encoder_state(ctl, pipeline, true);
156 
157 	mdp5_cmd_enc->enabled = true;
158 }
159 
160 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
161 				       struct drm_encoder *slave_encoder)
162 {
163 	struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder);
164 	struct mdp5_kms *mdp5_kms;
165 	struct device *dev;
166 	int intf_num;
167 	u32 data = 0;
168 
169 	if (!encoder || !slave_encoder)
170 		return -EINVAL;
171 
172 	mdp5_kms = get_kms(encoder);
173 	intf_num = mdp5_cmd_enc->intf->num;
174 
175 	/* Switch slave encoder's trigger MUX, to use the master's
176 	 * start signal for the slave encoder
177 	 */
178 	if (intf_num == 1)
179 		data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX;
180 	else if (intf_num == 2)
181 		data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX;
182 	else
183 		return -EINVAL;
184 
185 	/* Smart Panel, Sync mode */
186 	data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL;
187 
188 	dev = &mdp5_kms->pdev->dev;
189 
190 	/* Make sure clocks are on when connectors calling this function. */
191 	pm_runtime_get_sync(dev);
192 	mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data);
193 
194 	mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER,
195 		   MDP5_SPLIT_DPL_LOWER_SMART_PANEL);
196 	mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
197 	pm_runtime_put_sync(dev);
198 
199 	return 0;
200 }
201