1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include "dsi_cfg.h" 7 8 static const char * const dsi_v2_bus_clk_names[] = { 9 "core_mmss", "iface", "bus", 10 }; 11 12 static const struct msm_dsi_config apq8064_dsi_cfg = { 13 .io_offset = 0, 14 .reg_cfg = { 15 .num = 3, 16 .regs = { 17 {"vdda", 100000, 100}, /* 1.2 V */ 18 {"avdd", 10000, 100}, /* 3.0 V */ 19 {"vddio", 100000, 100}, /* 1.8 V */ 20 }, 21 }, 22 .bus_clk_names = dsi_v2_bus_clk_names, 23 .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names), 24 .io_start = { 0x4700000, 0x5800000 }, 25 .num_dsi = 2, 26 }; 27 28 static const char * const dsi_6g_bus_clk_names[] = { 29 "mdp_core", "iface", "bus", "core_mmss", 30 }; 31 32 static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = { 33 .io_offset = DSI_6G_REG_SHIFT, 34 .reg_cfg = { 35 .num = 4, 36 .regs = { 37 {"gdsc", -1, -1}, 38 {"vdd", 150000, 100}, /* 3.0 V */ 39 {"vdda", 100000, 100}, /* 1.2 V */ 40 {"vddio", 100000, 100}, /* 1.8 V */ 41 }, 42 }, 43 .bus_clk_names = dsi_6g_bus_clk_names, 44 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), 45 .io_start = { 0xfd922800, 0xfd922b00 }, 46 .num_dsi = 2, 47 }; 48 49 static const char * const dsi_8916_bus_clk_names[] = { 50 "mdp_core", "iface", "bus", 51 }; 52 53 static const struct msm_dsi_config msm8916_dsi_cfg = { 54 .io_offset = DSI_6G_REG_SHIFT, 55 .reg_cfg = { 56 .num = 3, 57 .regs = { 58 {"gdsc", -1, -1}, 59 {"vdda", 100000, 100}, /* 1.2 V */ 60 {"vddio", 100000, 100}, /* 1.8 V */ 61 }, 62 }, 63 .bus_clk_names = dsi_8916_bus_clk_names, 64 .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names), 65 .io_start = { 0x1a98000 }, 66 .num_dsi = 1, 67 }; 68 69 static const struct msm_dsi_config msm8994_dsi_cfg = { 70 .io_offset = DSI_6G_REG_SHIFT, 71 .reg_cfg = { 72 .num = 7, 73 .regs = { 74 {"gdsc", -1, -1}, 75 {"vdda", 100000, 100}, /* 1.25 V */ 76 {"vddio", 100000, 100}, /* 1.8 V */ 77 {"vcca", 10000, 100}, /* 1.0 V */ 78 {"vdd", 100000, 100}, /* 1.8 V */ 79 {"lab_reg", -1, -1}, 80 {"ibb_reg", -1, -1}, 81 }, 82 }, 83 .bus_clk_names = dsi_6g_bus_clk_names, 84 .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), 85 .io_start = { 0xfd998000, 0xfd9a0000 }, 86 .num_dsi = 2, 87 }; 88 89 /* 90 * TODO: core_mmss_clk fails to enable for some reason, but things work fine 91 * without it too. Figure out why it doesn't enable and uncomment below 92 */ 93 static const char * const dsi_8996_bus_clk_names[] = { 94 "mdp_core", "iface", "bus", /* "core_mmss", */ 95 }; 96 97 static const struct msm_dsi_config msm8996_dsi_cfg = { 98 .io_offset = DSI_6G_REG_SHIFT, 99 .reg_cfg = { 100 .num = 2, 101 .regs = { 102 {"vdda", 18160, 1 }, /* 1.25 V */ 103 {"vcca", 17000, 32 }, /* 0.925 V */ 104 {"vddio", 100000, 100 },/* 1.8 V */ 105 }, 106 }, 107 .bus_clk_names = dsi_8996_bus_clk_names, 108 .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names), 109 .io_start = { 0x994000, 0x996000 }, 110 .num_dsi = 2, 111 }; 112 113 static const char * const dsi_sdm845_bus_clk_names[] = { 114 "iface", "bus", 115 }; 116 117 static const struct msm_dsi_config sdm845_dsi_cfg = { 118 .io_offset = DSI_6G_REG_SHIFT, 119 .reg_cfg = { 120 .num = 1, 121 .regs = { 122 {"vdda", 21800, 4 }, /* 1.2 V */ 123 }, 124 }, 125 .bus_clk_names = dsi_sdm845_bus_clk_names, 126 .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names), 127 .io_start = { 0xae94000, 0xae96000 }, 128 .num_dsi = 2, 129 }; 130 131 const static struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { 132 .link_clk_enable = dsi_link_clk_enable_v2, 133 .link_clk_disable = dsi_link_clk_disable_v2, 134 .clk_init_ver = dsi_clk_init_v2, 135 .tx_buf_alloc = dsi_tx_buf_alloc_v2, 136 .tx_buf_get = dsi_tx_buf_get_v2, 137 .tx_buf_put = NULL, 138 .dma_base_get = dsi_dma_base_get_v2, 139 .calc_clk_rate = dsi_calc_clk_rate_v2, 140 }; 141 142 const static struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = { 143 .link_clk_enable = dsi_link_clk_enable_6g, 144 .link_clk_disable = dsi_link_clk_disable_6g, 145 .clk_init_ver = NULL, 146 .tx_buf_alloc = dsi_tx_buf_alloc_6g, 147 .tx_buf_get = dsi_tx_buf_get_6g, 148 .tx_buf_put = dsi_tx_buf_put_6g, 149 .dma_base_get = dsi_dma_base_get_6g, 150 .calc_clk_rate = dsi_calc_clk_rate_6g, 151 }; 152 153 const static struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = { 154 .link_clk_enable = dsi_link_clk_enable_6g, 155 .link_clk_disable = dsi_link_clk_disable_6g, 156 .clk_init_ver = dsi_clk_init_6g_v2, 157 .tx_buf_alloc = dsi_tx_buf_alloc_6g, 158 .tx_buf_get = dsi_tx_buf_get_6g, 159 .tx_buf_put = dsi_tx_buf_put_6g, 160 .dma_base_get = dsi_dma_base_get_6g, 161 .calc_clk_rate = dsi_calc_clk_rate_6g, 162 }; 163 164 static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { 165 {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, 166 &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, 167 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, 168 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, 169 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1, 170 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, 171 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1, 172 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, 173 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2, 174 &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, 175 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, 176 &msm8994_dsi_cfg, &msm_dsi_6g_host_ops}, 177 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, 178 &msm8916_dsi_cfg, &msm_dsi_6g_host_ops}, 179 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, 180 &msm8996_dsi_cfg, &msm_dsi_6g_host_ops}, 181 {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, 182 &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, 183 }; 184 185 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) 186 { 187 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 188 int i; 189 190 for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) { 191 if ((dsi_cfg_handlers[i].major == major) && 192 (dsi_cfg_handlers[i].minor == minor)) { 193 cfg_hnd = &dsi_cfg_handlers[i]; 194 break; 195 } 196 } 197 198 return cfg_hnd; 199 } 200 201