xref: /linux/drivers/gpu/drm/msm/dsi/dsi_host.c (revision db10cb9b)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/err.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_opp.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spinlock.h>
21 
22 #include <video/mipi_display.h>
23 
24 #include <drm/display/drm_dsc_helper.h>
25 #include <drm/drm_of.h>
26 
27 #include "dsi.h"
28 #include "dsi.xml.h"
29 #include "sfpb.xml.h"
30 #include "dsi_cfg.h"
31 #include "msm_dsc_helper.h"
32 #include "msm_kms.h"
33 #include "msm_gem.h"
34 #include "phy/dsi_phy.h"
35 
36 #define DSI_RESET_TOGGLE_DELAY_MS 20
37 
38 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
39 
40 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
41 {
42 	u32 ver;
43 
44 	if (!major || !minor)
45 		return -EINVAL;
46 
47 	/*
48 	 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
49 	 * makes all other registers 4-byte shifted down.
50 	 *
51 	 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
52 	 * older, we read the DSI_VERSION register without any shift(offset
53 	 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
54 	 * the case of DSI6G, this has to be zero (the offset points to a
55 	 * scratch register which we never touch)
56 	 */
57 
58 	ver = msm_readl(base + REG_DSI_VERSION);
59 	if (ver) {
60 		/* older dsi host, there is no register shift */
61 		ver = FIELD(ver, DSI_VERSION_MAJOR);
62 		if (ver <= MSM_DSI_VER_MAJOR_V2) {
63 			/* old versions */
64 			*major = ver;
65 			*minor = 0;
66 			return 0;
67 		} else {
68 			return -EINVAL;
69 		}
70 	} else {
71 		/*
72 		 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
73 		 * registers are shifted down, read DSI_VERSION again with
74 		 * the shifted offset
75 		 */
76 		ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
77 		ver = FIELD(ver, DSI_VERSION_MAJOR);
78 		if (ver == MSM_DSI_VER_MAJOR_6G) {
79 			/* 6G version */
80 			*major = ver;
81 			*minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
82 			return 0;
83 		} else {
84 			return -EINVAL;
85 		}
86 	}
87 }
88 
89 #define DSI_ERR_STATE_ACK			0x0000
90 #define DSI_ERR_STATE_TIMEOUT			0x0001
91 #define DSI_ERR_STATE_DLN0_PHY			0x0002
92 #define DSI_ERR_STATE_FIFO			0x0004
93 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW	0x0008
94 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION	0x0010
95 #define DSI_ERR_STATE_PLL_UNLOCKED		0x0020
96 
97 #define DSI_CLK_CTRL_ENABLE_CLKS	\
98 		(DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
99 		DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
100 		DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
101 		DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
102 
103 struct msm_dsi_host {
104 	struct mipi_dsi_host base;
105 
106 	struct platform_device *pdev;
107 	struct drm_device *dev;
108 
109 	int id;
110 
111 	void __iomem *ctrl_base;
112 	phys_addr_t ctrl_size;
113 	struct regulator_bulk_data *supplies;
114 
115 	int num_bus_clks;
116 	struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX];
117 
118 	struct clk *byte_clk;
119 	struct clk *esc_clk;
120 	struct clk *pixel_clk;
121 	struct clk *byte_intf_clk;
122 
123 	unsigned long byte_clk_rate;
124 	unsigned long byte_intf_clk_rate;
125 	unsigned long pixel_clk_rate;
126 	unsigned long esc_clk_rate;
127 
128 	/* DSI v2 specific clocks */
129 	struct clk *src_clk;
130 
131 	unsigned long src_clk_rate;
132 
133 	struct gpio_desc *disp_en_gpio;
134 	struct gpio_desc *te_gpio;
135 
136 	const struct msm_dsi_cfg_handler *cfg_hnd;
137 
138 	struct completion dma_comp;
139 	struct completion video_comp;
140 	struct mutex dev_mutex;
141 	struct mutex cmd_mutex;
142 	spinlock_t intr_lock; /* Protect interrupt ctrl register */
143 
144 	u32 err_work_state;
145 	struct work_struct err_work;
146 	struct workqueue_struct *workqueue;
147 
148 	/* DSI 6G TX buffer*/
149 	struct drm_gem_object *tx_gem_obj;
150 
151 	/* DSI v2 TX buffer */
152 	void *tx_buf;
153 	dma_addr_t tx_buf_paddr;
154 
155 	int tx_size;
156 
157 	u8 *rx_buf;
158 
159 	struct regmap *sfpb;
160 
161 	struct drm_display_mode *mode;
162 	struct drm_dsc_config *dsc;
163 
164 	/* connected device info */
165 	unsigned int channel;
166 	unsigned int lanes;
167 	enum mipi_dsi_pixel_format format;
168 	unsigned long mode_flags;
169 
170 	/* lane data parsed via DT */
171 	int dlane_swap;
172 	int num_data_lanes;
173 
174 	/* from phy DT */
175 	bool cphy_mode;
176 
177 	u32 dma_cmd_ctrl_restore;
178 
179 	bool registered;
180 	bool power_on;
181 	bool enabled;
182 	int irq;
183 };
184 
185 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
186 {
187 	switch (fmt) {
188 	case MIPI_DSI_FMT_RGB565:		return 16;
189 	case MIPI_DSI_FMT_RGB666_PACKED:	return 18;
190 	case MIPI_DSI_FMT_RGB666:
191 	case MIPI_DSI_FMT_RGB888:
192 	default:				return 24;
193 	}
194 }
195 
196 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
197 {
198 	return msm_readl(msm_host->ctrl_base + reg);
199 }
200 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
201 {
202 	msm_writel(data, msm_host->ctrl_base + reg);
203 }
204 
205 static const struct msm_dsi_cfg_handler *dsi_get_config(
206 						struct msm_dsi_host *msm_host)
207 {
208 	const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
209 	struct device *dev = &msm_host->pdev->dev;
210 	struct clk *ahb_clk;
211 	int ret;
212 	u32 major = 0, minor = 0;
213 
214 	ahb_clk = msm_clk_get(msm_host->pdev, "iface");
215 	if (IS_ERR(ahb_clk)) {
216 		pr_err("%s: cannot get interface clock\n", __func__);
217 		goto exit;
218 	}
219 
220 	pm_runtime_get_sync(dev);
221 
222 	ret = clk_prepare_enable(ahb_clk);
223 	if (ret) {
224 		pr_err("%s: unable to enable ahb_clk\n", __func__);
225 		goto runtime_put;
226 	}
227 
228 	ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
229 	if (ret) {
230 		pr_err("%s: Invalid version\n", __func__);
231 		goto disable_clks;
232 	}
233 
234 	cfg_hnd = msm_dsi_cfg_get(major, minor);
235 
236 	DBG("%s: Version %x:%x\n", __func__, major, minor);
237 
238 disable_clks:
239 	clk_disable_unprepare(ahb_clk);
240 runtime_put:
241 	pm_runtime_put_sync(dev);
242 exit:
243 	return cfg_hnd;
244 }
245 
246 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
247 {
248 	return container_of(host, struct msm_dsi_host, base);
249 }
250 
251 int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
252 {
253 	struct platform_device *pdev = msm_host->pdev;
254 	int ret = 0;
255 
256 	msm_host->src_clk = msm_clk_get(pdev, "src");
257 
258 	if (IS_ERR(msm_host->src_clk)) {
259 		ret = PTR_ERR(msm_host->src_clk);
260 		pr_err("%s: can't find src clock. ret=%d\n",
261 			__func__, ret);
262 		msm_host->src_clk = NULL;
263 		return ret;
264 	}
265 
266 	return ret;
267 }
268 
269 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
270 {
271 	struct platform_device *pdev = msm_host->pdev;
272 	int ret = 0;
273 
274 	msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
275 	if (IS_ERR(msm_host->byte_intf_clk)) {
276 		ret = PTR_ERR(msm_host->byte_intf_clk);
277 		pr_err("%s: can't find byte_intf clock. ret=%d\n",
278 			__func__, ret);
279 	}
280 
281 	return ret;
282 }
283 
284 static int dsi_clk_init(struct msm_dsi_host *msm_host)
285 {
286 	struct platform_device *pdev = msm_host->pdev;
287 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
288 	const struct msm_dsi_config *cfg = cfg_hnd->cfg;
289 	int i, ret = 0;
290 
291 	/* get bus clocks */
292 	for (i = 0; i < cfg->num_bus_clks; i++)
293 		msm_host->bus_clks[i].id = cfg->bus_clk_names[i];
294 	msm_host->num_bus_clks = cfg->num_bus_clks;
295 
296 	ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks);
297 	if (ret < 0) {
298 		dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret);
299 		goto exit;
300 	}
301 
302 	/* get link and source clocks */
303 	msm_host->byte_clk = msm_clk_get(pdev, "byte");
304 	if (IS_ERR(msm_host->byte_clk)) {
305 		ret = PTR_ERR(msm_host->byte_clk);
306 		pr_err("%s: can't find dsi_byte clock. ret=%d\n",
307 			__func__, ret);
308 		msm_host->byte_clk = NULL;
309 		goto exit;
310 	}
311 
312 	msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
313 	if (IS_ERR(msm_host->pixel_clk)) {
314 		ret = PTR_ERR(msm_host->pixel_clk);
315 		pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
316 			__func__, ret);
317 		msm_host->pixel_clk = NULL;
318 		goto exit;
319 	}
320 
321 	msm_host->esc_clk = msm_clk_get(pdev, "core");
322 	if (IS_ERR(msm_host->esc_clk)) {
323 		ret = PTR_ERR(msm_host->esc_clk);
324 		pr_err("%s: can't find dsi_esc clock. ret=%d\n",
325 			__func__, ret);
326 		msm_host->esc_clk = NULL;
327 		goto exit;
328 	}
329 
330 	if (cfg_hnd->ops->clk_init_ver)
331 		ret = cfg_hnd->ops->clk_init_ver(msm_host);
332 exit:
333 	return ret;
334 }
335 
336 int msm_dsi_runtime_suspend(struct device *dev)
337 {
338 	struct platform_device *pdev = to_platform_device(dev);
339 	struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
340 	struct mipi_dsi_host *host = msm_dsi->host;
341 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
342 
343 	if (!msm_host->cfg_hnd)
344 		return 0;
345 
346 	clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks);
347 
348 	return 0;
349 }
350 
351 int msm_dsi_runtime_resume(struct device *dev)
352 {
353 	struct platform_device *pdev = to_platform_device(dev);
354 	struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
355 	struct mipi_dsi_host *host = msm_dsi->host;
356 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
357 
358 	if (!msm_host->cfg_hnd)
359 		return 0;
360 
361 	return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks);
362 }
363 
364 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
365 {
366 	int ret;
367 
368 	DBG("Set clk rates: pclk=%d, byteclk=%lu",
369 		msm_host->mode->clock, msm_host->byte_clk_rate);
370 
371 	ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
372 				  msm_host->byte_clk_rate);
373 	if (ret) {
374 		pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
375 		return ret;
376 	}
377 
378 	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
379 	if (ret) {
380 		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
381 		return ret;
382 	}
383 
384 	if (msm_host->byte_intf_clk) {
385 		ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate);
386 		if (ret) {
387 			pr_err("%s: Failed to set rate byte intf clk, %d\n",
388 			       __func__, ret);
389 			return ret;
390 		}
391 	}
392 
393 	return 0;
394 }
395 
396 
397 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
398 {
399 	int ret;
400 
401 	ret = clk_prepare_enable(msm_host->esc_clk);
402 	if (ret) {
403 		pr_err("%s: Failed to enable dsi esc clk\n", __func__);
404 		goto error;
405 	}
406 
407 	ret = clk_prepare_enable(msm_host->byte_clk);
408 	if (ret) {
409 		pr_err("%s: Failed to enable dsi byte clk\n", __func__);
410 		goto byte_clk_err;
411 	}
412 
413 	ret = clk_prepare_enable(msm_host->pixel_clk);
414 	if (ret) {
415 		pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
416 		goto pixel_clk_err;
417 	}
418 
419 	ret = clk_prepare_enable(msm_host->byte_intf_clk);
420 	if (ret) {
421 		pr_err("%s: Failed to enable byte intf clk\n",
422 			   __func__);
423 		goto byte_intf_clk_err;
424 	}
425 
426 	return 0;
427 
428 byte_intf_clk_err:
429 	clk_disable_unprepare(msm_host->pixel_clk);
430 pixel_clk_err:
431 	clk_disable_unprepare(msm_host->byte_clk);
432 byte_clk_err:
433 	clk_disable_unprepare(msm_host->esc_clk);
434 error:
435 	return ret;
436 }
437 
438 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
439 {
440 	int ret;
441 
442 	DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
443 		msm_host->mode->clock, msm_host->byte_clk_rate,
444 		msm_host->esc_clk_rate, msm_host->src_clk_rate);
445 
446 	ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
447 	if (ret) {
448 		pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
449 		return ret;
450 	}
451 
452 	ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
453 	if (ret) {
454 		pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
455 		return ret;
456 	}
457 
458 	ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
459 	if (ret) {
460 		pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
461 		return ret;
462 	}
463 
464 	ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
465 	if (ret) {
466 		pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
467 		return ret;
468 	}
469 
470 	return 0;
471 }
472 
473 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
474 {
475 	int ret;
476 
477 	ret = clk_prepare_enable(msm_host->byte_clk);
478 	if (ret) {
479 		pr_err("%s: Failed to enable dsi byte clk\n", __func__);
480 		goto error;
481 	}
482 
483 	ret = clk_prepare_enable(msm_host->esc_clk);
484 	if (ret) {
485 		pr_err("%s: Failed to enable dsi esc clk\n", __func__);
486 		goto esc_clk_err;
487 	}
488 
489 	ret = clk_prepare_enable(msm_host->src_clk);
490 	if (ret) {
491 		pr_err("%s: Failed to enable dsi src clk\n", __func__);
492 		goto src_clk_err;
493 	}
494 
495 	ret = clk_prepare_enable(msm_host->pixel_clk);
496 	if (ret) {
497 		pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
498 		goto pixel_clk_err;
499 	}
500 
501 	return 0;
502 
503 pixel_clk_err:
504 	clk_disable_unprepare(msm_host->src_clk);
505 src_clk_err:
506 	clk_disable_unprepare(msm_host->esc_clk);
507 esc_clk_err:
508 	clk_disable_unprepare(msm_host->byte_clk);
509 error:
510 	return ret;
511 }
512 
513 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
514 {
515 	/* Drop the performance state vote */
516 	dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
517 	clk_disable_unprepare(msm_host->esc_clk);
518 	clk_disable_unprepare(msm_host->pixel_clk);
519 	clk_disable_unprepare(msm_host->byte_intf_clk);
520 	clk_disable_unprepare(msm_host->byte_clk);
521 }
522 
523 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
524 {
525 	clk_disable_unprepare(msm_host->pixel_clk);
526 	clk_disable_unprepare(msm_host->src_clk);
527 	clk_disable_unprepare(msm_host->esc_clk);
528 	clk_disable_unprepare(msm_host->byte_clk);
529 }
530 
531 static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode,
532 		const struct drm_dsc_config *dsc)
533 {
534 	int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc),
535 			dsc->bits_per_component * 3);
536 
537 	int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay;
538 
539 	return new_htotal * mode->vtotal * drm_mode_vrefresh(mode);
540 }
541 
542 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
543 		const struct drm_dsc_config *dsc, bool is_bonded_dsi)
544 {
545 	unsigned long pclk_rate;
546 
547 	pclk_rate = mode->clock * 1000;
548 
549 	if (dsc)
550 		pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc);
551 
552 	/*
553 	 * For bonded DSI mode, the current DRM mode has the complete width of the
554 	 * panel. Since, the complete panel is driven by two DSI controllers,
555 	 * the clock rates have to be split between the two dsi controllers.
556 	 * Adjust the byte and pixel clock rates for each dsi host accordingly.
557 	 */
558 	if (is_bonded_dsi)
559 		pclk_rate /= 2;
560 
561 	return pclk_rate;
562 }
563 
564 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi,
565 				    const struct drm_display_mode *mode)
566 {
567 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
568 	u8 lanes = msm_host->lanes;
569 	u32 bpp = dsi_get_bpp(msm_host->format);
570 	unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi);
571 	unsigned long pclk_bpp;
572 
573 	if (lanes == 0) {
574 		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
575 		lanes = 1;
576 	}
577 
578 	/* CPHY "byte_clk" is in units of 16 bits */
579 	if (msm_host->cphy_mode)
580 		pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes);
581 	else
582 		pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes);
583 
584 	return pclk_bpp;
585 }
586 
587 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
588 {
589 	msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi);
590 	msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi,
591 							msm_host->mode);
592 
593 	DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate,
594 				msm_host->byte_clk_rate);
595 
596 }
597 
598 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
599 {
600 	if (!msm_host->mode) {
601 		pr_err("%s: mode not set\n", __func__);
602 		return -EINVAL;
603 	}
604 
605 	dsi_calc_pclk(msm_host, is_bonded_dsi);
606 	msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
607 	return 0;
608 }
609 
610 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
611 {
612 	u32 bpp = dsi_get_bpp(msm_host->format);
613 	unsigned int esc_mhz, esc_div;
614 	unsigned long byte_mhz;
615 
616 	dsi_calc_pclk(msm_host, is_bonded_dsi);
617 
618 	msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8);
619 
620 	/*
621 	 * esc clock is byte clock followed by a 4 bit divider,
622 	 * we need to find an escape clock frequency within the
623 	 * mipi DSI spec range within the maximum divider limit
624 	 * We iterate here between an escape clock frequencey
625 	 * between 20 Mhz to 5 Mhz and pick up the first one
626 	 * that can be supported by our divider
627 	 */
628 
629 	byte_mhz = msm_host->byte_clk_rate / 1000000;
630 
631 	for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
632 		esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
633 
634 		/*
635 		 * TODO: Ideally, we shouldn't know what sort of divider
636 		 * is available in mmss_cc, we're just assuming that
637 		 * it'll always be a 4 bit divider. Need to come up with
638 		 * a better way here.
639 		 */
640 		if (esc_div >= 1 && esc_div <= 16)
641 			break;
642 	}
643 
644 	if (esc_mhz < 5)
645 		return -EINVAL;
646 
647 	msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
648 
649 	DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate,
650 		msm_host->src_clk_rate);
651 
652 	return 0;
653 }
654 
655 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
656 {
657 	u32 intr;
658 	unsigned long flags;
659 
660 	spin_lock_irqsave(&msm_host->intr_lock, flags);
661 	intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
662 
663 	if (enable)
664 		intr |= mask;
665 	else
666 		intr &= ~mask;
667 
668 	DBG("intr=%x enable=%d", intr, enable);
669 
670 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
671 	spin_unlock_irqrestore(&msm_host->intr_lock, flags);
672 }
673 
674 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
675 {
676 	if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
677 		return BURST_MODE;
678 	else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
679 		return NON_BURST_SYNCH_PULSE;
680 
681 	return NON_BURST_SYNCH_EVENT;
682 }
683 
684 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
685 				const enum mipi_dsi_pixel_format mipi_fmt)
686 {
687 	switch (mipi_fmt) {
688 	case MIPI_DSI_FMT_RGB888:	return VID_DST_FORMAT_RGB888;
689 	case MIPI_DSI_FMT_RGB666:	return VID_DST_FORMAT_RGB666_LOOSE;
690 	case MIPI_DSI_FMT_RGB666_PACKED:	return VID_DST_FORMAT_RGB666;
691 	case MIPI_DSI_FMT_RGB565:	return VID_DST_FORMAT_RGB565;
692 	default:			return VID_DST_FORMAT_RGB888;
693 	}
694 }
695 
696 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
697 				const enum mipi_dsi_pixel_format mipi_fmt)
698 {
699 	switch (mipi_fmt) {
700 	case MIPI_DSI_FMT_RGB888:	return CMD_DST_FORMAT_RGB888;
701 	case MIPI_DSI_FMT_RGB666_PACKED:
702 	case MIPI_DSI_FMT_RGB666:	return CMD_DST_FORMAT_RGB666;
703 	case MIPI_DSI_FMT_RGB565:	return CMD_DST_FORMAT_RGB565;
704 	default:			return CMD_DST_FORMAT_RGB888;
705 	}
706 }
707 
708 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host)
709 {
710 	dsi_write(msm_host, REG_DSI_CTRL, 0);
711 }
712 
713 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
714 			struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy)
715 {
716 	u32 flags = msm_host->mode_flags;
717 	enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
718 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
719 	u32 data = 0, lane_ctrl = 0;
720 
721 	if (flags & MIPI_DSI_MODE_VIDEO) {
722 		if (flags & MIPI_DSI_MODE_VIDEO_HSE)
723 			data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
724 		if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
725 			data |= DSI_VID_CFG0_HFP_POWER_STOP;
726 		if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
727 			data |= DSI_VID_CFG0_HBP_POWER_STOP;
728 		if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
729 			data |= DSI_VID_CFG0_HSA_POWER_STOP;
730 		/* Always set low power stop mode for BLLP
731 		 * to let command engine send packets
732 		 */
733 		data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
734 			DSI_VID_CFG0_BLLP_POWER_STOP;
735 		data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
736 		data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
737 		data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
738 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);
739 
740 		/* Do not swap RGB colors */
741 		data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
742 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
743 	} else {
744 		/* Do not swap RGB colors */
745 		data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
746 		data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
747 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
748 
749 		data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
750 			DSI_CMD_CFG1_WR_MEM_CONTINUE(
751 					MIPI_DCS_WRITE_MEMORY_CONTINUE);
752 		/* Always insert DCS command */
753 		data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
754 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
755 
756 		if (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G &&
757 		    msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) {
758 			data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2);
759 			data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE;
760 			dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data);
761 		}
762 	}
763 
764 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
765 			DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
766 			DSI_CMD_DMA_CTRL_LOW_POWER);
767 
768 	data = 0;
769 	/* Always assume dedicated TE pin */
770 	data |= DSI_TRIG_CTRL_TE;
771 	data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
772 	data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
773 	data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
774 	if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
775 		(cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
776 		data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
777 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
778 
779 	data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
780 		DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
781 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
782 
783 	if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
784 	    (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
785 	    phy_shared_timings->clk_pre_inc_by_2)
786 		dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
787 			  DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
788 
789 	data = 0;
790 	if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
791 		data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
792 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
793 
794 	/* allow only ack-err-status to generate interrupt */
795 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
796 
797 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
798 
799 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
800 
801 	data = DSI_CTRL_CLK_EN;
802 
803 	DBG("lane number=%d", msm_host->lanes);
804 	data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
805 
806 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
807 		  DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
808 
809 	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
810 		lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
811 
812 		if (msm_dsi_phy_set_continuous_clock(phy, true))
813 			lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY;
814 
815 		dsi_write(msm_host, REG_DSI_LANE_CTRL,
816 			lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
817 	}
818 
819 	data |= DSI_CTRL_ENABLE;
820 
821 	dsi_write(msm_host, REG_DSI_CTRL, data);
822 
823 	if (msm_host->cphy_mode)
824 		dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
825 }
826 
827 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
828 {
829 	struct drm_dsc_config *dsc = msm_host->dsc;
830 	u32 reg, reg_ctrl, reg_ctrl2;
831 	u32 slice_per_intf, total_bytes_per_intf;
832 	u32 pkt_per_line;
833 	u32 eol_byte_num;
834 
835 	/* first calculate dsc parameters and then program
836 	 * compress mode registers
837 	 */
838 	slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
839 
840 	total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
841 
842 	eol_byte_num = total_bytes_per_intf % 3;
843 
844 	/*
845 	 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt.
846 	 *
847 	 * Since the current driver only supports slice_per_pkt = 1,
848 	 * pkt_per_line will be equal to slice per intf for now.
849 	 */
850 	pkt_per_line = slice_per_intf;
851 
852 	if (is_cmd_mode) /* packet data type */
853 		reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
854 	else
855 		reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM);
856 
857 	/* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
858 	 * registers have similar offsets, so for below common code use
859 	 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits
860 	 */
861 	reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
862 	reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
863 	reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN;
864 
865 	if (is_cmd_mode) {
866 		reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
867 		reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
868 
869 		reg_ctrl &= ~0xffff;
870 		reg_ctrl |= reg;
871 
872 		reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
873 		reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);
874 
875 		dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
876 		dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
877 	} else {
878 		dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
879 	}
880 }
881 
882 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
883 {
884 	struct drm_display_mode *mode = msm_host->mode;
885 	u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
886 	u32 h_total = mode->htotal;
887 	u32 v_total = mode->vtotal;
888 	u32 hs_end = mode->hsync_end - mode->hsync_start;
889 	u32 vs_end = mode->vsync_end - mode->vsync_start;
890 	u32 ha_start = h_total - mode->hsync_start;
891 	u32 ha_end = ha_start + mode->hdisplay;
892 	u32 va_start = v_total - mode->vsync_start;
893 	u32 va_end = va_start + mode->vdisplay;
894 	u32 hdisplay = mode->hdisplay;
895 	u32 wc;
896 	int ret;
897 
898 	DBG("");
899 
900 	/*
901 	 * For bonded DSI mode, the current DRM mode has
902 	 * the complete width of the panel. Since, the complete
903 	 * panel is driven by two DSI controllers, the horizontal
904 	 * timings have to be split between the two dsi controllers.
905 	 * Adjust the DSI host timing values accordingly.
906 	 */
907 	if (is_bonded_dsi) {
908 		h_total /= 2;
909 		hs_end /= 2;
910 		ha_start /= 2;
911 		ha_end /= 2;
912 		hdisplay /= 2;
913 	}
914 
915 	if (msm_host->dsc) {
916 		struct drm_dsc_config *dsc = msm_host->dsc;
917 
918 		/* update dsc params with timing params */
919 		if (!dsc || !mode->hdisplay || !mode->vdisplay) {
920 			pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n",
921 			       mode->hdisplay, mode->vdisplay);
922 			return;
923 		}
924 
925 		dsc->pic_width = mode->hdisplay;
926 		dsc->pic_height = mode->vdisplay;
927 		DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
928 
929 		/* we do the calculations for dsc parameters here so that
930 		 * panel can use these parameters
931 		 */
932 		ret = dsi_populate_dsc_params(msm_host, dsc);
933 		if (ret)
934 			return;
935 
936 		/* Divide the display by 3 but keep back/font porch and
937 		 * pulse width same
938 		 */
939 		h_total -= hdisplay;
940 		hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
941 		h_total += hdisplay;
942 		ha_end = ha_start + hdisplay;
943 	}
944 
945 	if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
946 		if (msm_host->dsc)
947 			dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
948 
949 		dsi_write(msm_host, REG_DSI_ACTIVE_H,
950 			DSI_ACTIVE_H_START(ha_start) |
951 			DSI_ACTIVE_H_END(ha_end));
952 		dsi_write(msm_host, REG_DSI_ACTIVE_V,
953 			DSI_ACTIVE_V_START(va_start) |
954 			DSI_ACTIVE_V_END(va_end));
955 		dsi_write(msm_host, REG_DSI_TOTAL,
956 			DSI_TOTAL_H_TOTAL(h_total - 1) |
957 			DSI_TOTAL_V_TOTAL(v_total - 1));
958 
959 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
960 			DSI_ACTIVE_HSYNC_START(hs_start) |
961 			DSI_ACTIVE_HSYNC_END(hs_end));
962 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
963 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
964 			DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
965 			DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
966 	} else {		/* command mode */
967 		if (msm_host->dsc)
968 			dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
969 
970 		/* image data and 1 byte write_memory_start cmd */
971 		if (!msm_host->dsc)
972 			wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
973 		else
974 			/*
975 			 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1.
976 			 * Currently, the driver only supports default value of slice_per_pkt = 1
977 			 *
978 			 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info
979 			 *       and adjust DSC math to account for slice_per_pkt.
980 			 */
981 			wc = msm_host->dsc->slice_chunk_size + 1;
982 
983 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
984 			DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
985 			DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
986 					msm_host->channel) |
987 			DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
988 					MIPI_DSI_DCS_LONG_WRITE));
989 
990 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
991 			DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
992 			DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
993 	}
994 }
995 
996 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
997 {
998 	u32 ctrl;
999 
1000 	ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1001 
1002 	if (ctrl & DSI_CTRL_ENABLE) {
1003 		dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);
1004 		/*
1005 		 * dsi controller need to be disabled before
1006 		 * clocks turned on
1007 		 */
1008 		wmb();
1009 	}
1010 
1011 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1012 	wmb(); /* clocks need to be enabled before reset */
1013 
1014 	/* dsi controller can only be reset while clocks are running */
1015 	dsi_write(msm_host, REG_DSI_RESET, 1);
1016 	msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1017 	dsi_write(msm_host, REG_DSI_RESET, 0);
1018 	wmb(); /* controller out of reset */
1019 
1020 	if (ctrl & DSI_CTRL_ENABLE) {
1021 		dsi_write(msm_host, REG_DSI_CTRL, ctrl);
1022 		wmb();	/* make sure dsi controller enabled again */
1023 	}
1024 }
1025 
1026 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1027 					bool video_mode, bool enable)
1028 {
1029 	u32 dsi_ctrl;
1030 
1031 	dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1032 
1033 	if (!enable) {
1034 		dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1035 				DSI_CTRL_CMD_MODE_EN);
1036 		dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1037 					DSI_IRQ_MASK_VIDEO_DONE, 0);
1038 	} else {
1039 		if (video_mode) {
1040 			dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1041 		} else {		/* command mode */
1042 			dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1043 			dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1044 		}
1045 		dsi_ctrl |= DSI_CTRL_ENABLE;
1046 	}
1047 
1048 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1049 }
1050 
1051 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1052 {
1053 	u32 data;
1054 
1055 	data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1056 
1057 	if (mode == 0)
1058 		data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1059 	else
1060 		data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1061 
1062 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1063 }
1064 
1065 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1066 {
1067 	u32 ret = 0;
1068 	struct device *dev = &msm_host->pdev->dev;
1069 
1070 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1071 
1072 	reinit_completion(&msm_host->video_comp);
1073 
1074 	ret = wait_for_completion_timeout(&msm_host->video_comp,
1075 			msecs_to_jiffies(70));
1076 
1077 	if (ret == 0)
1078 		DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1079 
1080 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1081 }
1082 
1083 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1084 {
1085 	if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1086 		return;
1087 
1088 	if (msm_host->power_on && msm_host->enabled) {
1089 		dsi_wait4video_done(msm_host);
1090 		/* delay 4 ms to skip BLLP */
1091 		usleep_range(2000, 4000);
1092 	}
1093 }
1094 
1095 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1096 {
1097 	struct drm_device *dev = msm_host->dev;
1098 	struct msm_drm_private *priv = dev->dev_private;
1099 	uint64_t iova;
1100 	u8 *data;
1101 
1102 	data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1103 					priv->kms->aspace,
1104 					&msm_host->tx_gem_obj, &iova);
1105 
1106 	if (IS_ERR(data)) {
1107 		msm_host->tx_gem_obj = NULL;
1108 		return PTR_ERR(data);
1109 	}
1110 
1111 	msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1112 
1113 	msm_host->tx_size = msm_host->tx_gem_obj->size;
1114 
1115 	return 0;
1116 }
1117 
1118 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1119 {
1120 	struct drm_device *dev = msm_host->dev;
1121 
1122 	msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1123 					&msm_host->tx_buf_paddr, GFP_KERNEL);
1124 	if (!msm_host->tx_buf)
1125 		return -ENOMEM;
1126 
1127 	msm_host->tx_size = size;
1128 
1129 	return 0;
1130 }
1131 
1132 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1133 {
1134 	struct drm_device *dev = msm_host->dev;
1135 	struct msm_drm_private *priv;
1136 
1137 	/*
1138 	 * This is possible if we're tearing down before we've had a chance to
1139 	 * fully initialize. A very real possibility if our probe is deferred,
1140 	 * in which case we'll hit msm_dsi_host_destroy() without having run
1141 	 * through the dsi_tx_buf_alloc().
1142 	 */
1143 	if (!dev)
1144 		return;
1145 
1146 	priv = dev->dev_private;
1147 	if (msm_host->tx_gem_obj) {
1148 		msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1149 		drm_gem_object_put(msm_host->tx_gem_obj);
1150 		msm_host->tx_gem_obj = NULL;
1151 	}
1152 
1153 	if (msm_host->tx_buf)
1154 		dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1155 			msm_host->tx_buf_paddr);
1156 }
1157 
1158 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1159 {
1160 	return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1161 }
1162 
1163 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1164 {
1165 	return msm_host->tx_buf;
1166 }
1167 
1168 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1169 {
1170 	msm_gem_put_vaddr(msm_host->tx_gem_obj);
1171 }
1172 
1173 /*
1174  * prepare cmd buffer to be txed
1175  */
1176 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1177 			   const struct mipi_dsi_msg *msg)
1178 {
1179 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1180 	struct mipi_dsi_packet packet;
1181 	int len;
1182 	int ret;
1183 	u8 *data;
1184 
1185 	ret = mipi_dsi_create_packet(&packet, msg);
1186 	if (ret) {
1187 		pr_err("%s: create packet failed, %d\n", __func__, ret);
1188 		return ret;
1189 	}
1190 	len = (packet.size + 3) & (~0x3);
1191 
1192 	if (len > msm_host->tx_size) {
1193 		pr_err("%s: packet size is too big\n", __func__);
1194 		return -EINVAL;
1195 	}
1196 
1197 	data = cfg_hnd->ops->tx_buf_get(msm_host);
1198 	if (IS_ERR(data)) {
1199 		ret = PTR_ERR(data);
1200 		pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1201 		return ret;
1202 	}
1203 
1204 	/* MSM specific command format in memory */
1205 	data[0] = packet.header[1];
1206 	data[1] = packet.header[2];
1207 	data[2] = packet.header[0];
1208 	data[3] = BIT(7); /* Last packet */
1209 	if (mipi_dsi_packet_format_is_long(msg->type))
1210 		data[3] |= BIT(6);
1211 	if (msg->rx_buf && msg->rx_len)
1212 		data[3] |= BIT(5);
1213 
1214 	/* Long packet */
1215 	if (packet.payload && packet.payload_length)
1216 		memcpy(data + 4, packet.payload, packet.payload_length);
1217 
1218 	/* Append 0xff to the end */
1219 	if (packet.size < len)
1220 		memset(data + packet.size, 0xff, len - packet.size);
1221 
1222 	if (cfg_hnd->ops->tx_buf_put)
1223 		cfg_hnd->ops->tx_buf_put(msm_host);
1224 
1225 	return len;
1226 }
1227 
1228 /*
1229  * dsi_short_read1_resp: 1 parameter
1230  */
1231 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1232 {
1233 	u8 *data = msg->rx_buf;
1234 	if (data && (msg->rx_len >= 1)) {
1235 		*data = buf[1]; /* strip out dcs type */
1236 		return 1;
1237 	} else {
1238 		pr_err("%s: read data does not match with rx_buf len %zu\n",
1239 			__func__, msg->rx_len);
1240 		return -EINVAL;
1241 	}
1242 }
1243 
1244 /*
1245  * dsi_short_read2_resp: 2 parameter
1246  */
1247 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1248 {
1249 	u8 *data = msg->rx_buf;
1250 	if (data && (msg->rx_len >= 2)) {
1251 		data[0] = buf[1]; /* strip out dcs type */
1252 		data[1] = buf[2];
1253 		return 2;
1254 	} else {
1255 		pr_err("%s: read data does not match with rx_buf len %zu\n",
1256 			__func__, msg->rx_len);
1257 		return -EINVAL;
1258 	}
1259 }
1260 
1261 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1262 {
1263 	/* strip out 4 byte dcs header */
1264 	if (msg->rx_buf && msg->rx_len)
1265 		memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1266 
1267 	return msg->rx_len;
1268 }
1269 
1270 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1271 {
1272 	struct drm_device *dev = msm_host->dev;
1273 	struct msm_drm_private *priv = dev->dev_private;
1274 
1275 	if (!dma_base)
1276 		return -EINVAL;
1277 
1278 	return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1279 				priv->kms->aspace, dma_base);
1280 }
1281 
1282 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1283 {
1284 	if (!dma_base)
1285 		return -EINVAL;
1286 
1287 	*dma_base = msm_host->tx_buf_paddr;
1288 	return 0;
1289 }
1290 
1291 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1292 {
1293 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1294 	int ret;
1295 	uint64_t dma_base;
1296 	bool triggered;
1297 
1298 	ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1299 	if (ret) {
1300 		pr_err("%s: failed to get iova: %d\n", __func__, ret);
1301 		return ret;
1302 	}
1303 
1304 	reinit_completion(&msm_host->dma_comp);
1305 
1306 	dsi_wait4video_eng_busy(msm_host);
1307 
1308 	triggered = msm_dsi_manager_cmd_xfer_trigger(
1309 						msm_host->id, dma_base, len);
1310 	if (triggered) {
1311 		ret = wait_for_completion_timeout(&msm_host->dma_comp,
1312 					msecs_to_jiffies(200));
1313 		DBG("ret=%d", ret);
1314 		if (ret == 0)
1315 			ret = -ETIMEDOUT;
1316 		else
1317 			ret = len;
1318 	} else
1319 		ret = len;
1320 
1321 	return ret;
1322 }
1323 
1324 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1325 			u8 *buf, int rx_byte, int pkt_size)
1326 {
1327 	u32 *temp, data;
1328 	int i, j = 0, cnt;
1329 	u32 read_cnt;
1330 	u8 reg[16];
1331 	int repeated_bytes = 0;
1332 	int buf_offset = buf - msm_host->rx_buf;
1333 
1334 	temp = (u32 *)reg;
1335 	cnt = (rx_byte + 3) >> 2;
1336 	if (cnt > 4)
1337 		cnt = 4; /* 4 x 32 bits registers only */
1338 
1339 	if (rx_byte == 4)
1340 		read_cnt = 4;
1341 	else
1342 		read_cnt = pkt_size + 6;
1343 
1344 	/*
1345 	 * In case of multiple reads from the panel, after the first read, there
1346 	 * is possibility that there are some bytes in the payload repeating in
1347 	 * the RDBK_DATA registers. Since we read all the parameters from the
1348 	 * panel right from the first byte for every pass. We need to skip the
1349 	 * repeating bytes and then append the new parameters to the rx buffer.
1350 	 */
1351 	if (read_cnt > 16) {
1352 		int bytes_shifted;
1353 		/* Any data more than 16 bytes will be shifted out.
1354 		 * The temp read buffer should already contain these bytes.
1355 		 * The remaining bytes in read buffer are the repeated bytes.
1356 		 */
1357 		bytes_shifted = read_cnt - 16;
1358 		repeated_bytes = buf_offset - bytes_shifted;
1359 	}
1360 
1361 	for (i = cnt - 1; i >= 0; i--) {
1362 		data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1363 		*temp++ = ntohl(data); /* to host byte order */
1364 		DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1365 	}
1366 
1367 	for (i = repeated_bytes; i < 16; i++)
1368 		buf[j++] = reg[i];
1369 
1370 	return j;
1371 }
1372 
1373 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1374 				const struct mipi_dsi_msg *msg)
1375 {
1376 	int len, ret;
1377 	int bllp_len = msm_host->mode->hdisplay *
1378 			dsi_get_bpp(msm_host->format) / 8;
1379 
1380 	len = dsi_cmd_dma_add(msm_host, msg);
1381 	if (len < 0) {
1382 		pr_err("%s: failed to add cmd type = 0x%x\n",
1383 			__func__,  msg->type);
1384 		return len;
1385 	}
1386 
1387 	/* for video mode, do not send cmds more than
1388 	* one pixel line, since it only transmit it
1389 	* during BLLP.
1390 	*/
1391 	/* TODO: if the command is sent in LP mode, the bit rate is only
1392 	 * half of esc clk rate. In this case, if the video is already
1393 	 * actively streaming, we need to check more carefully if the
1394 	 * command can be fit into one BLLP.
1395 	 */
1396 	if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1397 		pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1398 			__func__, len);
1399 		return -EINVAL;
1400 	}
1401 
1402 	ret = dsi_cmd_dma_tx(msm_host, len);
1403 	if (ret < 0) {
1404 		pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
1405 			__func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
1406 		return ret;
1407 	} else if (ret < len) {
1408 		pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
1409 			__func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
1410 		return -EIO;
1411 	}
1412 
1413 	return len;
1414 }
1415 
1416 static void dsi_err_worker(struct work_struct *work)
1417 {
1418 	struct msm_dsi_host *msm_host =
1419 		container_of(work, struct msm_dsi_host, err_work);
1420 	u32 status = msm_host->err_work_state;
1421 
1422 	pr_err_ratelimited("%s: status=%x\n", __func__, status);
1423 	if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1424 		dsi_sw_reset(msm_host);
1425 
1426 	/* It is safe to clear here because error irq is disabled. */
1427 	msm_host->err_work_state = 0;
1428 
1429 	/* enable dsi error interrupt */
1430 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1431 }
1432 
1433 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1434 {
1435 	u32 status;
1436 
1437 	status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1438 
1439 	if (status) {
1440 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1441 		/* Writing of an extra 0 needed to clear error bits */
1442 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1443 		msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1444 	}
1445 }
1446 
1447 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1448 {
1449 	u32 status;
1450 
1451 	status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1452 
1453 	if (status) {
1454 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1455 		msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1456 	}
1457 }
1458 
1459 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1460 {
1461 	u32 status;
1462 
1463 	status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1464 
1465 	if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1466 			DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1467 			DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1468 			DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1469 			DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1470 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1471 		msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1472 	}
1473 }
1474 
1475 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1476 {
1477 	u32 status;
1478 
1479 	status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1480 
1481 	/* fifo underflow, overflow */
1482 	if (status) {
1483 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1484 		msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1485 		if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1486 			msm_host->err_work_state |=
1487 					DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1488 	}
1489 }
1490 
1491 static void dsi_status(struct msm_dsi_host *msm_host)
1492 {
1493 	u32 status;
1494 
1495 	status = dsi_read(msm_host, REG_DSI_STATUS0);
1496 
1497 	if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1498 		dsi_write(msm_host, REG_DSI_STATUS0, status);
1499 		msm_host->err_work_state |=
1500 			DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1501 	}
1502 }
1503 
1504 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1505 {
1506 	u32 status;
1507 
1508 	status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1509 
1510 	if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1511 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1512 		msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1513 	}
1514 }
1515 
1516 static void dsi_error(struct msm_dsi_host *msm_host)
1517 {
1518 	/* disable dsi error interrupt */
1519 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1520 
1521 	dsi_clk_status(msm_host);
1522 	dsi_fifo_status(msm_host);
1523 	dsi_ack_err_status(msm_host);
1524 	dsi_timeout_status(msm_host);
1525 	dsi_status(msm_host);
1526 	dsi_dln0_phy_err(msm_host);
1527 
1528 	queue_work(msm_host->workqueue, &msm_host->err_work);
1529 }
1530 
1531 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1532 {
1533 	struct msm_dsi_host *msm_host = ptr;
1534 	u32 isr;
1535 	unsigned long flags;
1536 
1537 	if (!msm_host->ctrl_base)
1538 		return IRQ_HANDLED;
1539 
1540 	spin_lock_irqsave(&msm_host->intr_lock, flags);
1541 	isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1542 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1543 	spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1544 
1545 	DBG("isr=0x%x, id=%d", isr, msm_host->id);
1546 
1547 	if (isr & DSI_IRQ_ERROR)
1548 		dsi_error(msm_host);
1549 
1550 	if (isr & DSI_IRQ_VIDEO_DONE)
1551 		complete(&msm_host->video_comp);
1552 
1553 	if (isr & DSI_IRQ_CMD_DMA_DONE)
1554 		complete(&msm_host->dma_comp);
1555 
1556 	return IRQ_HANDLED;
1557 }
1558 
1559 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1560 			struct device *panel_device)
1561 {
1562 	msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1563 							 "disp-enable",
1564 							 GPIOD_OUT_LOW);
1565 	if (IS_ERR(msm_host->disp_en_gpio)) {
1566 		DBG("cannot get disp-enable-gpios %ld",
1567 				PTR_ERR(msm_host->disp_en_gpio));
1568 		return PTR_ERR(msm_host->disp_en_gpio);
1569 	}
1570 
1571 	msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1572 								GPIOD_IN);
1573 	if (IS_ERR(msm_host->te_gpio)) {
1574 		DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1575 		return PTR_ERR(msm_host->te_gpio);
1576 	}
1577 
1578 	return 0;
1579 }
1580 
1581 static int dsi_host_attach(struct mipi_dsi_host *host,
1582 					struct mipi_dsi_device *dsi)
1583 {
1584 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1585 	int ret;
1586 
1587 	if (dsi->lanes > msm_host->num_data_lanes)
1588 		return -EINVAL;
1589 
1590 	msm_host->channel = dsi->channel;
1591 	msm_host->lanes = dsi->lanes;
1592 	msm_host->format = dsi->format;
1593 	msm_host->mode_flags = dsi->mode_flags;
1594 	if (dsi->dsc)
1595 		msm_host->dsc = dsi->dsc;
1596 
1597 	/* Some gpios defined in panel DT need to be controlled by host */
1598 	ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1599 	if (ret)
1600 		return ret;
1601 
1602 	ret = dsi_dev_attach(msm_host->pdev);
1603 	if (ret)
1604 		return ret;
1605 
1606 	DBG("id=%d", msm_host->id);
1607 
1608 	return 0;
1609 }
1610 
1611 static int dsi_host_detach(struct mipi_dsi_host *host,
1612 					struct mipi_dsi_device *dsi)
1613 {
1614 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1615 
1616 	dsi_dev_detach(msm_host->pdev);
1617 
1618 	DBG("id=%d", msm_host->id);
1619 
1620 	return 0;
1621 }
1622 
1623 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1624 					const struct mipi_dsi_msg *msg)
1625 {
1626 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1627 	int ret;
1628 
1629 	if (!msg || !msm_host->power_on)
1630 		return -EINVAL;
1631 
1632 	mutex_lock(&msm_host->cmd_mutex);
1633 	ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1634 	mutex_unlock(&msm_host->cmd_mutex);
1635 
1636 	return ret;
1637 }
1638 
1639 static const struct mipi_dsi_host_ops dsi_host_ops = {
1640 	.attach = dsi_host_attach,
1641 	.detach = dsi_host_detach,
1642 	.transfer = dsi_host_transfer,
1643 };
1644 
1645 /*
1646  * List of supported physical to logical lane mappings.
1647  * For example, the 2nd entry represents the following mapping:
1648  *
1649  * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1650  */
1651 static const int supported_data_lane_swaps[][4] = {
1652 	{ 0, 1, 2, 3 },
1653 	{ 3, 0, 1, 2 },
1654 	{ 2, 3, 0, 1 },
1655 	{ 1, 2, 3, 0 },
1656 	{ 0, 3, 2, 1 },
1657 	{ 1, 0, 3, 2 },
1658 	{ 2, 1, 0, 3 },
1659 	{ 3, 2, 1, 0 },
1660 };
1661 
1662 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1663 				    struct device_node *ep)
1664 {
1665 	struct device *dev = &msm_host->pdev->dev;
1666 	struct property *prop;
1667 	u32 lane_map[4];
1668 	int ret, i, len, num_lanes;
1669 
1670 	prop = of_find_property(ep, "data-lanes", &len);
1671 	if (!prop) {
1672 		DRM_DEV_DEBUG(dev,
1673 			"failed to find data lane mapping, using default\n");
1674 		/* Set the number of date lanes to 4 by default. */
1675 		msm_host->num_data_lanes = 4;
1676 		return 0;
1677 	}
1678 
1679 	num_lanes = drm_of_get_data_lanes_count(ep, 1, 4);
1680 	if (num_lanes < 0) {
1681 		DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1682 		return num_lanes;
1683 	}
1684 
1685 	msm_host->num_data_lanes = num_lanes;
1686 
1687 	ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1688 					 num_lanes);
1689 	if (ret) {
1690 		DRM_DEV_ERROR(dev, "failed to read lane data\n");
1691 		return ret;
1692 	}
1693 
1694 	/*
1695 	 * compare DT specified physical-logical lane mappings with the ones
1696 	 * supported by hardware
1697 	 */
1698 	for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1699 		const int *swap = supported_data_lane_swaps[i];
1700 		int j;
1701 
1702 		/*
1703 		 * the data-lanes array we get from DT has a logical->physical
1704 		 * mapping. The "data lane swap" register field represents
1705 		 * supported configurations in a physical->logical mapping.
1706 		 * Translate the DT mapping to what we understand and find a
1707 		 * configuration that works.
1708 		 */
1709 		for (j = 0; j < num_lanes; j++) {
1710 			if (lane_map[j] < 0 || lane_map[j] > 3)
1711 				DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1712 					lane_map[j]);
1713 
1714 			if (swap[lane_map[j]] != j)
1715 				break;
1716 		}
1717 
1718 		if (j == num_lanes) {
1719 			msm_host->dlane_swap = i;
1720 			return 0;
1721 		}
1722 	}
1723 
1724 	return -EINVAL;
1725 }
1726 
1727 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
1728 {
1729 	int ret;
1730 
1731 	if (dsc->bits_per_pixel & 0xf) {
1732 		DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
1733 		return -EINVAL;
1734 	}
1735 
1736 	if (dsc->bits_per_component != 8) {
1737 		DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n");
1738 		return -EOPNOTSUPP;
1739 	}
1740 
1741 	dsc->simple_422 = 0;
1742 	dsc->convert_rgb = 1;
1743 	dsc->vbr_enable = 0;
1744 
1745 	drm_dsc_set_const_params(dsc);
1746 	drm_dsc_set_rc_buf_thresh(dsc);
1747 
1748 	/* handle only bpp = bpc = 8, pre-SCR panels */
1749 	ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
1750 	if (ret) {
1751 		DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
1752 		return ret;
1753 	}
1754 
1755 	dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc);
1756 	dsc->line_buf_depth = dsc->bits_per_component + 1;
1757 
1758 	return drm_dsc_compute_rc_parameters(dsc);
1759 }
1760 
1761 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1762 {
1763 	struct device *dev = &msm_host->pdev->dev;
1764 	struct device_node *np = dev->of_node;
1765 	struct device_node *endpoint;
1766 	int ret = 0;
1767 
1768 	/*
1769 	 * Get the endpoint of the output port of the DSI host. In our case,
1770 	 * this is mapped to port number with reg = 1. Don't return an error if
1771 	 * the remote endpoint isn't defined. It's possible that there is
1772 	 * nothing connected to the dsi output.
1773 	 */
1774 	endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1775 	if (!endpoint) {
1776 		DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1777 		return 0;
1778 	}
1779 
1780 	ret = dsi_host_parse_lane_data(msm_host, endpoint);
1781 	if (ret) {
1782 		DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1783 			__func__, ret);
1784 		ret = -EINVAL;
1785 		goto err;
1786 	}
1787 
1788 	if (of_property_read_bool(np, "syscon-sfpb")) {
1789 		msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1790 					"syscon-sfpb");
1791 		if (IS_ERR(msm_host->sfpb)) {
1792 			DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1793 				__func__);
1794 			ret = PTR_ERR(msm_host->sfpb);
1795 		}
1796 	}
1797 
1798 err:
1799 	of_node_put(endpoint);
1800 
1801 	return ret;
1802 }
1803 
1804 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1805 {
1806 	struct platform_device *pdev = msm_host->pdev;
1807 	const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1808 	struct resource *res;
1809 	int i, j;
1810 
1811 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1812 	if (!res)
1813 		return -EINVAL;
1814 
1815 	for (i = 0; i < VARIANTS_MAX; i++)
1816 		for (j = 0; j < DSI_MAX; j++)
1817 			if (cfg->io_start[i][j] == res->start)
1818 				return j;
1819 
1820 	return -EINVAL;
1821 }
1822 
1823 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1824 {
1825 	struct msm_dsi_host *msm_host = NULL;
1826 	struct platform_device *pdev = msm_dsi->pdev;
1827 	const struct msm_dsi_config *cfg;
1828 	int ret;
1829 
1830 	msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1831 	if (!msm_host) {
1832 		return -ENOMEM;
1833 	}
1834 
1835 	msm_host->pdev = pdev;
1836 	msm_dsi->host = &msm_host->base;
1837 
1838 	ret = dsi_host_parse_dt(msm_host);
1839 	if (ret) {
1840 		pr_err("%s: failed to parse dt\n", __func__);
1841 		return ret;
1842 	}
1843 
1844 	msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size);
1845 	if (IS_ERR(msm_host->ctrl_base)) {
1846 		pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1847 		return PTR_ERR(msm_host->ctrl_base);
1848 	}
1849 
1850 	pm_runtime_enable(&pdev->dev);
1851 
1852 	msm_host->cfg_hnd = dsi_get_config(msm_host);
1853 	if (!msm_host->cfg_hnd) {
1854 		pr_err("%s: get config failed\n", __func__);
1855 		return -EINVAL;
1856 	}
1857 	cfg = msm_host->cfg_hnd->cfg;
1858 
1859 	msm_host->id = dsi_host_get_id(msm_host);
1860 	if (msm_host->id < 0) {
1861 		pr_err("%s: unable to identify DSI host index\n", __func__);
1862 		return msm_host->id;
1863 	}
1864 
1865 	/* fixup base address by io offset */
1866 	msm_host->ctrl_base += cfg->io_offset;
1867 
1868 	ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators,
1869 					    cfg->regulator_data,
1870 					    &msm_host->supplies);
1871 	if (ret)
1872 		return ret;
1873 
1874 	ret = dsi_clk_init(msm_host);
1875 	if (ret) {
1876 		pr_err("%s: unable to initialize dsi clks\n", __func__);
1877 		return ret;
1878 	}
1879 
1880 	msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1881 	if (!msm_host->rx_buf) {
1882 		pr_err("%s: alloc rx temp buf failed\n", __func__);
1883 		return -ENOMEM;
1884 	}
1885 
1886 	ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1887 	if (ret)
1888 		return ret;
1889 	/* OPP table is optional */
1890 	ret = devm_pm_opp_of_add_table(&pdev->dev);
1891 	if (ret && ret != -ENODEV) {
1892 		dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1893 		return ret;
1894 	}
1895 
1896 	msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1897 	if (msm_host->irq < 0) {
1898 		ret = msm_host->irq;
1899 		dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
1900 		return ret;
1901 	}
1902 
1903 	/* do not autoenable, will be enabled later */
1904 	ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq,
1905 			IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1906 			"dsi_isr", msm_host);
1907 	if (ret < 0) {
1908 		dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1909 				msm_host->irq, ret);
1910 		return ret;
1911 	}
1912 
1913 	init_completion(&msm_host->dma_comp);
1914 	init_completion(&msm_host->video_comp);
1915 	mutex_init(&msm_host->dev_mutex);
1916 	mutex_init(&msm_host->cmd_mutex);
1917 	spin_lock_init(&msm_host->intr_lock);
1918 
1919 	/* setup workqueue */
1920 	msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1921 	if (!msm_host->workqueue)
1922 		return -ENOMEM;
1923 
1924 	INIT_WORK(&msm_host->err_work, dsi_err_worker);
1925 
1926 	msm_dsi->id = msm_host->id;
1927 
1928 	DBG("Dsi Host %d initialized", msm_host->id);
1929 	return 0;
1930 }
1931 
1932 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1933 {
1934 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1935 
1936 	DBG("");
1937 	dsi_tx_buf_free(msm_host);
1938 	if (msm_host->workqueue) {
1939 		destroy_workqueue(msm_host->workqueue);
1940 		msm_host->workqueue = NULL;
1941 	}
1942 
1943 	mutex_destroy(&msm_host->cmd_mutex);
1944 	mutex_destroy(&msm_host->dev_mutex);
1945 
1946 	pm_runtime_disable(&msm_host->pdev->dev);
1947 }
1948 
1949 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1950 					struct drm_device *dev)
1951 {
1952 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1953 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1954 	int ret;
1955 
1956 	msm_host->dev = dev;
1957 
1958 	ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1959 	if (ret) {
1960 		pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1961 		return ret;
1962 	}
1963 
1964 	return 0;
1965 }
1966 
1967 int msm_dsi_host_register(struct mipi_dsi_host *host)
1968 {
1969 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1970 	int ret;
1971 
1972 	/* Register mipi dsi host */
1973 	if (!msm_host->registered) {
1974 		host->dev = &msm_host->pdev->dev;
1975 		host->ops = &dsi_host_ops;
1976 		ret = mipi_dsi_host_register(host);
1977 		if (ret)
1978 			return ret;
1979 
1980 		msm_host->registered = true;
1981 	}
1982 
1983 	return 0;
1984 }
1985 
1986 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1987 {
1988 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1989 
1990 	if (msm_host->registered) {
1991 		mipi_dsi_host_unregister(host);
1992 		host->dev = NULL;
1993 		host->ops = NULL;
1994 		msm_host->registered = false;
1995 	}
1996 }
1997 
1998 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1999 				const struct mipi_dsi_msg *msg)
2000 {
2001 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2002 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2003 
2004 	/* TODO: make sure dsi_cmd_mdp is idle.
2005 	 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
2006 	 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2007 	 * How to handle the old versions? Wait for mdp cmd done?
2008 	 */
2009 
2010 	/*
2011 	 * mdss interrupt is generated in mdp core clock domain
2012 	 * mdp clock need to be enabled to receive dsi interrupt
2013 	 */
2014 	pm_runtime_get_sync(&msm_host->pdev->dev);
2015 	cfg_hnd->ops->link_clk_set_rate(msm_host);
2016 	cfg_hnd->ops->link_clk_enable(msm_host);
2017 
2018 	/* TODO: vote for bus bandwidth */
2019 
2020 	if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2021 		dsi_set_tx_power_mode(0, msm_host);
2022 
2023 	msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2024 	dsi_write(msm_host, REG_DSI_CTRL,
2025 		msm_host->dma_cmd_ctrl_restore |
2026 		DSI_CTRL_CMD_MODE_EN |
2027 		DSI_CTRL_ENABLE);
2028 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2029 
2030 	return 0;
2031 }
2032 
2033 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2034 				const struct mipi_dsi_msg *msg)
2035 {
2036 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2037 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2038 
2039 	dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2040 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2041 
2042 	if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2043 		dsi_set_tx_power_mode(1, msm_host);
2044 
2045 	/* TODO: unvote for bus bandwidth */
2046 
2047 	cfg_hnd->ops->link_clk_disable(msm_host);
2048 	pm_runtime_put(&msm_host->pdev->dev);
2049 }
2050 
2051 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2052 				const struct mipi_dsi_msg *msg)
2053 {
2054 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2055 
2056 	return dsi_cmds2buf_tx(msm_host, msg);
2057 }
2058 
2059 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2060 				const struct mipi_dsi_msg *msg)
2061 {
2062 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2063 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2064 	int data_byte, rx_byte, dlen, end;
2065 	int short_response, diff, pkt_size, ret = 0;
2066 	char cmd;
2067 	int rlen = msg->rx_len;
2068 	u8 *buf;
2069 
2070 	if (rlen <= 2) {
2071 		short_response = 1;
2072 		pkt_size = rlen;
2073 		rx_byte = 4;
2074 	} else {
2075 		short_response = 0;
2076 		data_byte = 10;	/* first read */
2077 		if (rlen < data_byte)
2078 			pkt_size = rlen;
2079 		else
2080 			pkt_size = data_byte;
2081 		rx_byte = data_byte + 6; /* 4 header + 2 crc */
2082 	}
2083 
2084 	buf = msm_host->rx_buf;
2085 	end = 0;
2086 	while (!end) {
2087 		u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2088 		struct mipi_dsi_msg max_pkt_size_msg = {
2089 			.channel = msg->channel,
2090 			.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2091 			.tx_len = 2,
2092 			.tx_buf = tx,
2093 		};
2094 
2095 		DBG("rlen=%d pkt_size=%d rx_byte=%d",
2096 			rlen, pkt_size, rx_byte);
2097 
2098 		ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2099 		if (ret < 2) {
2100 			pr_err("%s: Set max pkt size failed, %d\n",
2101 				__func__, ret);
2102 			return -EINVAL;
2103 		}
2104 
2105 		if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2106 			(cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2107 			/* Clear the RDBK_DATA registers */
2108 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2109 					DSI_RDBK_DATA_CTRL_CLR);
2110 			wmb(); /* make sure the RDBK registers are cleared */
2111 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2112 			wmb(); /* release cleared status before transfer */
2113 		}
2114 
2115 		ret = dsi_cmds2buf_tx(msm_host, msg);
2116 		if (ret < 0) {
2117 			pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2118 			return ret;
2119 		} else if (ret < msg->tx_len) {
2120 			pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
2121 			return -ECOMM;
2122 		}
2123 
2124 		/*
2125 		 * once cmd_dma_done interrupt received,
2126 		 * return data from client is ready and stored
2127 		 * at RDBK_DATA register already
2128 		 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2129 		 * after that dcs header lost during shift into registers
2130 		 */
2131 		dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2132 
2133 		if (dlen <= 0)
2134 			return 0;
2135 
2136 		if (short_response)
2137 			break;
2138 
2139 		if (rlen <= data_byte) {
2140 			diff = data_byte - rlen;
2141 			end = 1;
2142 		} else {
2143 			diff = 0;
2144 			rlen -= data_byte;
2145 		}
2146 
2147 		if (!end) {
2148 			dlen -= 2; /* 2 crc */
2149 			dlen -= diff;
2150 			buf += dlen;	/* next start position */
2151 			data_byte = 14;	/* NOT first read */
2152 			if (rlen < data_byte)
2153 				pkt_size += rlen;
2154 			else
2155 				pkt_size += data_byte;
2156 			DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2157 		}
2158 	}
2159 
2160 	/*
2161 	 * For single Long read, if the requested rlen < 10,
2162 	 * we need to shift the start position of rx
2163 	 * data buffer to skip the bytes which are not
2164 	 * updated.
2165 	 */
2166 	if (pkt_size < 10 && !short_response)
2167 		buf = msm_host->rx_buf + (10 - rlen);
2168 	else
2169 		buf = msm_host->rx_buf;
2170 
2171 	cmd = buf[0];
2172 	switch (cmd) {
2173 	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2174 		pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2175 		ret = 0;
2176 		break;
2177 	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2178 	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2179 		ret = dsi_short_read1_resp(buf, msg);
2180 		break;
2181 	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2182 	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2183 		ret = dsi_short_read2_resp(buf, msg);
2184 		break;
2185 	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2186 	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2187 		ret = dsi_long_read_resp(buf, msg);
2188 		break;
2189 	default:
2190 		pr_warn("%s:Invalid response cmd\n", __func__);
2191 		ret = 0;
2192 	}
2193 
2194 	return ret;
2195 }
2196 
2197 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2198 				  u32 len)
2199 {
2200 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2201 
2202 	dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2203 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2204 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2205 
2206 	/* Make sure trigger happens */
2207 	wmb();
2208 }
2209 
2210 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host,
2211 	struct msm_dsi_phy *src_phy)
2212 {
2213 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2214 
2215 	msm_host->cphy_mode = src_phy->cphy_mode;
2216 }
2217 
2218 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2219 {
2220 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2221 
2222 	DBG("");
2223 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2224 	/* Make sure fully reset */
2225 	wmb();
2226 	udelay(1000);
2227 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2228 	udelay(100);
2229 }
2230 
2231 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2232 			struct msm_dsi_phy_clk_request *clk_req,
2233 			bool is_bonded_dsi)
2234 {
2235 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2236 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2237 	int ret;
2238 
2239 	ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
2240 	if (ret) {
2241 		pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2242 		return;
2243 	}
2244 
2245 	/* CPHY transmits 16 bits over 7 clock cycles
2246 	 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk),
2247 	 * so multiply by 7 to get the "bitclk rate"
2248 	 */
2249 	if (msm_host->cphy_mode)
2250 		clk_req->bitclk_rate = msm_host->byte_clk_rate * 7;
2251 	else
2252 		clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2253 	clk_req->escclk_rate = msm_host->esc_clk_rate;
2254 }
2255 
2256 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host)
2257 {
2258 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2259 
2260 	enable_irq(msm_host->irq);
2261 }
2262 
2263 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host)
2264 {
2265 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2266 
2267 	disable_irq(msm_host->irq);
2268 }
2269 
2270 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2271 {
2272 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2273 
2274 	dsi_op_mode_config(msm_host,
2275 		!!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2276 
2277 	/* TODO: clock should be turned off for command mode,
2278 	 * and only turned on before MDP START.
2279 	 * This part of code should be enabled once mdp driver support it.
2280 	 */
2281 	/* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2282 	 *	dsi_link_clk_disable(msm_host);
2283 	 *	pm_runtime_put(&msm_host->pdev->dev);
2284 	 * }
2285 	 */
2286 	msm_host->enabled = true;
2287 	return 0;
2288 }
2289 
2290 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2291 {
2292 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2293 
2294 	msm_host->enabled = false;
2295 	dsi_op_mode_config(msm_host,
2296 		!!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2297 
2298 	/* Since we have disabled INTF, the video engine won't stop so that
2299 	 * the cmd engine will be blocked.
2300 	 * Reset to disable video engine so that we can send off cmd.
2301 	 */
2302 	dsi_sw_reset(msm_host);
2303 
2304 	return 0;
2305 }
2306 
2307 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2308 {
2309 	enum sfpb_ahb_arb_master_port_en en;
2310 
2311 	if (!msm_host->sfpb)
2312 		return;
2313 
2314 	en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2315 
2316 	regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2317 			SFPB_GPREG_MASTER_PORT_EN__MASK,
2318 			SFPB_GPREG_MASTER_PORT_EN(en));
2319 }
2320 
2321 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2322 			struct msm_dsi_phy_shared_timings *phy_shared_timings,
2323 			bool is_bonded_dsi, struct msm_dsi_phy *phy)
2324 {
2325 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2326 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2327 	int ret = 0;
2328 
2329 	mutex_lock(&msm_host->dev_mutex);
2330 	if (msm_host->power_on) {
2331 		DBG("dsi host already on");
2332 		goto unlock_ret;
2333 	}
2334 
2335 	msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate;
2336 	if (phy_shared_timings->byte_intf_clk_div_2)
2337 		msm_host->byte_intf_clk_rate /= 2;
2338 
2339 	msm_dsi_sfpb_config(msm_host, true);
2340 
2341 	ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators,
2342 				    msm_host->supplies);
2343 	if (ret) {
2344 		pr_err("%s:Failed to enable vregs.ret=%d\n",
2345 			__func__, ret);
2346 		goto unlock_ret;
2347 	}
2348 
2349 	pm_runtime_get_sync(&msm_host->pdev->dev);
2350 	ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
2351 	if (!ret)
2352 		ret = cfg_hnd->ops->link_clk_enable(msm_host);
2353 	if (ret) {
2354 		pr_err("%s: failed to enable link clocks. ret=%d\n",
2355 		       __func__, ret);
2356 		goto fail_disable_reg;
2357 	}
2358 
2359 	ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2360 	if (ret) {
2361 		pr_err("%s: failed to set pinctrl default state, %d\n",
2362 			__func__, ret);
2363 		goto fail_disable_clk;
2364 	}
2365 
2366 	dsi_timing_setup(msm_host, is_bonded_dsi);
2367 	dsi_sw_reset(msm_host);
2368 	dsi_ctrl_enable(msm_host, phy_shared_timings, phy);
2369 
2370 	if (msm_host->disp_en_gpio)
2371 		gpiod_set_value(msm_host->disp_en_gpio, 1);
2372 
2373 	msm_host->power_on = true;
2374 	mutex_unlock(&msm_host->dev_mutex);
2375 
2376 	return 0;
2377 
2378 fail_disable_clk:
2379 	cfg_hnd->ops->link_clk_disable(msm_host);
2380 	pm_runtime_put(&msm_host->pdev->dev);
2381 fail_disable_reg:
2382 	regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2383 			       msm_host->supplies);
2384 unlock_ret:
2385 	mutex_unlock(&msm_host->dev_mutex);
2386 	return ret;
2387 }
2388 
2389 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2390 {
2391 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2392 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2393 
2394 	mutex_lock(&msm_host->dev_mutex);
2395 	if (!msm_host->power_on) {
2396 		DBG("dsi host already off");
2397 		goto unlock_ret;
2398 	}
2399 
2400 	dsi_ctrl_disable(msm_host);
2401 
2402 	if (msm_host->disp_en_gpio)
2403 		gpiod_set_value(msm_host->disp_en_gpio, 0);
2404 
2405 	pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2406 
2407 	cfg_hnd->ops->link_clk_disable(msm_host);
2408 	pm_runtime_put(&msm_host->pdev->dev);
2409 
2410 	regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2411 			       msm_host->supplies);
2412 
2413 	msm_dsi_sfpb_config(msm_host, false);
2414 
2415 	DBG("-");
2416 
2417 	msm_host->power_on = false;
2418 
2419 unlock_ret:
2420 	mutex_unlock(&msm_host->dev_mutex);
2421 	return 0;
2422 }
2423 
2424 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2425 				  const struct drm_display_mode *mode)
2426 {
2427 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2428 
2429 	if (msm_host->mode) {
2430 		drm_mode_destroy(msm_host->dev, msm_host->mode);
2431 		msm_host->mode = NULL;
2432 	}
2433 
2434 	msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2435 	if (!msm_host->mode) {
2436 		pr_err("%s: cannot duplicate mode\n", __func__);
2437 		return -ENOMEM;
2438 	}
2439 
2440 	return 0;
2441 }
2442 
2443 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
2444 					    const struct drm_display_mode *mode)
2445 {
2446 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2447 	struct drm_dsc_config *dsc = msm_host->dsc;
2448 	int pic_width = mode->hdisplay;
2449 	int pic_height = mode->vdisplay;
2450 
2451 	if (!msm_host->dsc)
2452 		return MODE_OK;
2453 
2454 	if (pic_width % dsc->slice_width) {
2455 		pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
2456 		       pic_width, dsc->slice_width);
2457 		return MODE_H_ILLEGAL;
2458 	}
2459 
2460 	if (pic_height % dsc->slice_height) {
2461 		pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
2462 		       pic_height, dsc->slice_height);
2463 		return MODE_V_ILLEGAL;
2464 	}
2465 
2466 	return MODE_OK;
2467 }
2468 
2469 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2470 {
2471 	return to_msm_dsi_host(host)->mode_flags;
2472 }
2473 
2474 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2475 {
2476 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2477 
2478 	pm_runtime_get_sync(&msm_host->pdev->dev);
2479 
2480 	msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2481 			msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2482 
2483 	pm_runtime_put_sync(&msm_host->pdev->dev);
2484 }
2485 
2486 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host)
2487 {
2488 	u32 reg;
2489 
2490 	reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2491 
2492 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);
2493 	/* draw checkered rectangle pattern */
2494 	dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,
2495 			DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN);
2496 	/* use 24-bit RGB test pttern */
2497 	dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,
2498 			DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) |
2499 			DSI_TPG_VIDEO_CONFIG_RGB);
2500 
2501 	reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN);
2502 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2503 
2504 	DBG("Video test pattern setup done\n");
2505 }
2506 
2507 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host)
2508 {
2509 	u32 reg;
2510 
2511 	reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2512 
2513 	/* initial value for test pattern */
2514 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
2515 
2516 	reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN);
2517 
2518 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2519 	/* draw checkered rectangle pattern */
2520 	dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,
2521 			DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN);
2522 
2523 	DBG("Cmd test pattern setup done\n");
2524 }
2525 
2526 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
2527 {
2528 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2529 	bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);
2530 	u32 reg;
2531 
2532 	if (is_video_mode)
2533 		msm_dsi_host_video_test_pattern_setup(msm_host);
2534 	else
2535 		msm_dsi_host_cmd_test_pattern_setup(msm_host);
2536 
2537 	reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2538 	/* enable the test pattern generator */
2539 	dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));
2540 
2541 	/* for command mode need to trigger one frame from tpg */
2542 	if (!is_video_mode)
2543 		dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
2544 				DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
2545 }
2546 
2547 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
2548 {
2549 	struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2550 
2551 	return msm_host->dsc;
2552 }
2553