1 #ifndef __NV50_KMS_ATOM_H__ 2 #define __NV50_KMS_ATOM_H__ 3 #define nv50_atom(p) container_of((p), struct nv50_atom, state) 4 #include <drm/drm_atomic.h> 5 6 struct nv50_atom { 7 struct drm_atomic_state state; 8 9 struct list_head outp; 10 bool lock_core; 11 bool flush_disable; 12 }; 13 14 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state) 15 16 struct nv50_head_atom { 17 struct drm_crtc_state state; 18 19 struct { 20 u32 mask; 21 u32 olut; 22 } wndw; 23 24 struct { 25 u16 iW; 26 u16 iH; 27 u16 oW; 28 u16 oH; 29 } view; 30 31 struct nv50_head_mode { 32 bool interlace; 33 u32 clock; 34 struct { 35 u16 active; 36 u16 synce; 37 u16 blanke; 38 u16 blanks; 39 } h; 40 struct { 41 u32 active; 42 u16 synce; 43 u16 blanke; 44 u16 blanks; 45 u16 blank2s; 46 u16 blank2e; 47 u16 blankus; 48 } v; 49 } mode; 50 51 struct { 52 bool visible; 53 u32 handle; 54 u64 offset:40; 55 u8 buffer:1; 56 u8 mode:4; 57 u16 size:11; 58 u8 range:2; 59 u8 output_mode:2; 60 void (*load)(struct drm_color_lut *, int size, void __iomem *); 61 } olut; 62 63 struct { 64 bool visible; 65 u32 handle; 66 u64 offset:40; 67 u8 format; 68 u8 kind:7; 69 u8 layout:1; 70 u8 blockh:4; 71 u16 blocks:12; 72 u32 pitch:20; 73 u16 x; 74 u16 y; 75 u16 w; 76 u16 h; 77 } core; 78 79 struct { 80 bool visible; 81 u32 handle; 82 u64 offset:40; 83 u8 layout:2; 84 u8 format:8; 85 } curs; 86 87 struct { 88 u8 depth; 89 u8 cpp; 90 u16 x; 91 u16 y; 92 u16 w; 93 u16 h; 94 } base; 95 96 struct { 97 u8 cpp; 98 } ovly; 99 100 struct { 101 bool enable:1; 102 u8 bits:2; 103 u8 mode:4; 104 } dither; 105 106 struct { 107 struct { 108 u16 cos:12; 109 u16 sin:12; 110 } sat; 111 } procamp; 112 113 struct { 114 u8 nhsync:1; 115 u8 nvsync:1; 116 u8 depth:4; 117 u8 bpc; 118 } or; 119 120 /* Currently only used for MST */ 121 struct { 122 int pbn; 123 u8 tu:6; 124 } dp; 125 126 union nv50_head_atom_mask { 127 struct { 128 bool olut:1; 129 bool core:1; 130 bool curs:1; 131 bool view:1; 132 bool mode:1; 133 bool base:1; 134 bool ovly:1; 135 bool dither:1; 136 bool procamp:1; 137 bool or:1; 138 }; 139 u16 mask; 140 } set, clr; 141 }; 142 143 static inline struct nv50_head_atom * 144 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) 145 { 146 struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc); 147 if (IS_ERR(statec)) 148 return (void *)statec; 149 return nv50_head_atom(statec); 150 } 151 152 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state) 153 154 struct nv50_wndw_atom { 155 struct drm_plane_state state; 156 157 struct drm_property_blob *ilut; 158 bool visible; 159 160 struct { 161 u32 handle; 162 u16 offset:12; 163 bool awaken:1; 164 } ntfy; 165 166 struct { 167 u32 handle; 168 u16 offset:12; 169 u32 acquire; 170 u32 release; 171 } sema; 172 173 struct { 174 u32 handle; 175 struct { 176 u64 offset:40; 177 u8 buffer:1; 178 u8 enable:2; 179 u8 mode:4; 180 u16 size:11; 181 u8 range:2; 182 u8 output_mode:2; 183 void (*load)(struct drm_color_lut *, int size, 184 void __iomem *); 185 } i; 186 } xlut; 187 188 struct { 189 u32 matrix[12]; 190 bool valid; 191 } csc; 192 193 struct { 194 u8 mode:2; 195 u8 interval:4; 196 197 u8 colorspace:2; 198 u8 format; 199 u8 kind:7; 200 u8 layout:1; 201 u8 blockh:4; 202 u16 blocks[3]; 203 u32 pitch[3]; 204 u16 w; 205 u16 h; 206 207 u32 handle[6]; 208 u64 offset[6]; 209 } image; 210 211 struct { 212 u16 sx; 213 u16 sy; 214 u16 sw; 215 u16 sh; 216 u16 dw; 217 u16 dh; 218 } scale; 219 220 struct { 221 u16 x; 222 u16 y; 223 } point; 224 225 struct { 226 u8 depth; 227 u8 k1; 228 u8 src_color:4; 229 u8 dst_color:4; 230 } blend; 231 232 union nv50_wndw_atom_mask { 233 struct { 234 bool ntfy:1; 235 bool sema:1; 236 bool xlut:1; 237 bool csc:1; 238 bool image:1; 239 bool scale:1; 240 bool point:1; 241 bool blend:1; 242 }; 243 u8 mask; 244 } set, clr; 245 }; 246 #endif 247