1 #ifndef __src_nvidia_kernel_inc_vgpu_rpc_headers_h__
2 #define __src_nvidia_kernel_inc_vgpu_rpc_headers_h__
3 
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
5 
6 /*
7  * SPDX-FileCopyrightText: Copyright (c) 2017-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8  * SPDX-License-Identifier: MIT
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a
11  * copy of this software and associated documentation files (the "Software"),
12  * to deal in the Software without restriction, including without limitation
13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14  * and/or sell copies of the Software, and to permit persons to whom the
15  * Software is furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26  * DEALINGS IN THE SOFTWARE.
27  */
28 
29 #define MAX_GPC_COUNT           32
30 
31 typedef enum
32 {
33     NV_RPC_UPDATE_PDE_BAR_1,
34     NV_RPC_UPDATE_PDE_BAR_2,
35     NV_RPC_UPDATE_PDE_BAR_INVALID,
36 } NV_RPC_UPDATE_PDE_BAR_TYPE;
37 
38 typedef struct VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS
39 {
40     NvU32 headIndex;
41     NvU32 maxHResolution;
42     NvU32 maxVResolution;
43 } VIRTUAL_DISPLAY_GET_MAX_RESOLUTION_PARAMS;
44 
45 typedef struct VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS
46 {
47     NvU32 numHeads;
48     NvU32 maxNumHeads;
49 } VIRTUAL_DISPLAY_GET_NUM_HEADS_PARAMS;
50 
51 #endif
52