xref: /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c (revision 02917aa3)
1 /*
2  * Copyright 2016 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs <bskeggs@redhat.com>
23  */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26 
27 #include <nvif/class.h>
28 
29 void
30 gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr)
31 {
32 	struct nvkm_device *device = gr->base.engine.subdev.device;
33 	u32 mask = 0, data, gpc;
34 
35 	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
36 		data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f;
37 		mask |= data << (gpc * 4);
38 	}
39 
40 	nvkm_wr32(device, 0x4181d0, mask);
41 }
42 
43 static const struct gf100_gr_func
44 gp102_gr = {
45 	.init = gp100_gr_init,
46 	.init_gpc_mmu = gm200_gr_init_gpc_mmu,
47 	.init_vsc_stream_master = gk104_gr_init_vsc_stream_master,
48 	.init_zcull = gf117_gr_init_zcull,
49 	.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
50 	.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
51 	.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
52 	.init_num_active_ltcs = gp100_gr_init_num_active_ltcs,
53 	.rops = gm200_gr_rops,
54 	.ppc_nr = 3,
55 	.grctx = &gp102_grctx,
56 	.sclass = {
57 		{ -1, -1, FERMI_TWOD_A },
58 		{ -1, -1, KEPLER_INLINE_TO_MEMORY_B },
59 		{ -1, -1, PASCAL_B, &gf100_fermi },
60 		{ -1, -1, PASCAL_COMPUTE_B },
61 		{}
62 	}
63 };
64 
65 int
66 gp102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
67 {
68 	return gm200_gr_new_(&gp102_gr, device, index, pgr);
69 }
70