1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/conn.h> 28 #include <subdev/bios/dcb.h> 29 #include <subdev/bios/dp.h> 30 #include <subdev/bios/gpio.h> 31 #include <subdev/bios/init.h> 32 #include <subdev/bios/ramcfg.h> 33 34 #include <subdev/devinit.h> 35 #include <subdev/gpio.h> 36 #include <subdev/i2c.h> 37 #include <subdev/vga.h> 38 39 #define bioslog(lvl, fmt, args...) do { \ 40 nvkm_printk(init->subdev, lvl, info, "0x%04x[%c]: "fmt, \ 41 init->offset, init_exec(init) ? \ 42 '0' + (init->nested - 1) : ' ', ##args); \ 43 } while(0) 44 #define cont(fmt, args...) do { \ 45 if (init->subdev->debug >= NV_DBG_TRACE) \ 46 printk(fmt, ##args); \ 47 } while(0) 48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) 49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args) 50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args) 51 52 /****************************************************************************** 53 * init parser control flow helpers 54 *****************************************************************************/ 55 56 static inline bool 57 init_exec(struct nvbios_init *init) 58 { 59 return (init->execute == 1) || ((init->execute & 5) == 5); 60 } 61 62 static inline void 63 init_exec_set(struct nvbios_init *init, bool exec) 64 { 65 if (exec) init->execute &= 0xfd; 66 else init->execute |= 0x02; 67 } 68 69 static inline void 70 init_exec_inv(struct nvbios_init *init) 71 { 72 init->execute ^= 0x02; 73 } 74 75 static inline void 76 init_exec_force(struct nvbios_init *init, bool exec) 77 { 78 if (exec) init->execute |= 0x04; 79 else init->execute &= 0xfb; 80 } 81 82 /****************************************************************************** 83 * init parser wrappers for normal register/i2c/whatever accessors 84 *****************************************************************************/ 85 86 static inline int 87 init_or(struct nvbios_init *init) 88 { 89 if (init_exec(init)) { 90 if (init->outp) 91 return ffs(init->outp->or) - 1; 92 error("script needs OR!!\n"); 93 } 94 return 0; 95 } 96 97 static inline int 98 init_link(struct nvbios_init *init) 99 { 100 if (init_exec(init)) { 101 if (init->outp) 102 return !(init->outp->sorconf.link & 1); 103 error("script needs OR link\n"); 104 } 105 return 0; 106 } 107 108 static inline int 109 init_crtc(struct nvbios_init *init) 110 { 111 if (init_exec(init)) { 112 if (init->crtc >= 0) 113 return init->crtc; 114 error("script needs crtc\n"); 115 } 116 return 0; 117 } 118 119 static u8 120 init_conn(struct nvbios_init *init) 121 { 122 struct nvkm_bios *bios = init->bios; 123 struct nvbios_connE connE; 124 u8 ver, hdr; 125 u32 conn; 126 127 if (init_exec(init)) { 128 if (init->outp) { 129 conn = init->outp->connector; 130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); 131 if (conn) 132 return connE.type; 133 } 134 135 error("script needs connector type\n"); 136 } 137 138 return 0xff; 139 } 140 141 static inline u32 142 init_nvreg(struct nvbios_init *init, u32 reg) 143 { 144 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 145 146 /* C51 (at least) sometimes has the lower bits set which the VBIOS 147 * interprets to mean that access needs to go through certain IO 148 * ports instead. The NVIDIA binary driver has been seen to access 149 * these through the NV register address, so lets assume we can 150 * do the same 151 */ 152 reg &= ~0x00000003; 153 154 /* GF8+ display scripts need register addresses mangled a bit to 155 * select a specific CRTC/OR 156 */ 157 if (nv_device(init->bios)->card_type >= NV_50) { 158 if (reg & 0x80000000) { 159 reg += init_crtc(init) * 0x800; 160 reg &= ~0x80000000; 161 } 162 163 if (reg & 0x40000000) { 164 reg += init_or(init) * 0x800; 165 reg &= ~0x40000000; 166 if (reg & 0x20000000) { 167 reg += init_link(init) * 0x80; 168 reg &= ~0x20000000; 169 } 170 } 171 } 172 173 if (reg & ~0x00fffffc) 174 warn("unknown bits in register 0x%08x\n", reg); 175 176 if (devinit->mmio) 177 reg = devinit->mmio(devinit, reg); 178 return reg; 179 } 180 181 static u32 182 init_rd32(struct nvbios_init *init, u32 reg) 183 { 184 struct nvkm_device *device = init->bios->subdev.device; 185 reg = init_nvreg(init, reg); 186 if (reg != ~0 && init_exec(init)) 187 return nvkm_rd32(device, reg); 188 return 0x00000000; 189 } 190 191 static void 192 init_wr32(struct nvbios_init *init, u32 reg, u32 val) 193 { 194 struct nvkm_device *device = init->bios->subdev.device; 195 reg = init_nvreg(init, reg); 196 if (reg != ~0 && init_exec(init)) 197 nvkm_wr32(device, reg, val); 198 } 199 200 static u32 201 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) 202 { 203 struct nvkm_device *device = init->bios->subdev.device; 204 reg = init_nvreg(init, reg); 205 if (reg != ~0 && init_exec(init)) { 206 u32 tmp = nvkm_rd32(device, reg); 207 nvkm_wr32(device, reg, (tmp & ~mask) | val); 208 return tmp; 209 } 210 return 0x00000000; 211 } 212 213 static u8 214 init_rdport(struct nvbios_init *init, u16 port) 215 { 216 if (init_exec(init)) 217 return nvkm_rdport(init->subdev->device, init->crtc, port); 218 return 0x00; 219 } 220 221 static void 222 init_wrport(struct nvbios_init *init, u16 port, u8 value) 223 { 224 if (init_exec(init)) 225 nvkm_wrport(init->subdev->device, init->crtc, port, value); 226 } 227 228 static u8 229 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) 230 { 231 struct nvkm_subdev *subdev = init->subdev; 232 if (init_exec(init)) { 233 int head = init->crtc < 0 ? 0 : init->crtc; 234 return nvkm_rdvgai(subdev->device, head, port, index); 235 } 236 return 0x00; 237 } 238 239 static void 240 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) 241 { 242 struct nvkm_device *device = init->subdev->device; 243 244 /* force head 0 for updates to cr44, it only exists on first head */ 245 if (device->card_type < NV_50) { 246 if (port == 0x03d4 && index == 0x44) 247 init->crtc = 0; 248 } 249 250 if (init_exec(init)) { 251 int head = init->crtc < 0 ? 0 : init->crtc; 252 nvkm_wrvgai(device, head, port, index, value); 253 } 254 255 /* select head 1 if cr44 write selected it */ 256 if (device->card_type < NV_50) { 257 if (port == 0x03d4 && index == 0x44 && value == 3) 258 init->crtc = 1; 259 } 260 } 261 262 static struct i2c_adapter * 263 init_i2c(struct nvbios_init *init, int index) 264 { 265 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c; 266 struct nvkm_i2c_bus *bus; 267 268 if (index == 0xff) { 269 index = NVKM_I2C_BUS_PRI; 270 if (init->outp && init->outp->i2c_upper_default) 271 index = NVKM_I2C_BUS_SEC; 272 } 273 274 bus = nvkm_i2c_bus_find(i2c, index); 275 return bus ? &bus->i2c : NULL; 276 } 277 278 static int 279 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) 280 { 281 struct i2c_adapter *adap = init_i2c(init, index); 282 if (adap && init_exec(init)) 283 return nvkm_rdi2cr(adap, addr, reg); 284 return -ENODEV; 285 } 286 287 static int 288 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) 289 { 290 struct i2c_adapter *adap = init_i2c(init, index); 291 if (adap && init_exec(init)) 292 return nvkm_wri2cr(adap, addr, reg, val); 293 return -ENODEV; 294 } 295 296 static struct nvkm_i2c_aux * 297 init_aux(struct nvbios_init *init) 298 { 299 struct nvkm_i2c *i2c = init->bios->subdev.device->i2c; 300 if (!init->outp) { 301 if (init_exec(init)) 302 error("script needs output for aux\n"); 303 return NULL; 304 } 305 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index); 306 } 307 308 static u8 309 init_rdauxr(struct nvbios_init *init, u32 addr) 310 { 311 struct nvkm_i2c_aux *aux = init_aux(init); 312 u8 data; 313 314 if (aux && init_exec(init)) { 315 int ret = nvkm_rdaux(aux, addr, &data, 1); 316 if (ret == 0) 317 return data; 318 trace("auxch read failed with %d\n", ret); 319 } 320 321 return 0x00; 322 } 323 324 static int 325 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) 326 { 327 struct nvkm_i2c_aux *aux = init_aux(init); 328 if (aux && init_exec(init)) { 329 int ret = nvkm_wraux(aux, addr, &data, 1); 330 if (ret) 331 trace("auxch write failed with %d\n", ret); 332 return ret; 333 } 334 return -ENODEV; 335 } 336 337 static void 338 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) 339 { 340 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 341 if (devinit->pll_set && init_exec(init)) { 342 int ret = devinit->pll_set(devinit, id, freq); 343 if (ret) 344 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); 345 } 346 } 347 348 /****************************************************************************** 349 * parsing of bios structures that are required to execute init tables 350 *****************************************************************************/ 351 352 static u16 353 init_table(struct nvkm_bios *bios, u16 *len) 354 { 355 struct bit_entry bit_I; 356 357 if (!bit_entry(bios, 'I', &bit_I)) { 358 *len = bit_I.length; 359 return bit_I.offset; 360 } 361 362 if (bmp_version(bios) >= 0x0510) { 363 *len = 14; 364 return bios->bmp_offset + 75; 365 } 366 367 return 0x0000; 368 } 369 370 static u16 371 init_table_(struct nvbios_init *init, u16 offset, const char *name) 372 { 373 struct nvkm_bios *bios = init->bios; 374 u16 len, data = init_table(bios, &len); 375 if (data) { 376 if (len >= offset + 2) { 377 data = nvbios_rd16(bios, data + offset); 378 if (data) 379 return data; 380 381 warn("%s pointer invalid\n", name); 382 return 0x0000; 383 } 384 385 warn("init data too short for %s pointer", name); 386 return 0x0000; 387 } 388 389 warn("init data not found\n"); 390 return 0x0000; 391 } 392 393 #define init_script_table(b) init_table_((b), 0x00, "script table") 394 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") 395 #define init_macro_table(b) init_table_((b), 0x04, "macro table") 396 #define init_condition_table(b) init_table_((b), 0x06, "condition table") 397 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") 398 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") 399 #define init_function_table(b) init_table_((b), 0x0c, "function table") 400 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); 401 402 static u16 403 init_script(struct nvkm_bios *bios, int index) 404 { 405 struct nvbios_init init = { .bios = bios }; 406 u16 bmp_ver = bmp_version(bios), data; 407 408 if (bmp_ver && bmp_ver < 0x0510) { 409 if (index > 1 || bmp_ver < 0x0100) 410 return 0x0000; 411 412 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); 413 return nvbios_rd16(bios, data + (index * 2)); 414 } 415 416 data = init_script_table(&init); 417 if (data) 418 return nvbios_rd16(bios, data + (index * 2)); 419 420 return 0x0000; 421 } 422 423 static u16 424 init_unknown_script(struct nvkm_bios *bios) 425 { 426 u16 len, data = init_table(bios, &len); 427 if (data && len >= 16) 428 return nvbios_rd16(bios, data + 14); 429 return 0x0000; 430 } 431 432 static u8 433 init_ram_restrict_group_count(struct nvbios_init *init) 434 { 435 return nvbios_ramcfg_count(init->bios); 436 } 437 438 static u8 439 init_ram_restrict(struct nvbios_init *init) 440 { 441 /* This appears to be the behaviour of the VBIOS parser, and *is* 442 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to 443 * avoid fucking up the memory controller (somehow) by reading it 444 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. 445 * 446 * Preserving the non-caching behaviour on earlier chipsets just 447 * in case *not* re-reading the strap causes similar breakage. 448 */ 449 if (!init->ramcfg || init->bios->version.major < 0x70) 450 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); 451 return (init->ramcfg & 0x7fffffff); 452 } 453 454 static u8 455 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) 456 { 457 struct nvkm_bios *bios = init->bios; 458 u16 table = init_xlat_table(init); 459 if (table) { 460 u16 data = nvbios_rd16(bios, table + (index * 2)); 461 if (data) 462 return nvbios_rd08(bios, data + offset); 463 warn("xlat table pointer %d invalid\n", index); 464 } 465 return 0x00; 466 } 467 468 /****************************************************************************** 469 * utility functions used by various init opcode handlers 470 *****************************************************************************/ 471 472 static bool 473 init_condition_met(struct nvbios_init *init, u8 cond) 474 { 475 struct nvkm_bios *bios = init->bios; 476 u16 table = init_condition_table(init); 477 if (table) { 478 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); 479 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4); 480 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8); 481 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", 482 cond, reg, msk, val); 483 return (init_rd32(init, reg) & msk) == val; 484 } 485 return false; 486 } 487 488 static bool 489 init_io_condition_met(struct nvbios_init *init, u8 cond) 490 { 491 struct nvkm_bios *bios = init->bios; 492 u16 table = init_io_condition_table(init); 493 if (table) { 494 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0); 495 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2); 496 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3); 497 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4); 498 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", 499 cond, port, index, mask, value); 500 return (init_rdvgai(init, port, index) & mask) == value; 501 } 502 return false; 503 } 504 505 static bool 506 init_io_flag_condition_met(struct nvbios_init *init, u8 cond) 507 { 508 struct nvkm_bios *bios = init->bios; 509 u16 table = init_io_flag_condition_table(init); 510 if (table) { 511 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0); 512 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2); 513 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3); 514 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4); 515 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5); 516 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7); 517 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8); 518 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; 519 return (nvbios_rd08(bios, data + ioval) & dmask) == value; 520 } 521 return false; 522 } 523 524 static inline u32 525 init_shift(u32 data, u8 shift) 526 { 527 if (shift < 0x80) 528 return data >> shift; 529 return data << (0x100 - shift); 530 } 531 532 static u32 533 init_tmds_reg(struct nvbios_init *init, u8 tmds) 534 { 535 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. 536 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 537 * CR58 for CR57 = 0 to index a table of offsets to the basic 538 * 0x6808b0 address. 539 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 540 * CR58 for CR57 = 0 to index a table of offsets to the basic 541 * 0x6808b0 address, and then flip the offset by 8. 542 */ 543 const int pramdac_offset[13] = { 544 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 545 const u32 pramdac_table[4] = { 546 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 547 548 if (tmds >= 0x80) { 549 if (init->outp) { 550 u32 dacoffset = pramdac_offset[init->outp->or]; 551 if (tmds == 0x81) 552 dacoffset ^= 8; 553 return 0x6808b0 + dacoffset; 554 } 555 556 if (init_exec(init)) 557 error("tmds opcodes need dcb\n"); 558 } else { 559 if (tmds < ARRAY_SIZE(pramdac_table)) 560 return pramdac_table[tmds]; 561 562 error("tmds selector 0x%02x unknown\n", tmds); 563 } 564 565 return 0; 566 } 567 568 /****************************************************************************** 569 * init opcode handlers 570 *****************************************************************************/ 571 572 /** 573 * init_reserved - stub for various unknown/unused single-byte opcodes 574 * 575 */ 576 static void 577 init_reserved(struct nvbios_init *init) 578 { 579 u8 opcode = nvbios_rd08(init->bios, init->offset); 580 u8 length, i; 581 582 switch (opcode) { 583 case 0xaa: 584 length = 4; 585 break; 586 default: 587 length = 1; 588 break; 589 } 590 591 trace("RESERVED 0x%02x\t", opcode); 592 for (i = 1; i < length; i++) 593 cont(" 0x%02x", nvbios_rd08(init->bios, init->offset + i)); 594 cont("\n"); 595 init->offset += length; 596 } 597 598 /** 599 * INIT_DONE - opcode 0x71 600 * 601 */ 602 static void 603 init_done(struct nvbios_init *init) 604 { 605 trace("DONE\n"); 606 init->offset = 0x0000; 607 } 608 609 /** 610 * INIT_IO_RESTRICT_PROG - opcode 0x32 611 * 612 */ 613 static void 614 init_io_restrict_prog(struct nvbios_init *init) 615 { 616 struct nvkm_bios *bios = init->bios; 617 u16 port = nvbios_rd16(bios, init->offset + 1); 618 u8 index = nvbios_rd08(bios, init->offset + 3); 619 u8 mask = nvbios_rd08(bios, init->offset + 4); 620 u8 shift = nvbios_rd08(bios, init->offset + 5); 621 u8 count = nvbios_rd08(bios, init->offset + 6); 622 u32 reg = nvbios_rd32(bios, init->offset + 7); 623 u8 conf, i; 624 625 trace("IO_RESTRICT_PROG\tR[0x%06x] = " 626 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", 627 reg, port, index, mask, shift); 628 init->offset += 11; 629 630 conf = (init_rdvgai(init, port, index) & mask) >> shift; 631 for (i = 0; i < count; i++) { 632 u32 data = nvbios_rd32(bios, init->offset); 633 634 if (i == conf) { 635 trace("\t0x%08x *\n", data); 636 init_wr32(init, reg, data); 637 } else { 638 trace("\t0x%08x\n", data); 639 } 640 641 init->offset += 4; 642 } 643 trace("}]\n"); 644 } 645 646 /** 647 * INIT_REPEAT - opcode 0x33 648 * 649 */ 650 static void 651 init_repeat(struct nvbios_init *init) 652 { 653 struct nvkm_bios *bios = init->bios; 654 u8 count = nvbios_rd08(bios, init->offset + 1); 655 u16 repeat = init->repeat; 656 657 trace("REPEAT\t0x%02x\n", count); 658 init->offset += 2; 659 660 init->repeat = init->offset; 661 init->repend = init->offset; 662 while (count--) { 663 init->offset = init->repeat; 664 nvbios_exec(init); 665 if (count) 666 trace("REPEAT\t0x%02x\n", count); 667 } 668 init->offset = init->repend; 669 init->repeat = repeat; 670 } 671 672 /** 673 * INIT_IO_RESTRICT_PLL - opcode 0x34 674 * 675 */ 676 static void 677 init_io_restrict_pll(struct nvbios_init *init) 678 { 679 struct nvkm_bios *bios = init->bios; 680 u16 port = nvbios_rd16(bios, init->offset + 1); 681 u8 index = nvbios_rd08(bios, init->offset + 3); 682 u8 mask = nvbios_rd08(bios, init->offset + 4); 683 u8 shift = nvbios_rd08(bios, init->offset + 5); 684 s8 iofc = nvbios_rd08(bios, init->offset + 6); 685 u8 count = nvbios_rd08(bios, init->offset + 7); 686 u32 reg = nvbios_rd32(bios, init->offset + 8); 687 u8 conf, i; 688 689 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " 690 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", 691 reg, port, index, mask, shift, iofc); 692 init->offset += 12; 693 694 conf = (init_rdvgai(init, port, index) & mask) >> shift; 695 for (i = 0; i < count; i++) { 696 u32 freq = nvbios_rd16(bios, init->offset) * 10; 697 698 if (i == conf) { 699 trace("\t%dkHz *\n", freq); 700 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) 701 freq *= 2; 702 init_prog_pll(init, reg, freq); 703 } else { 704 trace("\t%dkHz\n", freq); 705 } 706 707 init->offset += 2; 708 } 709 trace("}]\n"); 710 } 711 712 /** 713 * INIT_END_REPEAT - opcode 0x36 714 * 715 */ 716 static void 717 init_end_repeat(struct nvbios_init *init) 718 { 719 trace("END_REPEAT\n"); 720 init->offset += 1; 721 722 if (init->repeat) { 723 init->repend = init->offset; 724 init->offset = 0; 725 } 726 } 727 728 /** 729 * INIT_COPY - opcode 0x37 730 * 731 */ 732 static void 733 init_copy(struct nvbios_init *init) 734 { 735 struct nvkm_bios *bios = init->bios; 736 u32 reg = nvbios_rd32(bios, init->offset + 1); 737 u8 shift = nvbios_rd08(bios, init->offset + 5); 738 u8 smask = nvbios_rd08(bios, init->offset + 6); 739 u16 port = nvbios_rd16(bios, init->offset + 7); 740 u8 index = nvbios_rd08(bios, init->offset + 9); 741 u8 mask = nvbios_rd08(bios, init->offset + 10); 742 u8 data; 743 744 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " 745 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", 746 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", 747 (shift & 0x80) ? (0x100 - shift) : shift, smask); 748 init->offset += 11; 749 750 data = init_rdvgai(init, port, index) & mask; 751 data |= init_shift(init_rd32(init, reg), shift) & smask; 752 init_wrvgai(init, port, index, data); 753 } 754 755 /** 756 * INIT_NOT - opcode 0x38 757 * 758 */ 759 static void 760 init_not(struct nvbios_init *init) 761 { 762 trace("NOT\n"); 763 init->offset += 1; 764 init_exec_inv(init); 765 } 766 767 /** 768 * INIT_IO_FLAG_CONDITION - opcode 0x39 769 * 770 */ 771 static void 772 init_io_flag_condition(struct nvbios_init *init) 773 { 774 struct nvkm_bios *bios = init->bios; 775 u8 cond = nvbios_rd08(bios, init->offset + 1); 776 777 trace("IO_FLAG_CONDITION\t0x%02x\n", cond); 778 init->offset += 2; 779 780 if (!init_io_flag_condition_met(init, cond)) 781 init_exec_set(init, false); 782 } 783 784 /** 785 * INIT_DP_CONDITION - opcode 0x3a 786 * 787 */ 788 static void 789 init_dp_condition(struct nvbios_init *init) 790 { 791 struct nvkm_bios *bios = init->bios; 792 struct nvbios_dpout info; 793 u8 cond = nvbios_rd08(bios, init->offset + 1); 794 u8 unkn = nvbios_rd08(bios, init->offset + 2); 795 u8 ver, hdr, cnt, len; 796 u16 data; 797 798 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn); 799 init->offset += 3; 800 801 switch (cond) { 802 case 0: 803 if (init_conn(init) != DCB_CONNECTOR_eDP) 804 init_exec_set(init, false); 805 break; 806 case 1: 807 case 2: 808 if ( init->outp && 809 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, 810 (init->outp->or << 0) | 811 (init->outp->sorconf.link << 6), 812 &ver, &hdr, &cnt, &len, &info))) 813 { 814 if (!(info.flags & cond)) 815 init_exec_set(init, false); 816 break; 817 } 818 819 if (init_exec(init)) 820 warn("script needs dp output table data\n"); 821 break; 822 case 5: 823 if (!(init_rdauxr(init, 0x0d) & 1)) 824 init_exec_set(init, false); 825 break; 826 default: 827 warn("unknown dp condition 0x%02x\n", cond); 828 break; 829 } 830 } 831 832 /** 833 * INIT_IO_MASK_OR - opcode 0x3b 834 * 835 */ 836 static void 837 init_io_mask_or(struct nvbios_init *init) 838 { 839 struct nvkm_bios *bios = init->bios; 840 u8 index = nvbios_rd08(bios, init->offset + 1); 841 u8 or = init_or(init); 842 u8 data; 843 844 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); 845 init->offset += 2; 846 847 data = init_rdvgai(init, 0x03d4, index); 848 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); 849 } 850 851 /** 852 * INIT_IO_OR - opcode 0x3c 853 * 854 */ 855 static void 856 init_io_or(struct nvbios_init *init) 857 { 858 struct nvkm_bios *bios = init->bios; 859 u8 index = nvbios_rd08(bios, init->offset + 1); 860 u8 or = init_or(init); 861 u8 data; 862 863 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); 864 init->offset += 2; 865 866 data = init_rdvgai(init, 0x03d4, index); 867 init_wrvgai(init, 0x03d4, index, data | (1 << or)); 868 } 869 870 /** 871 * INIT_ANDN_REG - opcode 0x47 872 * 873 */ 874 static void 875 init_andn_reg(struct nvbios_init *init) 876 { 877 struct nvkm_bios *bios = init->bios; 878 u32 reg = nvbios_rd32(bios, init->offset + 1); 879 u32 mask = nvbios_rd32(bios, init->offset + 5); 880 881 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); 882 init->offset += 9; 883 884 init_mask(init, reg, mask, 0); 885 } 886 887 /** 888 * INIT_OR_REG - opcode 0x48 889 * 890 */ 891 static void 892 init_or_reg(struct nvbios_init *init) 893 { 894 struct nvkm_bios *bios = init->bios; 895 u32 reg = nvbios_rd32(bios, init->offset + 1); 896 u32 mask = nvbios_rd32(bios, init->offset + 5); 897 898 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); 899 init->offset += 9; 900 901 init_mask(init, reg, 0, mask); 902 } 903 904 /** 905 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 906 * 907 */ 908 static void 909 init_idx_addr_latched(struct nvbios_init *init) 910 { 911 struct nvkm_bios *bios = init->bios; 912 u32 creg = nvbios_rd32(bios, init->offset + 1); 913 u32 dreg = nvbios_rd32(bios, init->offset + 5); 914 u32 mask = nvbios_rd32(bios, init->offset + 9); 915 u32 data = nvbios_rd32(bios, init->offset + 13); 916 u8 count = nvbios_rd08(bios, init->offset + 17); 917 918 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); 919 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); 920 init->offset += 18; 921 922 while (count--) { 923 u8 iaddr = nvbios_rd08(bios, init->offset + 0); 924 u8 idata = nvbios_rd08(bios, init->offset + 1); 925 926 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); 927 init->offset += 2; 928 929 init_wr32(init, dreg, idata); 930 init_mask(init, creg, ~mask, data | iaddr); 931 } 932 } 933 934 /** 935 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a 936 * 937 */ 938 static void 939 init_io_restrict_pll2(struct nvbios_init *init) 940 { 941 struct nvkm_bios *bios = init->bios; 942 u16 port = nvbios_rd16(bios, init->offset + 1); 943 u8 index = nvbios_rd08(bios, init->offset + 3); 944 u8 mask = nvbios_rd08(bios, init->offset + 4); 945 u8 shift = nvbios_rd08(bios, init->offset + 5); 946 u8 count = nvbios_rd08(bios, init->offset + 6); 947 u32 reg = nvbios_rd32(bios, init->offset + 7); 948 u8 conf, i; 949 950 trace("IO_RESTRICT_PLL2\t" 951 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", 952 reg, port, index, mask, shift); 953 init->offset += 11; 954 955 conf = (init_rdvgai(init, port, index) & mask) >> shift; 956 for (i = 0; i < count; i++) { 957 u32 freq = nvbios_rd32(bios, init->offset); 958 if (i == conf) { 959 trace("\t%dkHz *\n", freq); 960 init_prog_pll(init, reg, freq); 961 } else { 962 trace("\t%dkHz\n", freq); 963 } 964 init->offset += 4; 965 } 966 trace("}]\n"); 967 } 968 969 /** 970 * INIT_PLL2 - opcode 0x4b 971 * 972 */ 973 static void 974 init_pll2(struct nvbios_init *init) 975 { 976 struct nvkm_bios *bios = init->bios; 977 u32 reg = nvbios_rd32(bios, init->offset + 1); 978 u32 freq = nvbios_rd32(bios, init->offset + 5); 979 980 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 981 init->offset += 9; 982 983 init_prog_pll(init, reg, freq); 984 } 985 986 /** 987 * INIT_I2C_BYTE - opcode 0x4c 988 * 989 */ 990 static void 991 init_i2c_byte(struct nvbios_init *init) 992 { 993 struct nvkm_bios *bios = init->bios; 994 u8 index = nvbios_rd08(bios, init->offset + 1); 995 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 996 u8 count = nvbios_rd08(bios, init->offset + 3); 997 998 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 999 init->offset += 4; 1000 1001 while (count--) { 1002 u8 reg = nvbios_rd08(bios, init->offset + 0); 1003 u8 mask = nvbios_rd08(bios, init->offset + 1); 1004 u8 data = nvbios_rd08(bios, init->offset + 2); 1005 int val; 1006 1007 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); 1008 init->offset += 3; 1009 1010 val = init_rdi2cr(init, index, addr, reg); 1011 if (val < 0) 1012 continue; 1013 init_wri2cr(init, index, addr, reg, (val & mask) | data); 1014 } 1015 } 1016 1017 /** 1018 * INIT_ZM_I2C_BYTE - opcode 0x4d 1019 * 1020 */ 1021 static void 1022 init_zm_i2c_byte(struct nvbios_init *init) 1023 { 1024 struct nvkm_bios *bios = init->bios; 1025 u8 index = nvbios_rd08(bios, init->offset + 1); 1026 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1027 u8 count = nvbios_rd08(bios, init->offset + 3); 1028 1029 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1030 init->offset += 4; 1031 1032 while (count--) { 1033 u8 reg = nvbios_rd08(bios, init->offset + 0); 1034 u8 data = nvbios_rd08(bios, init->offset + 1); 1035 1036 trace("\t[0x%02x] = 0x%02x\n", reg, data); 1037 init->offset += 2; 1038 1039 init_wri2cr(init, index, addr, reg, data); 1040 } 1041 } 1042 1043 /** 1044 * INIT_ZM_I2C - opcode 0x4e 1045 * 1046 */ 1047 static void 1048 init_zm_i2c(struct nvbios_init *init) 1049 { 1050 struct nvkm_bios *bios = init->bios; 1051 u8 index = nvbios_rd08(bios, init->offset + 1); 1052 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1053 u8 count = nvbios_rd08(bios, init->offset + 3); 1054 u8 data[256], i; 1055 1056 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); 1057 init->offset += 4; 1058 1059 for (i = 0; i < count; i++) { 1060 data[i] = nvbios_rd08(bios, init->offset); 1061 trace("\t0x%02x\n", data[i]); 1062 init->offset++; 1063 } 1064 1065 if (init_exec(init)) { 1066 struct i2c_adapter *adap = init_i2c(init, index); 1067 struct i2c_msg msg = { 1068 .addr = addr, .flags = 0, .len = count, .buf = data, 1069 }; 1070 int ret; 1071 1072 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1) 1073 warn("i2c wr failed, %d\n", ret); 1074 } 1075 } 1076 1077 /** 1078 * INIT_TMDS - opcode 0x4f 1079 * 1080 */ 1081 static void 1082 init_tmds(struct nvbios_init *init) 1083 { 1084 struct nvkm_bios *bios = init->bios; 1085 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1086 u8 addr = nvbios_rd08(bios, init->offset + 2); 1087 u8 mask = nvbios_rd08(bios, init->offset + 3); 1088 u8 data = nvbios_rd08(bios, init->offset + 4); 1089 u32 reg = init_tmds_reg(init, tmds); 1090 1091 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", 1092 tmds, addr, mask, data); 1093 init->offset += 5; 1094 1095 if (reg == 0) 1096 return; 1097 1098 init_wr32(init, reg + 0, addr | 0x00010000); 1099 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); 1100 init_wr32(init, reg + 0, addr); 1101 } 1102 1103 /** 1104 * INIT_ZM_TMDS_GROUP - opcode 0x50 1105 * 1106 */ 1107 static void 1108 init_zm_tmds_group(struct nvbios_init *init) 1109 { 1110 struct nvkm_bios *bios = init->bios; 1111 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1112 u8 count = nvbios_rd08(bios, init->offset + 2); 1113 u32 reg = init_tmds_reg(init, tmds); 1114 1115 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); 1116 init->offset += 3; 1117 1118 while (count--) { 1119 u8 addr = nvbios_rd08(bios, init->offset + 0); 1120 u8 data = nvbios_rd08(bios, init->offset + 1); 1121 1122 trace("\t[0x%02x] = 0x%02x\n", addr, data); 1123 init->offset += 2; 1124 1125 init_wr32(init, reg + 4, data); 1126 init_wr32(init, reg + 0, addr); 1127 } 1128 } 1129 1130 /** 1131 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 1132 * 1133 */ 1134 static void 1135 init_cr_idx_adr_latch(struct nvbios_init *init) 1136 { 1137 struct nvkm_bios *bios = init->bios; 1138 u8 addr0 = nvbios_rd08(bios, init->offset + 1); 1139 u8 addr1 = nvbios_rd08(bios, init->offset + 2); 1140 u8 base = nvbios_rd08(bios, init->offset + 3); 1141 u8 count = nvbios_rd08(bios, init->offset + 4); 1142 u8 save0; 1143 1144 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); 1145 init->offset += 5; 1146 1147 save0 = init_rdvgai(init, 0x03d4, addr0); 1148 while (count--) { 1149 u8 data = nvbios_rd08(bios, init->offset); 1150 1151 trace("\t\t[0x%02x] = 0x%02x\n", base, data); 1152 init->offset += 1; 1153 1154 init_wrvgai(init, 0x03d4, addr0, base++); 1155 init_wrvgai(init, 0x03d4, addr1, data); 1156 } 1157 init_wrvgai(init, 0x03d4, addr0, save0); 1158 } 1159 1160 /** 1161 * INIT_CR - opcode 0x52 1162 * 1163 */ 1164 static void 1165 init_cr(struct nvbios_init *init) 1166 { 1167 struct nvkm_bios *bios = init->bios; 1168 u8 addr = nvbios_rd08(bios, init->offset + 1); 1169 u8 mask = nvbios_rd08(bios, init->offset + 2); 1170 u8 data = nvbios_rd08(bios, init->offset + 3); 1171 u8 val; 1172 1173 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 1174 init->offset += 4; 1175 1176 val = init_rdvgai(init, 0x03d4, addr) & mask; 1177 init_wrvgai(init, 0x03d4, addr, val | data); 1178 } 1179 1180 /** 1181 * INIT_ZM_CR - opcode 0x53 1182 * 1183 */ 1184 static void 1185 init_zm_cr(struct nvbios_init *init) 1186 { 1187 struct nvkm_bios *bios = init->bios; 1188 u8 addr = nvbios_rd08(bios, init->offset + 1); 1189 u8 data = nvbios_rd08(bios, init->offset + 2); 1190 1191 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); 1192 init->offset += 3; 1193 1194 init_wrvgai(init, 0x03d4, addr, data); 1195 } 1196 1197 /** 1198 * INIT_ZM_CR_GROUP - opcode 0x54 1199 * 1200 */ 1201 static void 1202 init_zm_cr_group(struct nvbios_init *init) 1203 { 1204 struct nvkm_bios *bios = init->bios; 1205 u8 count = nvbios_rd08(bios, init->offset + 1); 1206 1207 trace("ZM_CR_GROUP\n"); 1208 init->offset += 2; 1209 1210 while (count--) { 1211 u8 addr = nvbios_rd08(bios, init->offset + 0); 1212 u8 data = nvbios_rd08(bios, init->offset + 1); 1213 1214 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); 1215 init->offset += 2; 1216 1217 init_wrvgai(init, 0x03d4, addr, data); 1218 } 1219 } 1220 1221 /** 1222 * INIT_CONDITION_TIME - opcode 0x56 1223 * 1224 */ 1225 static void 1226 init_condition_time(struct nvbios_init *init) 1227 { 1228 struct nvkm_bios *bios = init->bios; 1229 u8 cond = nvbios_rd08(bios, init->offset + 1); 1230 u8 retry = nvbios_rd08(bios, init->offset + 2); 1231 u8 wait = min((u16)retry * 50, 100); 1232 1233 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); 1234 init->offset += 3; 1235 1236 if (!init_exec(init)) 1237 return; 1238 1239 while (wait--) { 1240 if (init_condition_met(init, cond)) 1241 return; 1242 mdelay(20); 1243 } 1244 1245 init_exec_set(init, false); 1246 } 1247 1248 /** 1249 * INIT_LTIME - opcode 0x57 1250 * 1251 */ 1252 static void 1253 init_ltime(struct nvbios_init *init) 1254 { 1255 struct nvkm_bios *bios = init->bios; 1256 u16 msec = nvbios_rd16(bios, init->offset + 1); 1257 1258 trace("LTIME\t0x%04x\n", msec); 1259 init->offset += 3; 1260 1261 if (init_exec(init)) 1262 mdelay(msec); 1263 } 1264 1265 /** 1266 * INIT_ZM_REG_SEQUENCE - opcode 0x58 1267 * 1268 */ 1269 static void 1270 init_zm_reg_sequence(struct nvbios_init *init) 1271 { 1272 struct nvkm_bios *bios = init->bios; 1273 u32 base = nvbios_rd32(bios, init->offset + 1); 1274 u8 count = nvbios_rd08(bios, init->offset + 5); 1275 1276 trace("ZM_REG_SEQUENCE\t0x%02x\n", count); 1277 init->offset += 6; 1278 1279 while (count--) { 1280 u32 data = nvbios_rd32(bios, init->offset); 1281 1282 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); 1283 init->offset += 4; 1284 1285 init_wr32(init, base, data); 1286 base += 4; 1287 } 1288 } 1289 1290 /** 1291 * INIT_PLL_INDIRECT - opcode 0x59 1292 * 1293 */ 1294 static void 1295 init_pll_indirect(struct nvbios_init *init) 1296 { 1297 struct nvkm_bios *bios = init->bios; 1298 u32 reg = nvbios_rd32(bios, init->offset + 1); 1299 u16 addr = nvbios_rd16(bios, init->offset + 5); 1300 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000; 1301 1302 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", 1303 reg, addr, freq); 1304 init->offset += 7; 1305 1306 init_prog_pll(init, reg, freq); 1307 } 1308 1309 /** 1310 * INIT_ZM_REG_INDIRECT - opcode 0x5a 1311 * 1312 */ 1313 static void 1314 init_zm_reg_indirect(struct nvbios_init *init) 1315 { 1316 struct nvkm_bios *bios = init->bios; 1317 u32 reg = nvbios_rd32(bios, init->offset + 1); 1318 u16 addr = nvbios_rd16(bios, init->offset + 5); 1319 u32 data = nvbios_rd32(bios, addr); 1320 1321 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", 1322 reg, addr, data); 1323 init->offset += 7; 1324 1325 init_wr32(init, addr, data); 1326 } 1327 1328 /** 1329 * INIT_SUB_DIRECT - opcode 0x5b 1330 * 1331 */ 1332 static void 1333 init_sub_direct(struct nvbios_init *init) 1334 { 1335 struct nvkm_bios *bios = init->bios; 1336 u16 addr = nvbios_rd16(bios, init->offset + 1); 1337 u16 save; 1338 1339 trace("SUB_DIRECT\t0x%04x\n", addr); 1340 1341 if (init_exec(init)) { 1342 save = init->offset; 1343 init->offset = addr; 1344 if (nvbios_exec(init)) { 1345 error("error parsing sub-table\n"); 1346 return; 1347 } 1348 init->offset = save; 1349 } 1350 1351 init->offset += 3; 1352 } 1353 1354 /** 1355 * INIT_JUMP - opcode 0x5c 1356 * 1357 */ 1358 static void 1359 init_jump(struct nvbios_init *init) 1360 { 1361 struct nvkm_bios *bios = init->bios; 1362 u16 offset = nvbios_rd16(bios, init->offset + 1); 1363 1364 trace("JUMP\t0x%04x\n", offset); 1365 1366 if (init_exec(init)) 1367 init->offset = offset; 1368 else 1369 init->offset += 3; 1370 } 1371 1372 /** 1373 * INIT_I2C_IF - opcode 0x5e 1374 * 1375 */ 1376 static void 1377 init_i2c_if(struct nvbios_init *init) 1378 { 1379 struct nvkm_bios *bios = init->bios; 1380 u8 index = nvbios_rd08(bios, init->offset + 1); 1381 u8 addr = nvbios_rd08(bios, init->offset + 2); 1382 u8 reg = nvbios_rd08(bios, init->offset + 3); 1383 u8 mask = nvbios_rd08(bios, init->offset + 4); 1384 u8 data = nvbios_rd08(bios, init->offset + 5); 1385 u8 value; 1386 1387 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", 1388 index, addr, reg, mask, data); 1389 init->offset += 6; 1390 init_exec_force(init, true); 1391 1392 value = init_rdi2cr(init, index, addr, reg); 1393 if ((value & mask) != data) 1394 init_exec_set(init, false); 1395 1396 init_exec_force(init, false); 1397 } 1398 1399 /** 1400 * INIT_COPY_NV_REG - opcode 0x5f 1401 * 1402 */ 1403 static void 1404 init_copy_nv_reg(struct nvbios_init *init) 1405 { 1406 struct nvkm_bios *bios = init->bios; 1407 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1408 u8 shift = nvbios_rd08(bios, init->offset + 5); 1409 u32 smask = nvbios_rd32(bios, init->offset + 6); 1410 u32 sxor = nvbios_rd32(bios, init->offset + 10); 1411 u32 dreg = nvbios_rd32(bios, init->offset + 14); 1412 u32 dmask = nvbios_rd32(bios, init->offset + 18); 1413 u32 data; 1414 1415 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " 1416 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", 1417 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", 1418 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); 1419 init->offset += 22; 1420 1421 data = init_shift(init_rd32(init, sreg), shift); 1422 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); 1423 } 1424 1425 /** 1426 * INIT_ZM_INDEX_IO - opcode 0x62 1427 * 1428 */ 1429 static void 1430 init_zm_index_io(struct nvbios_init *init) 1431 { 1432 struct nvkm_bios *bios = init->bios; 1433 u16 port = nvbios_rd16(bios, init->offset + 1); 1434 u8 index = nvbios_rd08(bios, init->offset + 3); 1435 u8 data = nvbios_rd08(bios, init->offset + 4); 1436 1437 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); 1438 init->offset += 5; 1439 1440 init_wrvgai(init, port, index, data); 1441 } 1442 1443 /** 1444 * INIT_COMPUTE_MEM - opcode 0x63 1445 * 1446 */ 1447 static void 1448 init_compute_mem(struct nvbios_init *init) 1449 { 1450 struct nvkm_devinit *devinit = nvkm_devinit(init->bios); 1451 1452 trace("COMPUTE_MEM\n"); 1453 init->offset += 1; 1454 1455 init_exec_force(init, true); 1456 if (init_exec(init) && devinit->meminit) 1457 devinit->meminit(devinit); 1458 init_exec_force(init, false); 1459 } 1460 1461 /** 1462 * INIT_RESET - opcode 0x65 1463 * 1464 */ 1465 static void 1466 init_reset(struct nvbios_init *init) 1467 { 1468 struct nvkm_bios *bios = init->bios; 1469 u32 reg = nvbios_rd32(bios, init->offset + 1); 1470 u32 data1 = nvbios_rd32(bios, init->offset + 5); 1471 u32 data2 = nvbios_rd32(bios, init->offset + 9); 1472 u32 savepci19; 1473 1474 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); 1475 init->offset += 13; 1476 init_exec_force(init, true); 1477 1478 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); 1479 init_wr32(init, reg, data1); 1480 udelay(10); 1481 init_wr32(init, reg, data2); 1482 init_wr32(init, 0x00184c, savepci19); 1483 init_mask(init, 0x001850, 0x00000001, 0x00000000); 1484 1485 init_exec_force(init, false); 1486 } 1487 1488 /** 1489 * INIT_CONFIGURE_MEM - opcode 0x66 1490 * 1491 */ 1492 static u16 1493 init_configure_mem_clk(struct nvbios_init *init) 1494 { 1495 u16 mdata = bmp_mem_init_table(init->bios); 1496 if (mdata) 1497 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; 1498 return mdata; 1499 } 1500 1501 static void 1502 init_configure_mem(struct nvbios_init *init) 1503 { 1504 struct nvkm_bios *bios = init->bios; 1505 u16 mdata, sdata; 1506 u32 addr, data; 1507 1508 trace("CONFIGURE_MEM\n"); 1509 init->offset += 1; 1510 1511 if (bios->version.major > 2) { 1512 init_done(init); 1513 return; 1514 } 1515 init_exec_force(init, true); 1516 1517 mdata = init_configure_mem_clk(init); 1518 sdata = bmp_sdr_seq_table(bios); 1519 if (nvbios_rd08(bios, mdata) & 0x01) 1520 sdata = bmp_ddr_seq_table(bios); 1521 mdata += 6; /* skip to data */ 1522 1523 data = init_rdvgai(init, 0x03c4, 0x01); 1524 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); 1525 1526 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) { 1527 switch (addr) { 1528 case 0x10021c: /* CKE_NORMAL */ 1529 case 0x1002d0: /* CMD_REFRESH */ 1530 case 0x1002d4: /* CMD_PRECHARGE */ 1531 data = 0x00000001; 1532 break; 1533 default: 1534 data = nvbios_rd32(bios, mdata); 1535 mdata += 4; 1536 if (data == 0xffffffff) 1537 continue; 1538 break; 1539 } 1540 1541 init_wr32(init, addr, data); 1542 } 1543 1544 init_exec_force(init, false); 1545 } 1546 1547 /** 1548 * INIT_CONFIGURE_CLK - opcode 0x67 1549 * 1550 */ 1551 static void 1552 init_configure_clk(struct nvbios_init *init) 1553 { 1554 struct nvkm_bios *bios = init->bios; 1555 u16 mdata, clock; 1556 1557 trace("CONFIGURE_CLK\n"); 1558 init->offset += 1; 1559 1560 if (bios->version.major > 2) { 1561 init_done(init); 1562 return; 1563 } 1564 init_exec_force(init, true); 1565 1566 mdata = init_configure_mem_clk(init); 1567 1568 /* NVPLL */ 1569 clock = nvbios_rd16(bios, mdata + 4) * 10; 1570 init_prog_pll(init, 0x680500, clock); 1571 1572 /* MPLL */ 1573 clock = nvbios_rd16(bios, mdata + 2) * 10; 1574 if (nvbios_rd08(bios, mdata) & 0x01) 1575 clock *= 2; 1576 init_prog_pll(init, 0x680504, clock); 1577 1578 init_exec_force(init, false); 1579 } 1580 1581 /** 1582 * INIT_CONFIGURE_PREINIT - opcode 0x68 1583 * 1584 */ 1585 static void 1586 init_configure_preinit(struct nvbios_init *init) 1587 { 1588 struct nvkm_bios *bios = init->bios; 1589 u32 strap; 1590 1591 trace("CONFIGURE_PREINIT\n"); 1592 init->offset += 1; 1593 1594 if (bios->version.major > 2) { 1595 init_done(init); 1596 return; 1597 } 1598 init_exec_force(init, true); 1599 1600 strap = init_rd32(init, 0x101000); 1601 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); 1602 init_wrvgai(init, 0x03d4, 0x3c, strap); 1603 1604 init_exec_force(init, false); 1605 } 1606 1607 /** 1608 * INIT_IO - opcode 0x69 1609 * 1610 */ 1611 static void 1612 init_io(struct nvbios_init *init) 1613 { 1614 struct nvkm_bios *bios = init->bios; 1615 u16 port = nvbios_rd16(bios, init->offset + 1); 1616 u8 mask = nvbios_rd16(bios, init->offset + 3); 1617 u8 data = nvbios_rd16(bios, init->offset + 4); 1618 u8 value; 1619 1620 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); 1621 init->offset += 5; 1622 1623 /* ummm.. yes.. should really figure out wtf this is and why it's 1624 * needed some day.. it's almost certainly wrong, but, it also 1625 * somehow makes things work... 1626 */ 1627 if (nv_device(init->bios)->card_type >= NV_50 && 1628 port == 0x03c3 && data == 0x01) { 1629 init_mask(init, 0x614100, 0xf0800000, 0x00800000); 1630 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); 1631 init_mask(init, 0x614900, 0xf0800000, 0x00800000); 1632 init_mask(init, 0x000200, 0x40000000, 0x00000000); 1633 mdelay(10); 1634 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); 1635 init_mask(init, 0x000200, 0x40000000, 0x40000000); 1636 init_wr32(init, 0x614100, 0x00800018); 1637 init_wr32(init, 0x614900, 0x00800018); 1638 mdelay(10); 1639 init_wr32(init, 0x614100, 0x10000018); 1640 init_wr32(init, 0x614900, 0x10000018); 1641 } 1642 1643 value = init_rdport(init, port) & mask; 1644 init_wrport(init, port, data | value); 1645 } 1646 1647 /** 1648 * INIT_SUB - opcode 0x6b 1649 * 1650 */ 1651 static void 1652 init_sub(struct nvbios_init *init) 1653 { 1654 struct nvkm_bios *bios = init->bios; 1655 u8 index = nvbios_rd08(bios, init->offset + 1); 1656 u16 addr, save; 1657 1658 trace("SUB\t0x%02x\n", index); 1659 1660 addr = init_script(bios, index); 1661 if (addr && init_exec(init)) { 1662 save = init->offset; 1663 init->offset = addr; 1664 if (nvbios_exec(init)) { 1665 error("error parsing sub-table\n"); 1666 return; 1667 } 1668 init->offset = save; 1669 } 1670 1671 init->offset += 2; 1672 } 1673 1674 /** 1675 * INIT_RAM_CONDITION - opcode 0x6d 1676 * 1677 */ 1678 static void 1679 init_ram_condition(struct nvbios_init *init) 1680 { 1681 struct nvkm_bios *bios = init->bios; 1682 u8 mask = nvbios_rd08(bios, init->offset + 1); 1683 u8 value = nvbios_rd08(bios, init->offset + 2); 1684 1685 trace("RAM_CONDITION\t" 1686 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); 1687 init->offset += 3; 1688 1689 if ((init_rd32(init, 0x100000) & mask) != value) 1690 init_exec_set(init, false); 1691 } 1692 1693 /** 1694 * INIT_NV_REG - opcode 0x6e 1695 * 1696 */ 1697 static void 1698 init_nv_reg(struct nvbios_init *init) 1699 { 1700 struct nvkm_bios *bios = init->bios; 1701 u32 reg = nvbios_rd32(bios, init->offset + 1); 1702 u32 mask = nvbios_rd32(bios, init->offset + 5); 1703 u32 data = nvbios_rd32(bios, init->offset + 9); 1704 1705 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); 1706 init->offset += 13; 1707 1708 init_mask(init, reg, ~mask, data); 1709 } 1710 1711 /** 1712 * INIT_MACRO - opcode 0x6f 1713 * 1714 */ 1715 static void 1716 init_macro(struct nvbios_init *init) 1717 { 1718 struct nvkm_bios *bios = init->bios; 1719 u8 macro = nvbios_rd08(bios, init->offset + 1); 1720 u16 table; 1721 1722 trace("MACRO\t0x%02x\n", macro); 1723 1724 table = init_macro_table(init); 1725 if (table) { 1726 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0); 1727 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4); 1728 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); 1729 init_wr32(init, addr, data); 1730 } 1731 1732 init->offset += 2; 1733 } 1734 1735 /** 1736 * INIT_RESUME - opcode 0x72 1737 * 1738 */ 1739 static void 1740 init_resume(struct nvbios_init *init) 1741 { 1742 trace("RESUME\n"); 1743 init->offset += 1; 1744 init_exec_set(init, true); 1745 } 1746 1747 /** 1748 * INIT_STRAP_CONDITION - opcode 0x73 1749 * 1750 */ 1751 static void 1752 init_strap_condition(struct nvbios_init *init) 1753 { 1754 struct nvkm_bios *bios = init->bios; 1755 u32 mask = nvbios_rd32(bios, init->offset + 1); 1756 u32 value = nvbios_rd32(bios, init->offset + 5); 1757 1758 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); 1759 init->offset += 9; 1760 1761 if ((init_rd32(init, 0x101000) & mask) != value) 1762 init_exec_set(init, false); 1763 } 1764 1765 /** 1766 * INIT_TIME - opcode 0x74 1767 * 1768 */ 1769 static void 1770 init_time(struct nvbios_init *init) 1771 { 1772 struct nvkm_bios *bios = init->bios; 1773 u16 usec = nvbios_rd16(bios, init->offset + 1); 1774 1775 trace("TIME\t0x%04x\n", usec); 1776 init->offset += 3; 1777 1778 if (init_exec(init)) { 1779 if (usec < 1000) 1780 udelay(usec); 1781 else 1782 mdelay((usec + 900) / 1000); 1783 } 1784 } 1785 1786 /** 1787 * INIT_CONDITION - opcode 0x75 1788 * 1789 */ 1790 static void 1791 init_condition(struct nvbios_init *init) 1792 { 1793 struct nvkm_bios *bios = init->bios; 1794 u8 cond = nvbios_rd08(bios, init->offset + 1); 1795 1796 trace("CONDITION\t0x%02x\n", cond); 1797 init->offset += 2; 1798 1799 if (!init_condition_met(init, cond)) 1800 init_exec_set(init, false); 1801 } 1802 1803 /** 1804 * INIT_IO_CONDITION - opcode 0x76 1805 * 1806 */ 1807 static void 1808 init_io_condition(struct nvbios_init *init) 1809 { 1810 struct nvkm_bios *bios = init->bios; 1811 u8 cond = nvbios_rd08(bios, init->offset + 1); 1812 1813 trace("IO_CONDITION\t0x%02x\n", cond); 1814 init->offset += 2; 1815 1816 if (!init_io_condition_met(init, cond)) 1817 init_exec_set(init, false); 1818 } 1819 1820 /** 1821 * INIT_ZM_REG16 - opcode 0x77 1822 * 1823 */ 1824 static void 1825 init_zm_reg16(struct nvbios_init *init) 1826 { 1827 struct nvkm_bios *bios = init->bios; 1828 u32 addr = nvbios_rd32(bios, init->offset + 1); 1829 u16 data = nvbios_rd16(bios, init->offset + 5); 1830 1831 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); 1832 init->offset += 7; 1833 1834 init_wr32(init, addr, data); 1835 } 1836 1837 /** 1838 * INIT_INDEX_IO - opcode 0x78 1839 * 1840 */ 1841 static void 1842 init_index_io(struct nvbios_init *init) 1843 { 1844 struct nvkm_bios *bios = init->bios; 1845 u16 port = nvbios_rd16(bios, init->offset + 1); 1846 u8 index = nvbios_rd16(bios, init->offset + 3); 1847 u8 mask = nvbios_rd08(bios, init->offset + 4); 1848 u8 data = nvbios_rd08(bios, init->offset + 5); 1849 u8 value; 1850 1851 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", 1852 port, index, mask, data); 1853 init->offset += 6; 1854 1855 value = init_rdvgai(init, port, index) & mask; 1856 init_wrvgai(init, port, index, data | value); 1857 } 1858 1859 /** 1860 * INIT_PLL - opcode 0x79 1861 * 1862 */ 1863 static void 1864 init_pll(struct nvbios_init *init) 1865 { 1866 struct nvkm_bios *bios = init->bios; 1867 u32 reg = nvbios_rd32(bios, init->offset + 1); 1868 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10; 1869 1870 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 1871 init->offset += 7; 1872 1873 init_prog_pll(init, reg, freq); 1874 } 1875 1876 /** 1877 * INIT_ZM_REG - opcode 0x7a 1878 * 1879 */ 1880 static void 1881 init_zm_reg(struct nvbios_init *init) 1882 { 1883 struct nvkm_bios *bios = init->bios; 1884 u32 addr = nvbios_rd32(bios, init->offset + 1); 1885 u32 data = nvbios_rd32(bios, init->offset + 5); 1886 1887 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); 1888 init->offset += 9; 1889 1890 if (addr == 0x000200) 1891 data |= 0x00000001; 1892 1893 init_wr32(init, addr, data); 1894 } 1895 1896 /** 1897 * INIT_RAM_RESTRICT_PLL - opcde 0x87 1898 * 1899 */ 1900 static void 1901 init_ram_restrict_pll(struct nvbios_init *init) 1902 { 1903 struct nvkm_bios *bios = init->bios; 1904 u8 type = nvbios_rd08(bios, init->offset + 1); 1905 u8 count = init_ram_restrict_group_count(init); 1906 u8 strap = init_ram_restrict(init); 1907 u8 cconf; 1908 1909 trace("RAM_RESTRICT_PLL\t0x%02x\n", type); 1910 init->offset += 2; 1911 1912 for (cconf = 0; cconf < count; cconf++) { 1913 u32 freq = nvbios_rd32(bios, init->offset); 1914 1915 if (cconf == strap) { 1916 trace("%dkHz *\n", freq); 1917 init_prog_pll(init, type, freq); 1918 } else { 1919 trace("%dkHz\n", freq); 1920 } 1921 1922 init->offset += 4; 1923 } 1924 } 1925 1926 /** 1927 * INIT_GPIO - opcode 0x8e 1928 * 1929 */ 1930 static void 1931 init_gpio(struct nvbios_init *init) 1932 { 1933 struct nvkm_gpio *gpio = nvkm_gpio(init->bios); 1934 1935 trace("GPIO\n"); 1936 init->offset += 1; 1937 1938 if (init_exec(init) && gpio && gpio->reset) 1939 gpio->reset(gpio, DCB_GPIO_UNUSED); 1940 } 1941 1942 /** 1943 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f 1944 * 1945 */ 1946 static void 1947 init_ram_restrict_zm_reg_group(struct nvbios_init *init) 1948 { 1949 struct nvkm_bios *bios = init->bios; 1950 u32 addr = nvbios_rd32(bios, init->offset + 1); 1951 u8 incr = nvbios_rd08(bios, init->offset + 5); 1952 u8 num = nvbios_rd08(bios, init->offset + 6); 1953 u8 count = init_ram_restrict_group_count(init); 1954 u8 index = init_ram_restrict(init); 1955 u8 i, j; 1956 1957 trace("RAM_RESTRICT_ZM_REG_GROUP\t" 1958 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); 1959 init->offset += 7; 1960 1961 for (i = 0; i < num; i++) { 1962 trace("\tR[0x%06x] = {\n", addr); 1963 for (j = 0; j < count; j++) { 1964 u32 data = nvbios_rd32(bios, init->offset); 1965 1966 if (j == index) { 1967 trace("\t\t0x%08x *\n", data); 1968 init_wr32(init, addr, data); 1969 } else { 1970 trace("\t\t0x%08x\n", data); 1971 } 1972 1973 init->offset += 4; 1974 } 1975 trace("\t}\n"); 1976 addr += incr; 1977 } 1978 } 1979 1980 /** 1981 * INIT_COPY_ZM_REG - opcode 0x90 1982 * 1983 */ 1984 static void 1985 init_copy_zm_reg(struct nvbios_init *init) 1986 { 1987 struct nvkm_bios *bios = init->bios; 1988 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1989 u32 dreg = nvbios_rd32(bios, init->offset + 5); 1990 1991 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); 1992 init->offset += 9; 1993 1994 init_wr32(init, dreg, init_rd32(init, sreg)); 1995 } 1996 1997 /** 1998 * INIT_ZM_REG_GROUP - opcode 0x91 1999 * 2000 */ 2001 static void 2002 init_zm_reg_group(struct nvbios_init *init) 2003 { 2004 struct nvkm_bios *bios = init->bios; 2005 u32 addr = nvbios_rd32(bios, init->offset + 1); 2006 u8 count = nvbios_rd08(bios, init->offset + 5); 2007 2008 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); 2009 init->offset += 6; 2010 2011 while (count--) { 2012 u32 data = nvbios_rd32(bios, init->offset); 2013 trace("\t0x%08x\n", data); 2014 init_wr32(init, addr, data); 2015 init->offset += 4; 2016 } 2017 } 2018 2019 /** 2020 * INIT_XLAT - opcode 0x96 2021 * 2022 */ 2023 static void 2024 init_xlat(struct nvbios_init *init) 2025 { 2026 struct nvkm_bios *bios = init->bios; 2027 u32 saddr = nvbios_rd32(bios, init->offset + 1); 2028 u8 sshift = nvbios_rd08(bios, init->offset + 5); 2029 u8 smask = nvbios_rd08(bios, init->offset + 6); 2030 u8 index = nvbios_rd08(bios, init->offset + 7); 2031 u32 daddr = nvbios_rd32(bios, init->offset + 8); 2032 u32 dmask = nvbios_rd32(bios, init->offset + 12); 2033 u8 shift = nvbios_rd08(bios, init->offset + 16); 2034 u32 data; 2035 2036 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " 2037 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", 2038 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", 2039 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); 2040 init->offset += 17; 2041 2042 data = init_shift(init_rd32(init, saddr), sshift) & smask; 2043 data = init_xlat_(init, index, data) << shift; 2044 init_mask(init, daddr, ~dmask, data); 2045 } 2046 2047 /** 2048 * INIT_ZM_MASK_ADD - opcode 0x97 2049 * 2050 */ 2051 static void 2052 init_zm_mask_add(struct nvbios_init *init) 2053 { 2054 struct nvkm_bios *bios = init->bios; 2055 u32 addr = nvbios_rd32(bios, init->offset + 1); 2056 u32 mask = nvbios_rd32(bios, init->offset + 5); 2057 u32 add = nvbios_rd32(bios, init->offset + 9); 2058 u32 data; 2059 2060 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 2061 init->offset += 13; 2062 2063 data = init_rd32(init, addr); 2064 data = (data & mask) | ((data + add) & ~mask); 2065 init_wr32(init, addr, data); 2066 } 2067 2068 /** 2069 * INIT_AUXCH - opcode 0x98 2070 * 2071 */ 2072 static void 2073 init_auxch(struct nvbios_init *init) 2074 { 2075 struct nvkm_bios *bios = init->bios; 2076 u32 addr = nvbios_rd32(bios, init->offset + 1); 2077 u8 count = nvbios_rd08(bios, init->offset + 5); 2078 2079 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2080 init->offset += 6; 2081 2082 while (count--) { 2083 u8 mask = nvbios_rd08(bios, init->offset + 0); 2084 u8 data = nvbios_rd08(bios, init->offset + 1); 2085 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 2086 mask = init_rdauxr(init, addr) & mask; 2087 init_wrauxr(init, addr, mask | data); 2088 init->offset += 2; 2089 } 2090 } 2091 2092 /** 2093 * INIT_AUXCH - opcode 0x99 2094 * 2095 */ 2096 static void 2097 init_zm_auxch(struct nvbios_init *init) 2098 { 2099 struct nvkm_bios *bios = init->bios; 2100 u32 addr = nvbios_rd32(bios, init->offset + 1); 2101 u8 count = nvbios_rd08(bios, init->offset + 5); 2102 2103 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2104 init->offset += 6; 2105 2106 while (count--) { 2107 u8 data = nvbios_rd08(bios, init->offset + 0); 2108 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); 2109 init_wrauxr(init, addr, data); 2110 init->offset += 1; 2111 } 2112 } 2113 2114 /** 2115 * INIT_I2C_LONG_IF - opcode 0x9a 2116 * 2117 */ 2118 static void 2119 init_i2c_long_if(struct nvbios_init *init) 2120 { 2121 struct nvkm_bios *bios = init->bios; 2122 u8 index = nvbios_rd08(bios, init->offset + 1); 2123 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 2124 u8 reglo = nvbios_rd08(bios, init->offset + 3); 2125 u8 reghi = nvbios_rd08(bios, init->offset + 4); 2126 u8 mask = nvbios_rd08(bios, init->offset + 5); 2127 u8 data = nvbios_rd08(bios, init->offset + 6); 2128 struct i2c_adapter *adap; 2129 2130 trace("I2C_LONG_IF\t" 2131 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", 2132 index, addr, reglo, reghi, mask, data); 2133 init->offset += 7; 2134 2135 adap = init_i2c(init, index); 2136 if (adap) { 2137 u8 i[2] = { reghi, reglo }; 2138 u8 o[1] = {}; 2139 struct i2c_msg msg[] = { 2140 { .addr = addr, .flags = 0, .len = 2, .buf = i }, 2141 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } 2142 }; 2143 int ret; 2144 2145 ret = i2c_transfer(adap, msg, 2); 2146 if (ret == 2 && ((o[0] & mask) == data)) 2147 return; 2148 } 2149 2150 init_exec_set(init, false); 2151 } 2152 2153 /** 2154 * INIT_GPIO_NE - opcode 0xa9 2155 * 2156 */ 2157 static void 2158 init_gpio_ne(struct nvbios_init *init) 2159 { 2160 struct nvkm_bios *bios = init->bios; 2161 struct nvkm_gpio *gpio = nvkm_gpio(bios); 2162 struct dcb_gpio_func func; 2163 u8 count = nvbios_rd08(bios, init->offset + 1); 2164 u8 idx = 0, ver, len; 2165 u16 data, i; 2166 2167 trace("GPIO_NE\t"); 2168 init->offset += 2; 2169 2170 for (i = init->offset; i < init->offset + count; i++) 2171 cont("0x%02x ", nvbios_rd08(bios, i)); 2172 cont("\n"); 2173 2174 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { 2175 if (func.func != DCB_GPIO_UNUSED) { 2176 for (i = init->offset; i < init->offset + count; i++) { 2177 if (func.func == nvbios_rd08(bios, i)) 2178 break; 2179 } 2180 2181 trace("\tFUNC[0x%02x]", func.func); 2182 if (i == (init->offset + count)) { 2183 cont(" *"); 2184 if (init_exec(init) && gpio && gpio->reset) 2185 gpio->reset(gpio, func.func); 2186 } 2187 cont("\n"); 2188 } 2189 } 2190 2191 init->offset += count; 2192 } 2193 2194 static struct nvbios_init_opcode { 2195 void (*exec)(struct nvbios_init *); 2196 } init_opcode[] = { 2197 [0x32] = { init_io_restrict_prog }, 2198 [0x33] = { init_repeat }, 2199 [0x34] = { init_io_restrict_pll }, 2200 [0x36] = { init_end_repeat }, 2201 [0x37] = { init_copy }, 2202 [0x38] = { init_not }, 2203 [0x39] = { init_io_flag_condition }, 2204 [0x3a] = { init_dp_condition }, 2205 [0x3b] = { init_io_mask_or }, 2206 [0x3c] = { init_io_or }, 2207 [0x47] = { init_andn_reg }, 2208 [0x48] = { init_or_reg }, 2209 [0x49] = { init_idx_addr_latched }, 2210 [0x4a] = { init_io_restrict_pll2 }, 2211 [0x4b] = { init_pll2 }, 2212 [0x4c] = { init_i2c_byte }, 2213 [0x4d] = { init_zm_i2c_byte }, 2214 [0x4e] = { init_zm_i2c }, 2215 [0x4f] = { init_tmds }, 2216 [0x50] = { init_zm_tmds_group }, 2217 [0x51] = { init_cr_idx_adr_latch }, 2218 [0x52] = { init_cr }, 2219 [0x53] = { init_zm_cr }, 2220 [0x54] = { init_zm_cr_group }, 2221 [0x56] = { init_condition_time }, 2222 [0x57] = { init_ltime }, 2223 [0x58] = { init_zm_reg_sequence }, 2224 [0x59] = { init_pll_indirect }, 2225 [0x5a] = { init_zm_reg_indirect }, 2226 [0x5b] = { init_sub_direct }, 2227 [0x5c] = { init_jump }, 2228 [0x5e] = { init_i2c_if }, 2229 [0x5f] = { init_copy_nv_reg }, 2230 [0x62] = { init_zm_index_io }, 2231 [0x63] = { init_compute_mem }, 2232 [0x65] = { init_reset }, 2233 [0x66] = { init_configure_mem }, 2234 [0x67] = { init_configure_clk }, 2235 [0x68] = { init_configure_preinit }, 2236 [0x69] = { init_io }, 2237 [0x6b] = { init_sub }, 2238 [0x6d] = { init_ram_condition }, 2239 [0x6e] = { init_nv_reg }, 2240 [0x6f] = { init_macro }, 2241 [0x71] = { init_done }, 2242 [0x72] = { init_resume }, 2243 [0x73] = { init_strap_condition }, 2244 [0x74] = { init_time }, 2245 [0x75] = { init_condition }, 2246 [0x76] = { init_io_condition }, 2247 [0x77] = { init_zm_reg16 }, 2248 [0x78] = { init_index_io }, 2249 [0x79] = { init_pll }, 2250 [0x7a] = { init_zm_reg }, 2251 [0x87] = { init_ram_restrict_pll }, 2252 [0x8c] = { init_reserved }, 2253 [0x8d] = { init_reserved }, 2254 [0x8e] = { init_gpio }, 2255 [0x8f] = { init_ram_restrict_zm_reg_group }, 2256 [0x90] = { init_copy_zm_reg }, 2257 [0x91] = { init_zm_reg_group }, 2258 [0x92] = { init_reserved }, 2259 [0x96] = { init_xlat }, 2260 [0x97] = { init_zm_mask_add }, 2261 [0x98] = { init_auxch }, 2262 [0x99] = { init_zm_auxch }, 2263 [0x9a] = { init_i2c_long_if }, 2264 [0xa9] = { init_gpio_ne }, 2265 [0xaa] = { init_reserved }, 2266 }; 2267 2268 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) 2269 2270 int 2271 nvbios_exec(struct nvbios_init *init) 2272 { 2273 init->nested++; 2274 while (init->offset) { 2275 u8 opcode = nvbios_rd08(init->bios, init->offset); 2276 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { 2277 error("unknown opcode 0x%02x\n", opcode); 2278 return -EINVAL; 2279 } 2280 2281 init_opcode[opcode].exec(init); 2282 } 2283 init->nested--; 2284 return 0; 2285 } 2286 2287 int 2288 nvbios_init(struct nvkm_subdev *subdev, bool execute) 2289 { 2290 struct nvkm_bios *bios = nvkm_bios(subdev); 2291 int ret = 0; 2292 int i = -1; 2293 u16 data; 2294 2295 if (execute) 2296 nvkm_debug(subdev, "running init tables\n"); 2297 while (!ret && (data = (init_script(bios, ++i)))) { 2298 struct nvbios_init init = { 2299 .subdev = subdev, 2300 .bios = bios, 2301 .offset = data, 2302 .outp = NULL, 2303 .crtc = -1, 2304 .execute = execute ? 1 : 0, 2305 }; 2306 2307 ret = nvbios_exec(&init); 2308 } 2309 2310 /* the vbios parser will run this right after the normal init 2311 * tables, whereas the binary driver appears to run it later. 2312 */ 2313 if (!ret && (data = init_unknown_script(bios))) { 2314 struct nvbios_init init = { 2315 .subdev = subdev, 2316 .bios = bios, 2317 .offset = data, 2318 .outp = NULL, 2319 .crtc = -1, 2320 .execute = execute ? 1 : 0, 2321 }; 2322 2323 ret = nvbios_exec(&init); 2324 } 2325 2326 return ret; 2327 } 2328