1f3867f43SBen Skeggs /*
2f3867f43SBen Skeggs * Copyright 2012 Red Hat Inc.
3f3867f43SBen Skeggs *
4f3867f43SBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining a
5f3867f43SBen Skeggs * copy of this software and associated documentation files (the "Software"),
6f3867f43SBen Skeggs * to deal in the Software without restriction, including without limitation
7f3867f43SBen Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f3867f43SBen Skeggs * and/or sell copies of the Software, and to permit persons to whom the
9f3867f43SBen Skeggs * Software is furnished to do so, subject to the following conditions:
10f3867f43SBen Skeggs *
11f3867f43SBen Skeggs * The above copyright notice and this permission notice shall be included in
12f3867f43SBen Skeggs * all copies or substantial portions of the Software.
13f3867f43SBen Skeggs *
14f3867f43SBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f3867f43SBen Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f3867f43SBen Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17f3867f43SBen Skeggs * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18f3867f43SBen Skeggs * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19f3867f43SBen Skeggs * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20f3867f43SBen Skeggs * OTHER DEALINGS IN THE SOFTWARE.
21f3867f43SBen Skeggs *
22f3867f43SBen Skeggs * Authors: Ben Skeggs
23f3867f43SBen Skeggs */
24f3867f43SBen Skeggs #include "nv50.h"
25f3867f43SBen Skeggs #include "pll.h"
26f3867f43SBen Skeggs #include "seq.h"
27f3867f43SBen Skeggs
287632b30eSBen Skeggs #include <subdev/bios.h>
297632b30eSBen Skeggs #include <subdev/bios/pll.h>
307632b30eSBen Skeggs
31f3867f43SBen Skeggs static u32
read_div(struct nv50_clk * clk)323eca809bSBen Skeggs read_div(struct nv50_clk *clk)
33f3867f43SBen Skeggs {
34822ad79fSBen Skeggs struct nvkm_device *device = clk->base.subdev.device;
35822ad79fSBen Skeggs switch (device->chipset) {
36f3867f43SBen Skeggs case 0x50: /* it exists, but only has bit 31, not the dividers.. */
37f3867f43SBen Skeggs case 0x84:
38f3867f43SBen Skeggs case 0x86:
39f3867f43SBen Skeggs case 0x98:
40f3867f43SBen Skeggs case 0xa0:
41822ad79fSBen Skeggs return nvkm_rd32(device, 0x004700);
42f3867f43SBen Skeggs case 0x92:
43f3867f43SBen Skeggs case 0x94:
44f3867f43SBen Skeggs case 0x96:
45822ad79fSBen Skeggs return nvkm_rd32(device, 0x004800);
46f3867f43SBen Skeggs default:
47f3867f43SBen Skeggs return 0x00000000;
48f3867f43SBen Skeggs }
49f3867f43SBen Skeggs }
50f3867f43SBen Skeggs
51f3867f43SBen Skeggs static u32
read_pll_src(struct nv50_clk * clk,u32 base)523eca809bSBen Skeggs read_pll_src(struct nv50_clk *clk, u32 base)
53f3867f43SBen Skeggs {
54b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
55b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
566625f55cSBen Skeggs u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal);
57822ad79fSBen Skeggs u32 rsel = nvkm_rd32(device, 0x00e18c);
58f3867f43SBen Skeggs int P, N, M, id;
59f3867f43SBen Skeggs
60822ad79fSBen Skeggs switch (device->chipset) {
61f3867f43SBen Skeggs case 0x50:
62f3867f43SBen Skeggs case 0xa0:
63f3867f43SBen Skeggs switch (base) {
64f3867f43SBen Skeggs case 0x4020:
65f3867f43SBen Skeggs case 0x4028: id = !!(rsel & 0x00000004); break;
66f3867f43SBen Skeggs case 0x4008: id = !!(rsel & 0x00000008); break;
67f3867f43SBen Skeggs case 0x4030: id = 0; break;
68f3867f43SBen Skeggs default:
69b907649eSBen Skeggs nvkm_error(subdev, "ref: bad pll %06x\n", base);
70f3867f43SBen Skeggs return 0;
71f3867f43SBen Skeggs }
72f3867f43SBen Skeggs
73822ad79fSBen Skeggs coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c));
74f3867f43SBen Skeggs ref *= (coef & 0x01000000) ? 2 : 4;
75f3867f43SBen Skeggs P = (coef & 0x00070000) >> 16;
76f3867f43SBen Skeggs N = ((coef & 0x0000ff00) >> 8) + 1;
77f3867f43SBen Skeggs M = ((coef & 0x000000ff) >> 0) + 1;
78f3867f43SBen Skeggs break;
79f3867f43SBen Skeggs case 0x84:
80f3867f43SBen Skeggs case 0x86:
81f3867f43SBen Skeggs case 0x92:
82822ad79fSBen Skeggs coef = nvkm_rd32(device, 0x00e81c);
83f3867f43SBen Skeggs P = (coef & 0x00070000) >> 16;
84f3867f43SBen Skeggs N = (coef & 0x0000ff00) >> 8;
85f3867f43SBen Skeggs M = (coef & 0x000000ff) >> 0;
86f3867f43SBen Skeggs break;
87f3867f43SBen Skeggs case 0x94:
88f3867f43SBen Skeggs case 0x96:
89f3867f43SBen Skeggs case 0x98:
90822ad79fSBen Skeggs rsel = nvkm_rd32(device, 0x00c050);
91f3867f43SBen Skeggs switch (base) {
92f3867f43SBen Skeggs case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
93f3867f43SBen Skeggs case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
94f3867f43SBen Skeggs case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
95f3867f43SBen Skeggs case 0x4030: rsel = 3; break;
96f3867f43SBen Skeggs default:
97b907649eSBen Skeggs nvkm_error(subdev, "ref: bad pll %06x\n", base);
98f3867f43SBen Skeggs return 0;
99f3867f43SBen Skeggs }
100f3867f43SBen Skeggs
101f3867f43SBen Skeggs switch (rsel) {
102f3867f43SBen Skeggs case 0: id = 1; break;
1036625f55cSBen Skeggs case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal);
1046625f55cSBen Skeggs case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href);
105f3867f43SBen Skeggs case 3: id = 0; break;
106f3867f43SBen Skeggs }
107f3867f43SBen Skeggs
108822ad79fSBen Skeggs coef = nvkm_rd32(device, 0x00e81c + (id * 0x28));
109822ad79fSBen Skeggs P = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7;
110f3867f43SBen Skeggs P += (coef & 0x00070000) >> 16;
111f3867f43SBen Skeggs N = (coef & 0x0000ff00) >> 8;
112f3867f43SBen Skeggs M = (coef & 0x000000ff) >> 0;
113f3867f43SBen Skeggs break;
114f3867f43SBen Skeggs default:
115af7db03eSBen Skeggs BUG();
116f3867f43SBen Skeggs }
117f3867f43SBen Skeggs
118f3867f43SBen Skeggs if (M)
119f3867f43SBen Skeggs return (ref * N / M) >> P;
1207632b30eSBen Skeggs
121f3867f43SBen Skeggs return 0;
122f3867f43SBen Skeggs }
123f3867f43SBen Skeggs
124f3867f43SBen Skeggs static u32
read_pll_ref(struct nv50_clk * clk,u32 base)1253eca809bSBen Skeggs read_pll_ref(struct nv50_clk *clk, u32 base)
126f3867f43SBen Skeggs {
127b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
128b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
129822ad79fSBen Skeggs u32 src, mast = nvkm_rd32(device, 0x00c040);
130f3867f43SBen Skeggs
131f3867f43SBen Skeggs switch (base) {
132f3867f43SBen Skeggs case 0x004028:
133f3867f43SBen Skeggs src = !!(mast & 0x00200000);
134f3867f43SBen Skeggs break;
135f3867f43SBen Skeggs case 0x004020:
136f3867f43SBen Skeggs src = !!(mast & 0x00400000);
137f3867f43SBen Skeggs break;
138f3867f43SBen Skeggs case 0x004008:
139f3867f43SBen Skeggs src = !!(mast & 0x00010000);
140f3867f43SBen Skeggs break;
141f3867f43SBen Skeggs case 0x004030:
142f3867f43SBen Skeggs src = !!(mast & 0x02000000);
143f3867f43SBen Skeggs break;
144f3867f43SBen Skeggs case 0x00e810:
1456625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_crystal);
146f3867f43SBen Skeggs default:
147b907649eSBen Skeggs nvkm_error(subdev, "bad pll %06x\n", base);
148f3867f43SBen Skeggs return 0;
149f3867f43SBen Skeggs }
150f3867f43SBen Skeggs
151f3867f43SBen Skeggs if (src)
1526625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_href);
1537632b30eSBen Skeggs
1543eca809bSBen Skeggs return read_pll_src(clk, base);
155f3867f43SBen Skeggs }
156f3867f43SBen Skeggs
157f3867f43SBen Skeggs static u32
read_pll(struct nv50_clk * clk,u32 base)1583eca809bSBen Skeggs read_pll(struct nv50_clk *clk, u32 base)
159f3867f43SBen Skeggs {
160822ad79fSBen Skeggs struct nvkm_device *device = clk->base.subdev.device;
161822ad79fSBen Skeggs u32 mast = nvkm_rd32(device, 0x00c040);
162822ad79fSBen Skeggs u32 ctrl = nvkm_rd32(device, base + 0);
163822ad79fSBen Skeggs u32 coef = nvkm_rd32(device, base + 4);
1643eca809bSBen Skeggs u32 ref = read_pll_ref(clk, base);
165f3867f43SBen Skeggs u32 freq = 0;
166f3867f43SBen Skeggs int N1, N2, M1, M2;
167f3867f43SBen Skeggs
168f3867f43SBen Skeggs if (base == 0x004028 && (mast & 0x00100000)) {
1697632b30eSBen Skeggs /* wtf, appears to only disable post-divider on gt200 */
170822ad79fSBen Skeggs if (device->chipset != 0xa0)
1716625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
172f3867f43SBen Skeggs }
173f3867f43SBen Skeggs
174f3867f43SBen Skeggs N2 = (coef & 0xff000000) >> 24;
175f3867f43SBen Skeggs M2 = (coef & 0x00ff0000) >> 16;
176f3867f43SBen Skeggs N1 = (coef & 0x0000ff00) >> 8;
177f3867f43SBen Skeggs M1 = (coef & 0x000000ff);
178f3867f43SBen Skeggs if ((ctrl & 0x80000000) && M1) {
179f3867f43SBen Skeggs freq = ref * N1 / M1;
180f3867f43SBen Skeggs if ((ctrl & 0x40000100) == 0x40000000) {
181f3867f43SBen Skeggs if (M2)
182f3867f43SBen Skeggs freq = freq * N2 / M2;
183f3867f43SBen Skeggs else
184f3867f43SBen Skeggs freq = 0;
185f3867f43SBen Skeggs }
186f3867f43SBen Skeggs }
187f3867f43SBen Skeggs
188f3867f43SBen Skeggs return freq;
189f3867f43SBen Skeggs }
190f3867f43SBen Skeggs
1916625f55cSBen Skeggs int
nv50_clk_read(struct nvkm_clk * base,enum nv_clk_src src)1926625f55cSBen Skeggs nv50_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
193f3867f43SBen Skeggs {
1946625f55cSBen Skeggs struct nv50_clk *clk = nv50_clk(base);
195b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
196b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
197822ad79fSBen Skeggs u32 mast = nvkm_rd32(device, 0x00c040);
198f3867f43SBen Skeggs u32 P = 0;
199f3867f43SBen Skeggs
200f3867f43SBen Skeggs switch (src) {
201f3867f43SBen Skeggs case nv_clk_src_crystal:
202822ad79fSBen Skeggs return device->crystal;
203f3867f43SBen Skeggs case nv_clk_src_href:
204f3867f43SBen Skeggs return 100000; /* PCIE reference clock */
205f3867f43SBen Skeggs case nv_clk_src_hclk:
2066625f55cSBen Skeggs return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000);
207f3867f43SBen Skeggs case nv_clk_src_hclkm3:
2086625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;
209f3867f43SBen Skeggs case nv_clk_src_hclkm3d2:
2106625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2;
211f3867f43SBen Skeggs case nv_clk_src_host:
212f3867f43SBen Skeggs switch (mast & 0x30000000) {
2136625f55cSBen Skeggs case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
214f3867f43SBen Skeggs case 0x10000000: break;
215f3867f43SBen Skeggs case 0x20000000: /* !0x50 */
2166625f55cSBen Skeggs case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
217f3867f43SBen Skeggs }
218f3867f43SBen Skeggs break;
219f3867f43SBen Skeggs case nv_clk_src_core:
220f3867f43SBen Skeggs if (!(mast & 0x00100000))
221822ad79fSBen Skeggs P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16;
222f3867f43SBen Skeggs switch (mast & 0x00000003) {
2236625f55cSBen Skeggs case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
2246625f55cSBen Skeggs case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6);
2253eca809bSBen Skeggs case 0x00000002: return read_pll(clk, 0x004020) >> P;
2263eca809bSBen Skeggs case 0x00000003: return read_pll(clk, 0x004028) >> P;
227f3867f43SBen Skeggs }
228f3867f43SBen Skeggs break;
229f3867f43SBen Skeggs case nv_clk_src_shader:
230822ad79fSBen Skeggs P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16;
231f3867f43SBen Skeggs switch (mast & 0x00000030) {
232f3867f43SBen Skeggs case 0x00000000:
233f3867f43SBen Skeggs if (mast & 0x00000080)
2346625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P;
2356625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
236f3867f43SBen Skeggs case 0x00000010: break;
2373eca809bSBen Skeggs case 0x00000020: return read_pll(clk, 0x004028) >> P;
2383eca809bSBen Skeggs case 0x00000030: return read_pll(clk, 0x004020) >> P;
239f3867f43SBen Skeggs }
240f3867f43SBen Skeggs break;
241f3867f43SBen Skeggs case nv_clk_src_mem:
242822ad79fSBen Skeggs P = (nvkm_rd32(device, 0x004008) & 0x00070000) >> 16;
243822ad79fSBen Skeggs if (nvkm_rd32(device, 0x004008) & 0x00000200) {
244f3867f43SBen Skeggs switch (mast & 0x0000c000) {
245f3867f43SBen Skeggs case 0x00000000:
2466625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
247f3867f43SBen Skeggs case 0x00008000:
248f3867f43SBen Skeggs case 0x0000c000:
2496625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;
250f3867f43SBen Skeggs }
251f3867f43SBen Skeggs } else {
2523eca809bSBen Skeggs return read_pll(clk, 0x004008) >> P;
253f3867f43SBen Skeggs }
254f3867f43SBen Skeggs break;
255f3867f43SBen Skeggs case nv_clk_src_vdec:
2563eca809bSBen Skeggs P = (read_div(clk) & 0x00000700) >> 8;
257822ad79fSBen Skeggs switch (device->chipset) {
258f3867f43SBen Skeggs case 0x84:
259f3867f43SBen Skeggs case 0x86:
260f3867f43SBen Skeggs case 0x92:
261f3867f43SBen Skeggs case 0x94:
262f3867f43SBen Skeggs case 0x96:
263f3867f43SBen Skeggs case 0xa0:
264f3867f43SBen Skeggs switch (mast & 0x00000c00) {
265f3867f43SBen Skeggs case 0x00000000:
266822ad79fSBen Skeggs if (device->chipset == 0xa0) /* wtf?? */
2676625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
2686625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
269f3867f43SBen Skeggs case 0x00000400:
270f3867f43SBen Skeggs return 0;
271f3867f43SBen Skeggs case 0x00000800:
272f3867f43SBen Skeggs if (mast & 0x01000000)
2733eca809bSBen Skeggs return read_pll(clk, 0x004028) >> P;
2743eca809bSBen Skeggs return read_pll(clk, 0x004030) >> P;
275f3867f43SBen Skeggs case 0x00000c00:
2766625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
277f3867f43SBen Skeggs }
278f3867f43SBen Skeggs break;
279f3867f43SBen Skeggs case 0x98:
280f3867f43SBen Skeggs switch (mast & 0x00000c00) {
281f3867f43SBen Skeggs case 0x00000000:
2826625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
283f3867f43SBen Skeggs case 0x00000400:
284f3867f43SBen Skeggs return 0;
285f3867f43SBen Skeggs case 0x00000800:
2866625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P;
287f3867f43SBen Skeggs case 0x00000c00:
2886625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P;
289f3867f43SBen Skeggs }
290f3867f43SBen Skeggs break;
291f3867f43SBen Skeggs }
292f3867f43SBen Skeggs break;
293f3867f43SBen Skeggs case nv_clk_src_dom6:
294822ad79fSBen Skeggs switch (device->chipset) {
295f3867f43SBen Skeggs case 0x50:
296f3867f43SBen Skeggs case 0xa0:
2973eca809bSBen Skeggs return read_pll(clk, 0x00e810) >> 2;
298f3867f43SBen Skeggs case 0x84:
299f3867f43SBen Skeggs case 0x86:
300f3867f43SBen Skeggs case 0x92:
301f3867f43SBen Skeggs case 0x94:
302f3867f43SBen Skeggs case 0x96:
303f3867f43SBen Skeggs case 0x98:
3043eca809bSBen Skeggs P = (read_div(clk) & 0x00000007) >> 0;
305f3867f43SBen Skeggs switch (mast & 0x0c000000) {
3066625f55cSBen Skeggs case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
307f3867f43SBen Skeggs case 0x04000000: break;
3086625f55cSBen Skeggs case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk);
309f3867f43SBen Skeggs case 0x0c000000:
3106625f55cSBen Skeggs return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P;
311f3867f43SBen Skeggs }
312f3867f43SBen Skeggs break;
313f3867f43SBen Skeggs default:
314f3867f43SBen Skeggs break;
315f3867f43SBen Skeggs }
316*0850bf2eSGustavo A. R. Silva break;
317f3867f43SBen Skeggs default:
318f3867f43SBen Skeggs break;
319f3867f43SBen Skeggs }
320f3867f43SBen Skeggs
321b907649eSBen Skeggs nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
322f3867f43SBen Skeggs return -EINVAL;
323f3867f43SBen Skeggs }
324f3867f43SBen Skeggs
325f3867f43SBen Skeggs static u32
calc_pll(struct nv50_clk * clk,u32 reg,u32 idx,int * N,int * M,int * P)3263eca809bSBen Skeggs calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P)
327f3867f43SBen Skeggs {
32846484438SBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
329f3867f43SBen Skeggs struct nvbios_pll pll;
330f3867f43SBen Skeggs int ret;
331f3867f43SBen Skeggs
33246484438SBen Skeggs ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
333f3867f43SBen Skeggs if (ret)
334f3867f43SBen Skeggs return 0;
335f3867f43SBen Skeggs
336f3867f43SBen Skeggs pll.vco2.max_freq = 0;
3373eca809bSBen Skeggs pll.refclk = read_pll_ref(clk, reg);
338f3867f43SBen Skeggs if (!pll.refclk)
339f3867f43SBen Skeggs return 0;
340f3867f43SBen Skeggs
34146484438SBen Skeggs return nv04_pll_calc(subdev, &pll, idx, N, M, NULL, NULL, P);
342f3867f43SBen Skeggs }
343f3867f43SBen Skeggs
344f3867f43SBen Skeggs static inline u32
calc_div(u32 src,u32 target,int * div)345f3867f43SBen Skeggs calc_div(u32 src, u32 target, int *div)
346f3867f43SBen Skeggs {
347f3867f43SBen Skeggs u32 clk0 = src, clk1 = src;
348f3867f43SBen Skeggs for (*div = 0; *div <= 7; (*div)++) {
349f3867f43SBen Skeggs if (clk0 <= target) {
350f3867f43SBen Skeggs clk1 = clk0 << (*div ? 1 : 0);
351f3867f43SBen Skeggs break;
352f3867f43SBen Skeggs }
353f3867f43SBen Skeggs clk0 >>= 1;
354f3867f43SBen Skeggs }
355f3867f43SBen Skeggs
356f3867f43SBen Skeggs if (target - clk0 <= clk1 - target)
357f3867f43SBen Skeggs return clk0;
358f3867f43SBen Skeggs (*div)--;
359f3867f43SBen Skeggs return clk1;
360f3867f43SBen Skeggs }
361f3867f43SBen Skeggs
362f3867f43SBen Skeggs static inline u32
clk_same(u32 a,u32 b)363f3867f43SBen Skeggs clk_same(u32 a, u32 b)
364f3867f43SBen Skeggs {
365f3867f43SBen Skeggs return ((a / 1000) == (b / 1000));
366f3867f43SBen Skeggs }
367f3867f43SBen Skeggs
3686625f55cSBen Skeggs int
nv50_clk_calc(struct nvkm_clk * base,struct nvkm_cstate * cstate)3696625f55cSBen Skeggs nv50_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
370f3867f43SBen Skeggs {
3716625f55cSBen Skeggs struct nv50_clk *clk = nv50_clk(base);
3723eca809bSBen Skeggs struct nv50_clk_hwsq *hwsq = &clk->hwsq;
3736625f55cSBen Skeggs struct nvkm_subdev *subdev = &clk->base.subdev;
3746625f55cSBen Skeggs struct nvkm_device *device = subdev->device;
375f3867f43SBen Skeggs const int shader = cstate->domain[nv_clk_src_shader];
376f3867f43SBen Skeggs const int core = cstate->domain[nv_clk_src_core];
377f3867f43SBen Skeggs const int vdec = cstate->domain[nv_clk_src_vdec];
378f3867f43SBen Skeggs const int dom6 = cstate->domain[nv_clk_src_dom6];
379f3867f43SBen Skeggs u32 mastm = 0, mastv = 0;
380f3867f43SBen Skeggs u32 divsm = 0, divsv = 0;
381f3867f43SBen Skeggs int N, M, P1, P2;
382f3867f43SBen Skeggs int freq, out;
383f3867f43SBen Skeggs
384f3867f43SBen Skeggs /* prepare a hwsq script from which we'll perform the reclock */
3856625f55cSBen Skeggs out = clk_init(hwsq, subdev);
386f3867f43SBen Skeggs if (out)
387f3867f43SBen Skeggs return out;
388f3867f43SBen Skeggs
389f3867f43SBen Skeggs clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
390f3867f43SBen Skeggs clk_nsec(hwsq, 8000);
391f3867f43SBen Skeggs clk_setf(hwsq, 0x10, 0x00); /* disable fb */
392f3867f43SBen Skeggs clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
393f3867f43SBen Skeggs
394f3867f43SBen Skeggs /* vdec: avoid modifying xpll until we know exactly how the other
395f3867f43SBen Skeggs * clock domains work, i suspect at least some of them can also be
396f3867f43SBen Skeggs * tied to xpll...
397f3867f43SBen Skeggs */
398f3867f43SBen Skeggs if (vdec) {
399f3867f43SBen Skeggs /* see how close we can get using nvclk as a source */
400f3867f43SBen Skeggs freq = calc_div(core, vdec, &P1);
401f3867f43SBen Skeggs
402f3867f43SBen Skeggs /* see how close we can get using xpll/hclk as a source */
4036625f55cSBen Skeggs if (device->chipset != 0x98)
4043eca809bSBen Skeggs out = read_pll(clk, 0x004030);
405f3867f43SBen Skeggs else
4066625f55cSBen Skeggs out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2);
407f3867f43SBen Skeggs out = calc_div(out, vdec, &P2);
408f3867f43SBen Skeggs
409f3867f43SBen Skeggs /* select whichever gets us closest */
410f3867f43SBen Skeggs if (abs(vdec - freq) <= abs(vdec - out)) {
4116625f55cSBen Skeggs if (device->chipset != 0x98)
412f3867f43SBen Skeggs mastv |= 0x00000c00;
413f3867f43SBen Skeggs divsv |= P1 << 8;
414f3867f43SBen Skeggs } else {
415f3867f43SBen Skeggs mastv |= 0x00000800;
416f3867f43SBen Skeggs divsv |= P2 << 8;
417f3867f43SBen Skeggs }
418f3867f43SBen Skeggs
419f3867f43SBen Skeggs mastm |= 0x00000c00;
420f3867f43SBen Skeggs divsm |= 0x00000700;
421f3867f43SBen Skeggs }
422f3867f43SBen Skeggs
423f3867f43SBen Skeggs /* dom6: nfi what this is, but we're limited to various combinations
424f3867f43SBen Skeggs * of the host clock frequency
425f3867f43SBen Skeggs */
426f3867f43SBen Skeggs if (dom6) {
4276625f55cSBen Skeggs if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) {
428f3867f43SBen Skeggs mastv |= 0x00000000;
429f3867f43SBen Skeggs } else
4306625f55cSBen Skeggs if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) {
431f3867f43SBen Skeggs mastv |= 0x08000000;
432f3867f43SBen Skeggs } else {
4336625f55cSBen Skeggs freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3;
4343eca809bSBen Skeggs calc_div(freq, dom6, &P1);
435f3867f43SBen Skeggs
436f3867f43SBen Skeggs mastv |= 0x0c000000;
437f3867f43SBen Skeggs divsv |= P1;
438f3867f43SBen Skeggs }
439f3867f43SBen Skeggs
440f3867f43SBen Skeggs mastm |= 0x0c000000;
441f3867f43SBen Skeggs divsm |= 0x00000007;
442f3867f43SBen Skeggs }
443f3867f43SBen Skeggs
444f3867f43SBen Skeggs /* vdec/dom6: switch to "safe" clocks temporarily, update dividers
445f3867f43SBen Skeggs * and then switch to target clocks
446f3867f43SBen Skeggs */
447f3867f43SBen Skeggs clk_mask(hwsq, mast, mastm, 0x00000000);
448f3867f43SBen Skeggs clk_mask(hwsq, divs, divsm, divsv);
449f3867f43SBen Skeggs clk_mask(hwsq, mast, mastm, mastv);
450f3867f43SBen Skeggs
451f3867f43SBen Skeggs /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
452f3867f43SBen Skeggs * sclk to hclk) before reprogramming
453f3867f43SBen Skeggs */
4546625f55cSBen Skeggs if (device->chipset < 0x92)
455f3867f43SBen Skeggs clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
456f3867f43SBen Skeggs else
457f3867f43SBen Skeggs clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
458f3867f43SBen Skeggs
459f3867f43SBen Skeggs /* core: for the moment at least, always use nvpll */
4603eca809bSBen Skeggs freq = calc_pll(clk, 0x4028, core, &N, &M, &P1);
461f3867f43SBen Skeggs if (freq == 0)
462f3867f43SBen Skeggs return -ERANGE;
463f3867f43SBen Skeggs
464f3867f43SBen Skeggs clk_mask(hwsq, nvpll[0], 0xc03f0100,
465f3867f43SBen Skeggs 0x80000000 | (P1 << 19) | (P1 << 16));
466f3867f43SBen Skeggs clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
467f3867f43SBen Skeggs
468f3867f43SBen Skeggs /* shader: tie to nvclk if possible, otherwise use spll. have to be
469f3867f43SBen Skeggs * very careful that the shader clock is at least twice the core, or
470f3867f43SBen Skeggs * some chipsets will be very unhappy. i expect most or all of these
471f3867f43SBen Skeggs * cases will be handled by tying to nvclk, but it's possible there's
472f3867f43SBen Skeggs * corners
473f3867f43SBen Skeggs */
474f3867f43SBen Skeggs if (P1-- && shader == (core << 1)) {
475f3867f43SBen Skeggs clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
476f3867f43SBen Skeggs clk_mask(hwsq, mast, 0x00100033, 0x00000023);
477f3867f43SBen Skeggs } else {
4783eca809bSBen Skeggs freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
479f3867f43SBen Skeggs if (freq == 0)
480f3867f43SBen Skeggs return -ERANGE;
481f3867f43SBen Skeggs
482f3867f43SBen Skeggs clk_mask(hwsq, spll[0], 0xc03f0100,
483f3867f43SBen Skeggs 0x80000000 | (P1 << 19) | (P1 << 16));
484f3867f43SBen Skeggs clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
485f3867f43SBen Skeggs clk_mask(hwsq, mast, 0x00100033, 0x00000033);
486f3867f43SBen Skeggs }
487f3867f43SBen Skeggs
488f3867f43SBen Skeggs /* restore normal operation */
489f3867f43SBen Skeggs clk_setf(hwsq, 0x10, 0x01); /* enable fb */
490f3867f43SBen Skeggs clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
491f3867f43SBen Skeggs clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
492f3867f43SBen Skeggs return 0;
493f3867f43SBen Skeggs }
494f3867f43SBen Skeggs
4956625f55cSBen Skeggs int
nv50_clk_prog(struct nvkm_clk * base)4966625f55cSBen Skeggs nv50_clk_prog(struct nvkm_clk *base)
497f3867f43SBen Skeggs {
4986625f55cSBen Skeggs struct nv50_clk *clk = nv50_clk(base);
4993eca809bSBen Skeggs return clk_exec(&clk->hwsq, true);
500f3867f43SBen Skeggs }
501f3867f43SBen Skeggs
5026625f55cSBen Skeggs void
nv50_clk_tidy(struct nvkm_clk * base)5036625f55cSBen Skeggs nv50_clk_tidy(struct nvkm_clk *base)
504f3867f43SBen Skeggs {
5056625f55cSBen Skeggs struct nv50_clk *clk = nv50_clk(base);
5063eca809bSBen Skeggs clk_exec(&clk->hwsq, false);
507f3867f43SBen Skeggs }
508f3867f43SBen Skeggs
509f3867f43SBen Skeggs int
nv50_clk_new_(const struct nvkm_clk_func * func,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,bool allow_reclock,struct nvkm_clk ** pclk)5106625f55cSBen Skeggs nv50_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
51198fd7f83SBen Skeggs enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
512f3867f43SBen Skeggs {
5133eca809bSBen Skeggs struct nv50_clk *clk;
514f3867f43SBen Skeggs int ret;
515f3867f43SBen Skeggs
5166625f55cSBen Skeggs if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
5176625f55cSBen Skeggs return -ENOMEM;
51898fd7f83SBen Skeggs ret = nvkm_clk_ctor(func, device, type, inst, allow_reclock, &clk->base);
5196625f55cSBen Skeggs *pclk = &clk->base;
520f3867f43SBen Skeggs if (ret)
521f3867f43SBen Skeggs return ret;
522f3867f43SBen Skeggs
5233eca809bSBen Skeggs clk->hwsq.r_fifo = hwsq_reg(0x002504);
5243eca809bSBen Skeggs clk->hwsq.r_spll[0] = hwsq_reg(0x004020);
5253eca809bSBen Skeggs clk->hwsq.r_spll[1] = hwsq_reg(0x004024);
5263eca809bSBen Skeggs clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
5273eca809bSBen Skeggs clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
5286625f55cSBen Skeggs switch (device->chipset) {
529f3867f43SBen Skeggs case 0x92:
530f3867f43SBen Skeggs case 0x94:
531f3867f43SBen Skeggs case 0x96:
5323eca809bSBen Skeggs clk->hwsq.r_divs = hwsq_reg(0x004800);
533f3867f43SBen Skeggs break;
534f3867f43SBen Skeggs default:
5353eca809bSBen Skeggs clk->hwsq.r_divs = hwsq_reg(0x004700);
536f3867f43SBen Skeggs break;
537f3867f43SBen Skeggs }
5383eca809bSBen Skeggs clk->hwsq.r_mast = hwsq_reg(0x00c040);
539f3867f43SBen Skeggs return 0;
540f3867f43SBen Skeggs }
541f3867f43SBen Skeggs
5426625f55cSBen Skeggs static const struct nvkm_clk_func
5436625f55cSBen Skeggs nv50_clk = {
5446625f55cSBen Skeggs .read = nv50_clk_read,
5456625f55cSBen Skeggs .calc = nv50_clk_calc,
5466625f55cSBen Skeggs .prog = nv50_clk_prog,
5476625f55cSBen Skeggs .tidy = nv50_clk_tidy,
5486625f55cSBen Skeggs .domains = {
549f3867f43SBen Skeggs { nv_clk_src_crystal, 0xff },
550f3867f43SBen Skeggs { nv_clk_src_href , 0xff },
551f3867f43SBen Skeggs { nv_clk_src_core , 0xff, 0, "core", 1000 },
552f3867f43SBen Skeggs { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
553f3867f43SBen Skeggs { nv_clk_src_mem , 0xff, 0, "memory", 1000 },
554f3867f43SBen Skeggs { nv_clk_src_max }
5556625f55cSBen Skeggs }
556f3867f43SBen Skeggs };
557f3867f43SBen Skeggs
5586625f55cSBen Skeggs int
nv50_clk_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_clk ** pclk)55998fd7f83SBen Skeggs nv50_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
56098fd7f83SBen Skeggs struct nvkm_clk **pclk)
5616625f55cSBen Skeggs {
56298fd7f83SBen Skeggs return nv50_clk_new_(&nv50_clk, device, type, inst, false, pclk);
5636625f55cSBen Skeggs }
564