xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c (revision 44f57d78)
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  *          Lyude Paul
24  */
25 #include "gk104.h"
26 #include "gf100.h"
27 #include "ram.h"
28 
29 /*
30  *******************************************************************************
31  * PGRAPH registers for clockgating
32  *******************************************************************************
33  */
34 const struct nvkm_therm_clkgate_init
35 gk104_fb_clkgate_blcg_init_unk_0[] = {
36 	{ 0x100d10, 1, 0x0000c244 },
37 	{ 0x100d30, 1, 0x0000c242 },
38 	{ 0x100d3c, 1, 0x00000242 },
39 	{ 0x100d48, 1, 0x00000242 },
40 	{ 0x100d1c, 1, 0x00000042 },
41 	{}
42 };
43 
44 const struct nvkm_therm_clkgate_init
45 gk104_fb_clkgate_blcg_init_vm_0[] = {
46 	{ 0x100c98, 1, 0x00000242 },
47 	{}
48 };
49 
50 const struct nvkm_therm_clkgate_init
51 gk104_fb_clkgate_blcg_init_main_0[] = {
52 	{ 0x10f000, 1, 0x00000042 },
53 	{ 0x17e030, 1, 0x00000044 },
54 	{ 0x17e040, 1, 0x00000044 },
55 	{}
56 };
57 
58 const struct nvkm_therm_clkgate_init
59 gk104_fb_clkgate_blcg_init_bcast_0[] = {
60 	{ 0x17ea60, 4, 0x00000044 },
61 	{}
62 };
63 
64 static const struct nvkm_therm_clkgate_pack
65 gk104_fb_clkgate_pack[] = {
66 	{ gk104_fb_clkgate_blcg_init_unk_0 },
67 	{ gk104_fb_clkgate_blcg_init_vm_0 },
68 	{ gk104_fb_clkgate_blcg_init_main_0 },
69 	{ gk104_fb_clkgate_blcg_init_bcast_0 },
70 	{}
71 };
72 
73 static const struct nvkm_fb_func
74 gk104_fb = {
75 	.dtor = gf100_fb_dtor,
76 	.oneinit = gf100_fb_oneinit,
77 	.init = gf100_fb_init,
78 	.init_page = gf100_fb_init_page,
79 	.intr = gf100_fb_intr,
80 	.ram_new = gk104_ram_new,
81 	.default_bigpage = 17,
82 	.clkgate_pack = gk104_fb_clkgate_pack,
83 };
84 
85 int
86 gk104_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
87 {
88 	return gf100_fb_new_(&gk104_fb, device, index, pfb);
89 }
90