1 /*
2  * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  */
22 
23 /*
24  * GK20A does not have dedicated video memory, and to accurately represent this
25  * fact Nouveau will not create a RAM device for it. Therefore its instmem
26  * implementation must be done directly on top of system memory, while
27  * preserving coherency for read and write operations.
28  *
29  * Instmem can be allocated through two means:
30  * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory
31  *    pages contiguous to the GPU. This is the preferred way.
32  * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically
33  *    contiguous memory.
34  *
35  * In both cases CPU read and writes are performed by creating a write-combined
36  * mapping. The GPU L2 cache must thus be flushed/invalidated when required. To
37  * be conservative we do this every time we acquire or release an instobj, but
38  * ideally L2 management should be handled at a higher level.
39  *
40  * To improve performance, CPU mappings are not removed upon instobj release.
41  * Instead they are placed into a LRU list to be recycled when the mapped space
42  * goes beyond a certain threshold. At the moment this limit is 1MB.
43  */
44 #include "priv.h"
45 
46 #include <core/memory.h>
47 #include <core/tegra.h>
48 #include <subdev/ltc.h>
49 #include <subdev/mmu.h>
50 
51 struct gk20a_instobj {
52 	struct nvkm_memory memory;
53 	struct nvkm_mm_node *mn;
54 	struct gk20a_instmem *imem;
55 
56 	/* CPU mapping */
57 	u32 *vaddr;
58 };
59 #define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory)
60 
61 /*
62  * Used for objects allocated using the DMA API
63  */
64 struct gk20a_instobj_dma {
65 	struct gk20a_instobj base;
66 
67 	dma_addr_t handle;
68 	struct nvkm_mm_node r;
69 };
70 #define gk20a_instobj_dma(p) \
71 	container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base)
72 
73 /*
74  * Used for objects flattened using the IOMMU API
75  */
76 struct gk20a_instobj_iommu {
77 	struct gk20a_instobj base;
78 
79 	/* to link into gk20a_instmem::vaddr_lru */
80 	struct list_head vaddr_node;
81 	/* how many clients are using vaddr? */
82 	u32 use_cpt;
83 
84 	/* will point to the higher half of pages */
85 	dma_addr_t *dma_addrs;
86 	/* array of base.mem->size pages (+ dma_addr_ts) */
87 	struct page *pages[];
88 };
89 #define gk20a_instobj_iommu(p) \
90 	container_of(gk20a_instobj(p), struct gk20a_instobj_iommu, base)
91 
92 struct gk20a_instmem {
93 	struct nvkm_instmem base;
94 
95 	/* protects vaddr_* and gk20a_instobj::vaddr* */
96 	struct mutex lock;
97 
98 	/* CPU mappings LRU */
99 	unsigned int vaddr_use;
100 	unsigned int vaddr_max;
101 	struct list_head vaddr_lru;
102 
103 	/* Only used if IOMMU if present */
104 	struct mutex *mm_mutex;
105 	struct nvkm_mm *mm;
106 	struct iommu_domain *domain;
107 	unsigned long iommu_pgshift;
108 	u16 iommu_bit;
109 
110 	/* Only used by DMA API */
111 	unsigned long attrs;
112 };
113 #define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base)
114 
115 static enum nvkm_memory_target
116 gk20a_instobj_target(struct nvkm_memory *memory)
117 {
118 	return NVKM_MEM_TARGET_NCOH;
119 }
120 
121 static u8
122 gk20a_instobj_page(struct nvkm_memory *memory)
123 {
124 	return 12;
125 }
126 
127 static u64
128 gk20a_instobj_addr(struct nvkm_memory *memory)
129 {
130 	return (u64)gk20a_instobj(memory)->mn->offset << 12;
131 }
132 
133 static u64
134 gk20a_instobj_size(struct nvkm_memory *memory)
135 {
136 	return (u64)gk20a_instobj(memory)->mn->length << 12;
137 }
138 
139 /*
140  * Recycle the vaddr of obj. Must be called with gk20a_instmem::lock held.
141  */
142 static void
143 gk20a_instobj_iommu_recycle_vaddr(struct gk20a_instobj_iommu *obj)
144 {
145 	struct gk20a_instmem *imem = obj->base.imem;
146 	/* there should not be any user left... */
147 	WARN_ON(obj->use_cpt);
148 	list_del(&obj->vaddr_node);
149 	vunmap(obj->base.vaddr);
150 	obj->base.vaddr = NULL;
151 	imem->vaddr_use -= nvkm_memory_size(&obj->base.memory);
152 	nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", imem->vaddr_use,
153 		   imem->vaddr_max);
154 }
155 
156 /*
157  * Must be called while holding gk20a_instmem::lock
158  */
159 static void
160 gk20a_instmem_vaddr_gc(struct gk20a_instmem *imem, const u64 size)
161 {
162 	while (imem->vaddr_use + size > imem->vaddr_max) {
163 		/* no candidate that can be unmapped, abort... */
164 		if (list_empty(&imem->vaddr_lru))
165 			break;
166 
167 		gk20a_instobj_iommu_recycle_vaddr(
168 				list_first_entry(&imem->vaddr_lru,
169 				struct gk20a_instobj_iommu, vaddr_node));
170 	}
171 }
172 
173 static void __iomem *
174 gk20a_instobj_acquire_dma(struct nvkm_memory *memory)
175 {
176 	struct gk20a_instobj *node = gk20a_instobj(memory);
177 	struct gk20a_instmem *imem = node->imem;
178 	struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
179 
180 	nvkm_ltc_flush(ltc);
181 
182 	return node->vaddr;
183 }
184 
185 static void __iomem *
186 gk20a_instobj_acquire_iommu(struct nvkm_memory *memory)
187 {
188 	struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
189 	struct gk20a_instmem *imem = node->base.imem;
190 	struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
191 	const u64 size = nvkm_memory_size(memory);
192 
193 	nvkm_ltc_flush(ltc);
194 
195 	mutex_lock(&imem->lock);
196 
197 	if (node->base.vaddr) {
198 		if (!node->use_cpt) {
199 			/* remove from LRU list since mapping in use again */
200 			list_del(&node->vaddr_node);
201 		}
202 		goto out;
203 	}
204 
205 	/* try to free some address space if we reached the limit */
206 	gk20a_instmem_vaddr_gc(imem, size);
207 
208 	/* map the pages */
209 	node->base.vaddr = vmap(node->pages, size >> PAGE_SHIFT, VM_MAP,
210 				pgprot_writecombine(PAGE_KERNEL));
211 	if (!node->base.vaddr) {
212 		nvkm_error(&imem->base.subdev, "cannot map instobj - "
213 			   "this is not going to end well...\n");
214 		goto out;
215 	}
216 
217 	imem->vaddr_use += size;
218 	nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n",
219 		   imem->vaddr_use, imem->vaddr_max);
220 
221 out:
222 	node->use_cpt++;
223 	mutex_unlock(&imem->lock);
224 
225 	return node->base.vaddr;
226 }
227 
228 static void
229 gk20a_instobj_release_dma(struct nvkm_memory *memory)
230 {
231 	struct gk20a_instobj *node = gk20a_instobj(memory);
232 	struct gk20a_instmem *imem = node->imem;
233 	struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
234 
235 	/* in case we got a write-combined mapping */
236 	wmb();
237 	nvkm_ltc_invalidate(ltc);
238 }
239 
240 static void
241 gk20a_instobj_release_iommu(struct nvkm_memory *memory)
242 {
243 	struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
244 	struct gk20a_instmem *imem = node->base.imem;
245 	struct nvkm_ltc *ltc = imem->base.subdev.device->ltc;
246 
247 	mutex_lock(&imem->lock);
248 
249 	/* we should at least have one user to release... */
250 	if (WARN_ON(node->use_cpt == 0))
251 		goto out;
252 
253 	/* add unused objs to the LRU list to recycle their mapping */
254 	if (--node->use_cpt == 0)
255 		list_add_tail(&node->vaddr_node, &imem->vaddr_lru);
256 
257 out:
258 	mutex_unlock(&imem->lock);
259 
260 	wmb();
261 	nvkm_ltc_invalidate(ltc);
262 }
263 
264 static u32
265 gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset)
266 {
267 	struct gk20a_instobj *node = gk20a_instobj(memory);
268 
269 	return node->vaddr[offset / 4];
270 }
271 
272 static void
273 gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data)
274 {
275 	struct gk20a_instobj *node = gk20a_instobj(memory);
276 
277 	node->vaddr[offset / 4] = data;
278 }
279 
280 static int
281 gk20a_instobj_map(struct nvkm_memory *memory, u64 offset, struct nvkm_vmm *vmm,
282 		  struct nvkm_vma *vma, void *argv, u32 argc)
283 {
284 	struct gk20a_instobj *node = gk20a_instobj(memory);
285 	struct nvkm_vmm_map map = {
286 		.memory = &node->memory,
287 		.offset = offset,
288 		.mem = node->mn,
289 	};
290 
291 	return nvkm_vmm_map(vmm, vma, argv, argc, &map);
292 }
293 
294 static void *
295 gk20a_instobj_dtor_dma(struct nvkm_memory *memory)
296 {
297 	struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory);
298 	struct gk20a_instmem *imem = node->base.imem;
299 	struct device *dev = imem->base.subdev.device->dev;
300 
301 	if (unlikely(!node->base.vaddr))
302 		goto out;
303 
304 	dma_free_attrs(dev, (u64)node->base.mn->length << PAGE_SHIFT,
305 		       node->base.vaddr, node->handle, imem->attrs);
306 
307 out:
308 	return node;
309 }
310 
311 static void *
312 gk20a_instobj_dtor_iommu(struct nvkm_memory *memory)
313 {
314 	struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory);
315 	struct gk20a_instmem *imem = node->base.imem;
316 	struct device *dev = imem->base.subdev.device->dev;
317 	struct nvkm_mm_node *r = node->base.mn;
318 	int i;
319 
320 	if (unlikely(!r))
321 		goto out;
322 
323 	mutex_lock(&imem->lock);
324 
325 	/* vaddr has already been recycled */
326 	if (node->base.vaddr)
327 		gk20a_instobj_iommu_recycle_vaddr(node);
328 
329 	mutex_unlock(&imem->lock);
330 
331 	/* clear IOMMU bit to unmap pages */
332 	r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift);
333 
334 	/* Unmap pages from GPU address space and free them */
335 	for (i = 0; i < node->base.mn->length; i++) {
336 		iommu_unmap(imem->domain,
337 			    (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE);
338 		dma_unmap_page(dev, node->dma_addrs[i], PAGE_SIZE,
339 			       DMA_BIDIRECTIONAL);
340 		__free_page(node->pages[i]);
341 	}
342 
343 	/* Release area from GPU address space */
344 	mutex_lock(imem->mm_mutex);
345 	nvkm_mm_free(imem->mm, &r);
346 	mutex_unlock(imem->mm_mutex);
347 
348 out:
349 	return node;
350 }
351 
352 static const struct nvkm_memory_func
353 gk20a_instobj_func_dma = {
354 	.dtor = gk20a_instobj_dtor_dma,
355 	.target = gk20a_instobj_target,
356 	.page = gk20a_instobj_page,
357 	.addr = gk20a_instobj_addr,
358 	.size = gk20a_instobj_size,
359 	.acquire = gk20a_instobj_acquire_dma,
360 	.release = gk20a_instobj_release_dma,
361 	.map = gk20a_instobj_map,
362 };
363 
364 static const struct nvkm_memory_func
365 gk20a_instobj_func_iommu = {
366 	.dtor = gk20a_instobj_dtor_iommu,
367 	.target = gk20a_instobj_target,
368 	.page = gk20a_instobj_page,
369 	.addr = gk20a_instobj_addr,
370 	.size = gk20a_instobj_size,
371 	.acquire = gk20a_instobj_acquire_iommu,
372 	.release = gk20a_instobj_release_iommu,
373 	.map = gk20a_instobj_map,
374 };
375 
376 static const struct nvkm_memory_ptrs
377 gk20a_instobj_ptrs = {
378 	.rd32 = gk20a_instobj_rd32,
379 	.wr32 = gk20a_instobj_wr32,
380 };
381 
382 static int
383 gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align,
384 		       struct gk20a_instobj **_node)
385 {
386 	struct gk20a_instobj_dma *node;
387 	struct nvkm_subdev *subdev = &imem->base.subdev;
388 	struct device *dev = subdev->device->dev;
389 
390 	if (!(node = kzalloc(sizeof(*node), GFP_KERNEL)))
391 		return -ENOMEM;
392 	*_node = &node->base;
393 
394 	nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory);
395 	node->base.memory.ptrs = &gk20a_instobj_ptrs;
396 
397 	node->base.vaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT,
398 					   &node->handle, GFP_KERNEL,
399 					   imem->attrs);
400 	if (!node->base.vaddr) {
401 		nvkm_error(subdev, "cannot allocate DMA memory\n");
402 		return -ENOMEM;
403 	}
404 
405 	/* alignment check */
406 	if (unlikely(node->handle & (align - 1)))
407 		nvkm_warn(subdev,
408 			  "memory not aligned as requested: %pad (0x%x)\n",
409 			  &node->handle, align);
410 
411 	/* present memory for being mapped using small pages */
412 	node->r.type = 12;
413 	node->r.offset = node->handle >> 12;
414 	node->r.length = (npages << PAGE_SHIFT) >> 12;
415 
416 	node->base.mn = &node->r;
417 	return 0;
418 }
419 
420 static int
421 gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align,
422 			 struct gk20a_instobj **_node)
423 {
424 	struct gk20a_instobj_iommu *node;
425 	struct nvkm_subdev *subdev = &imem->base.subdev;
426 	struct device *dev = subdev->device->dev;
427 	struct nvkm_mm_node *r;
428 	int ret;
429 	int i;
430 
431 	/*
432 	 * despite their variable size, instmem allocations are small enough
433 	 * (< 1 page) to be handled by kzalloc
434 	 */
435 	if (!(node = kzalloc(sizeof(*node) + ((sizeof(node->pages[0]) +
436 			     sizeof(*node->dma_addrs)) * npages), GFP_KERNEL)))
437 		return -ENOMEM;
438 	*_node = &node->base;
439 	node->dma_addrs = (void *)(node->pages + npages);
440 
441 	nvkm_memory_ctor(&gk20a_instobj_func_iommu, &node->base.memory);
442 	node->base.memory.ptrs = &gk20a_instobj_ptrs;
443 
444 	/* Allocate backing memory */
445 	for (i = 0; i < npages; i++) {
446 		struct page *p = alloc_page(GFP_KERNEL);
447 		dma_addr_t dma_adr;
448 
449 		if (p == NULL) {
450 			ret = -ENOMEM;
451 			goto free_pages;
452 		}
453 		node->pages[i] = p;
454 		dma_adr = dma_map_page(dev, p, 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
455 		if (dma_mapping_error(dev, dma_adr)) {
456 			nvkm_error(subdev, "DMA mapping error!\n");
457 			ret = -ENOMEM;
458 			goto free_pages;
459 		}
460 		node->dma_addrs[i] = dma_adr;
461 	}
462 
463 	mutex_lock(imem->mm_mutex);
464 	/* Reserve area from GPU address space */
465 	ret = nvkm_mm_head(imem->mm, 0, 1, npages, npages,
466 			   align >> imem->iommu_pgshift, &r);
467 	mutex_unlock(imem->mm_mutex);
468 	if (ret) {
469 		nvkm_error(subdev, "IOMMU space is full!\n");
470 		goto free_pages;
471 	}
472 
473 	/* Map into GPU address space */
474 	for (i = 0; i < npages; i++) {
475 		u32 offset = (r->offset + i) << imem->iommu_pgshift;
476 
477 		ret = iommu_map(imem->domain, offset, node->dma_addrs[i],
478 				PAGE_SIZE, IOMMU_READ | IOMMU_WRITE,
479 				GFP_KERNEL);
480 		if (ret < 0) {
481 			nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret);
482 
483 			while (i-- > 0) {
484 				offset -= PAGE_SIZE;
485 				iommu_unmap(imem->domain, offset, PAGE_SIZE);
486 			}
487 			goto release_area;
488 		}
489 	}
490 
491 	/* IOMMU bit tells that an address is to be resolved through the IOMMU */
492 	r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift);
493 
494 	node->base.mn = r;
495 	return 0;
496 
497 release_area:
498 	mutex_lock(imem->mm_mutex);
499 	nvkm_mm_free(imem->mm, &r);
500 	mutex_unlock(imem->mm_mutex);
501 
502 free_pages:
503 	for (i = 0; i < npages && node->pages[i] != NULL; i++) {
504 		dma_addr_t dma_addr = node->dma_addrs[i];
505 		if (dma_addr)
506 			dma_unmap_page(dev, dma_addr, PAGE_SIZE,
507 				       DMA_BIDIRECTIONAL);
508 		__free_page(node->pages[i]);
509 	}
510 
511 	return ret;
512 }
513 
514 static int
515 gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
516 		  struct nvkm_memory **pmemory)
517 {
518 	struct gk20a_instmem *imem = gk20a_instmem(base);
519 	struct nvkm_subdev *subdev = &imem->base.subdev;
520 	struct gk20a_instobj *node = NULL;
521 	int ret;
522 
523 	nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__,
524 		   imem->domain ? "IOMMU" : "DMA", size, align);
525 
526 	/* Round size and align to page bounds */
527 	size = max(roundup(size, PAGE_SIZE), PAGE_SIZE);
528 	align = max(roundup(align, PAGE_SIZE), PAGE_SIZE);
529 
530 	if (imem->domain)
531 		ret = gk20a_instobj_ctor_iommu(imem, size >> PAGE_SHIFT,
532 					       align, &node);
533 	else
534 		ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT,
535 					     align, &node);
536 	*pmemory = node ? &node->memory : NULL;
537 	if (ret)
538 		return ret;
539 
540 	node->imem = imem;
541 
542 	nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
543 		   size, align, (u64)node->mn->offset << 12);
544 
545 	return 0;
546 }
547 
548 static void *
549 gk20a_instmem_dtor(struct nvkm_instmem *base)
550 {
551 	struct gk20a_instmem *imem = gk20a_instmem(base);
552 
553 	/* perform some sanity checks... */
554 	if (!list_empty(&imem->vaddr_lru))
555 		nvkm_warn(&base->subdev, "instobj LRU not empty!\n");
556 
557 	if (imem->vaddr_use != 0)
558 		nvkm_warn(&base->subdev, "instobj vmap area not empty! "
559 			  "0x%x bytes still mapped\n", imem->vaddr_use);
560 
561 	return imem;
562 }
563 
564 static const struct nvkm_instmem_func
565 gk20a_instmem = {
566 	.dtor = gk20a_instmem_dtor,
567 	.memory_new = gk20a_instobj_new,
568 	.zero = false,
569 };
570 
571 int
572 gk20a_instmem_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
573 		  struct nvkm_instmem **pimem)
574 {
575 	struct nvkm_device_tegra *tdev = device->func->tegra(device);
576 	struct gk20a_instmem *imem;
577 
578 	if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
579 		return -ENOMEM;
580 	nvkm_instmem_ctor(&gk20a_instmem, device, type, inst, &imem->base);
581 	mutex_init(&imem->lock);
582 	*pimem = &imem->base;
583 
584 	/* do not allow more than 1MB of CPU-mapped instmem */
585 	imem->vaddr_use = 0;
586 	imem->vaddr_max = 0x100000;
587 	INIT_LIST_HEAD(&imem->vaddr_lru);
588 
589 	if (tdev->iommu.domain) {
590 		imem->mm_mutex = &tdev->iommu.mutex;
591 		imem->mm = &tdev->iommu.mm;
592 		imem->domain = tdev->iommu.domain;
593 		imem->iommu_pgshift = tdev->iommu.pgshift;
594 		imem->iommu_bit = tdev->func->iommu_bit;
595 
596 		nvkm_info(&imem->base.subdev, "using IOMMU\n");
597 	} else {
598 		imem->attrs = DMA_ATTR_WEAK_ORDERING |
599 			      DMA_ATTR_WRITE_COMBINE;
600 
601 		nvkm_info(&imem->base.subdev, "using DMA API\n");
602 	}
603 
604 	return 0;
605 }
606