1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 6 * Authors: Yong Zhi 7 * Mythri pk <mythripk@ti.com> 8 */ 9 10 #define DSS_SUBSYS_NAME "HDMICORE" 11 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/interrupt.h> 17 #include <linux/mutex.h> 18 #include <linux/delay.h> 19 #include <linux/platform_device.h> 20 #include <linux/string.h> 21 #include <linux/seq_file.h> 22 #include <linux/sys_soc.h> 23 #include <sound/asound.h> 24 #include <sound/asoundef.h> 25 26 #include "hdmi4_core.h" 27 28 #define HDMI_CORE_AV 0x500 29 30 static inline void __iomem *hdmi_av_base(struct hdmi_core_data *core) 31 { 32 return core->base + HDMI_CORE_AV; 33 } 34 35 static int hdmi_core_ddc_init(struct hdmi_core_data *core) 36 { 37 void __iomem *base = core->base; 38 39 /* Turn on CLK for DDC */ 40 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); 41 42 /* IN_PROG */ 43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { 44 /* Abort transaction */ 45 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0); 46 /* IN_PROG */ 47 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 48 4, 4, 0) != 0) { 49 DSSERR("Timeout aborting DDC transaction\n"); 50 return -ETIMEDOUT; 51 } 52 } 53 54 /* Clk SCL Devices */ 55 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0); 56 57 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 58 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 59 4, 4, 0) != 0) { 60 DSSERR("Timeout starting SCL clock\n"); 61 return -ETIMEDOUT; 62 } 63 64 /* Clear FIFO */ 65 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0); 66 67 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 68 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 69 4, 4, 0) != 0) { 70 DSSERR("Timeout clearing DDC fifo\n"); 71 return -ETIMEDOUT; 72 } 73 74 return 0; 75 } 76 77 static int hdmi_core_ddc_edid(struct hdmi_core_data *core, 78 u8 *pedid, int ext) 79 { 80 void __iomem *base = core->base; 81 u32 i; 82 char checksum; 83 u32 offset = 0; 84 85 /* HDMI_CORE_DDC_STATUS_IN_PROG */ 86 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS, 87 4, 4, 0) != 0) { 88 DSSERR("Timeout waiting DDC to be ready\n"); 89 return -ETIMEDOUT; 90 } 91 92 if (ext % 2 != 0) 93 offset = 0x80; 94 95 /* Load Segment Address Register */ 96 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0); 97 98 /* Load Slave Address Register */ 99 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); 100 101 /* Load Offset Address Register */ 102 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0); 103 104 /* Load Byte Count */ 105 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); 106 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); 107 108 /* Set DDC_CMD */ 109 if (ext) 110 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0); 111 else 112 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0); 113 114 /* HDMI_CORE_DDC_STATUS_BUS_LOW */ 115 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { 116 DSSERR("I2C Bus Low?\n"); 117 return -EIO; 118 } 119 /* HDMI_CORE_DDC_STATUS_NO_ACK */ 120 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { 121 DSSERR("I2C No Ack\n"); 122 return -EIO; 123 } 124 125 for (i = 0; i < 0x80; ++i) { 126 int t; 127 128 /* IN_PROG */ 129 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { 130 DSSERR("operation stopped when reading edid\n"); 131 return -EIO; 132 } 133 134 t = 0; 135 /* FIFO_EMPTY */ 136 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { 137 if (t++ > 10000) { 138 DSSERR("timeout reading edid\n"); 139 return -ETIMEDOUT; 140 } 141 udelay(1); 142 } 143 144 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); 145 } 146 147 checksum = 0; 148 for (i = 0; i < 0x80; ++i) 149 checksum += pedid[i]; 150 151 if (checksum != 0) { 152 DSSERR("E-EDID checksum failed!!\n"); 153 return -EIO; 154 } 155 156 return 0; 157 } 158 159 int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) 160 { 161 int r, l; 162 163 if (len < 128) 164 return -EINVAL; 165 166 r = hdmi_core_ddc_init(core); 167 if (r) 168 return r; 169 170 r = hdmi_core_ddc_edid(core, edid, 0); 171 if (r) 172 return r; 173 174 l = 128; 175 176 if (len >= 128 * 2 && edid[0x7e] > 0) { 177 r = hdmi_core_ddc_edid(core, edid + 0x80, 1); 178 if (r) 179 return r; 180 l += 128; 181 } 182 183 return l; 184 } 185 186 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg) 187 { 188 DSSDBG("Enter hdmi_core_init\n"); 189 190 /* video core */ 191 video_cfg->ip_bus_width = HDMI_INPUT_8BIT; 192 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; 193 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; 194 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; 195 video_cfg->hdmi_dvi = HDMI_DVI; 196 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; 197 } 198 199 void hdmi4_core_powerdown_disable(struct hdmi_core_data *core) 200 { 201 DSSDBG("Enter hdmi4_core_powerdown_disable\n"); 202 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SYS_CTRL1, 0x1, 0, 0); 203 } 204 205 static void hdmi_core_swreset_release(struct hdmi_core_data *core) 206 { 207 DSSDBG("Enter hdmi_core_swreset_release\n"); 208 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x0, 0, 0); 209 } 210 211 static void hdmi_core_swreset_assert(struct hdmi_core_data *core) 212 { 213 DSSDBG("Enter hdmi_core_swreset_assert\n"); 214 REG_FLD_MOD(core->base, HDMI_CORE_SYS_SRST, 0x1, 0, 0); 215 } 216 217 /* HDMI_CORE_VIDEO_CONFIG */ 218 static void hdmi_core_video_config(struct hdmi_core_data *core, 219 struct hdmi_core_video_config *cfg) 220 { 221 u32 r = 0; 222 void __iomem *core_sys_base = core->base; 223 void __iomem *core_av_base = hdmi_av_base(core); 224 225 /* sys_ctrl1 default configuration not tunable */ 226 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1); 227 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC, 5, 5); 228 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC, 4, 4); 229 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS, 2, 2); 230 r = FLD_MOD(r, HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE, 1, 1); 231 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_SYS_CTRL1, r); 232 233 REG_FLD_MOD(core_sys_base, 234 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); 235 236 /* Vid_Mode */ 237 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE); 238 239 /* dither truncation configuration */ 240 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { 241 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); 242 r = FLD_MOD(r, 1, 5, 5); 243 } else { 244 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); 245 r = FLD_MOD(r, 0, 5, 5); 246 } 247 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r); 248 249 /* HDMI_Ctrl */ 250 r = hdmi_read_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL); 251 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); 252 r = FLD_MOD(r, cfg->pkt_mode, 5, 3); 253 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); 254 hdmi_write_reg(core_av_base, HDMI_CORE_AV_HDMI_CTRL, r); 255 256 /* TMDS_CTRL */ 257 REG_FLD_MOD(core_sys_base, 258 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5); 259 } 260 261 static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core, 262 struct hdmi_avi_infoframe *frame) 263 { 264 void __iomem *av_base = hdmi_av_base(core); 265 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 266 int i; 267 268 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 269 270 print_hex_dump_debug("AVI: ", DUMP_PREFIX_NONE, 16, 1, data, 271 HDMI_INFOFRAME_SIZE(AVI), false); 272 273 for (i = 0; i < sizeof(data); ++i) { 274 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, 275 data[i]); 276 } 277 } 278 279 static void hdmi_core_av_packet_config(struct hdmi_core_data *core, 280 struct hdmi_core_packet_enable_repeat repeat_cfg) 281 { 282 /* enable/repeat the infoframe */ 283 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL1, 284 (repeat_cfg.audio_pkt << 5) | 285 (repeat_cfg.audio_pkt_repeat << 4) | 286 (repeat_cfg.avi_infoframe << 1) | 287 (repeat_cfg.avi_infoframe_repeat)); 288 289 /* enable/repeat the packet */ 290 hdmi_write_reg(hdmi_av_base(core), HDMI_CORE_AV_PB_CTRL2, 291 (repeat_cfg.gen_cntrl_pkt << 3) | 292 (repeat_cfg.gen_cntrl_pkt_repeat << 2) | 293 (repeat_cfg.generic_pkt << 1) | 294 (repeat_cfg.generic_pkt_repeat)); 295 } 296 297 void hdmi4_configure(struct hdmi_core_data *core, 298 struct hdmi_wp_data *wp, struct hdmi_config *cfg) 299 { 300 /* HDMI */ 301 struct videomode vm; 302 struct hdmi_video_format video_format; 303 /* HDMI core */ 304 struct hdmi_core_video_config v_core_cfg; 305 struct hdmi_core_packet_enable_repeat repeat_cfg = { 0 }; 306 307 hdmi_core_init(&v_core_cfg); 308 309 hdmi_wp_init_vid_fmt_timings(&video_format, &vm, cfg); 310 311 hdmi_wp_video_config_timing(wp, &vm); 312 313 /* video config */ 314 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; 315 316 hdmi_wp_video_config_format(wp, &video_format); 317 318 hdmi_wp_video_config_interface(wp, &vm); 319 320 /* 321 * configure core video part 322 * set software reset in the core 323 */ 324 hdmi_core_swreset_assert(core); 325 326 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; 327 v_core_cfg.hdmi_dvi = cfg->hdmi_dvi_mode; 328 329 hdmi_core_video_config(core, &v_core_cfg); 330 331 /* release software reset in the core */ 332 hdmi_core_swreset_release(core); 333 334 if (cfg->hdmi_dvi_mode == HDMI_HDMI) { 335 hdmi_core_write_avi_infoframe(core, &cfg->infoframe); 336 337 /* enable/repeat the infoframe */ 338 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; 339 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; 340 /* wakeup */ 341 repeat_cfg.audio_pkt = HDMI_PACKETENABLE; 342 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; 343 } 344 345 hdmi_core_av_packet_config(core, repeat_cfg); 346 } 347 348 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s) 349 { 350 int i; 351 352 #define CORE_REG(i, name) name(i) 353 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\ 354 hdmi_read_reg(core->base, r)) 355 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\ 356 hdmi_read_reg(hdmi_av_base(core), r)) 357 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \ 358 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \ 359 hdmi_read_reg(hdmi_av_base(core), CORE_REG(i, r))) 360 361 DUMPCORE(HDMI_CORE_SYS_VND_IDL); 362 DUMPCORE(HDMI_CORE_SYS_DEV_IDL); 363 DUMPCORE(HDMI_CORE_SYS_DEV_IDH); 364 DUMPCORE(HDMI_CORE_SYS_DEV_REV); 365 DUMPCORE(HDMI_CORE_SYS_SRST); 366 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1); 367 DUMPCORE(HDMI_CORE_SYS_SYS_STAT); 368 DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3); 369 DUMPCORE(HDMI_CORE_SYS_DE_DLY); 370 DUMPCORE(HDMI_CORE_SYS_DE_CTRL); 371 DUMPCORE(HDMI_CORE_SYS_DE_TOP); 372 DUMPCORE(HDMI_CORE_SYS_DE_CNTL); 373 DUMPCORE(HDMI_CORE_SYS_DE_CNTH); 374 DUMPCORE(HDMI_CORE_SYS_DE_LINL); 375 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1); 376 DUMPCORE(HDMI_CORE_SYS_HRES_L); 377 DUMPCORE(HDMI_CORE_SYS_HRES_H); 378 DUMPCORE(HDMI_CORE_SYS_VRES_L); 379 DUMPCORE(HDMI_CORE_SYS_VRES_H); 380 DUMPCORE(HDMI_CORE_SYS_IADJUST); 381 DUMPCORE(HDMI_CORE_SYS_POLDETECT); 382 DUMPCORE(HDMI_CORE_SYS_HWIDTH1); 383 DUMPCORE(HDMI_CORE_SYS_HWIDTH2); 384 DUMPCORE(HDMI_CORE_SYS_VWIDTH); 385 DUMPCORE(HDMI_CORE_SYS_VID_CTRL); 386 DUMPCORE(HDMI_CORE_SYS_VID_ACEN); 387 DUMPCORE(HDMI_CORE_SYS_VID_MODE); 388 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 389 DUMPCORE(HDMI_CORE_SYS_VID_BLANK3); 390 DUMPCORE(HDMI_CORE_SYS_VID_BLANK1); 391 DUMPCORE(HDMI_CORE_SYS_DC_HEADER); 392 DUMPCORE(HDMI_CORE_SYS_VID_DITHER); 393 DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT); 394 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW); 395 DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP); 396 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW); 397 DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP); 398 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW); 399 DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP); 400 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW); 401 DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP); 402 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW); 403 DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP); 404 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW); 405 DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP); 406 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW); 407 DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP); 408 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW); 409 DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP); 410 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW); 411 DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP); 412 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW); 413 DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP); 414 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW); 415 DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP); 416 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW); 417 DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP); 418 DUMPCORE(HDMI_CORE_SYS_INTR_STATE); 419 DUMPCORE(HDMI_CORE_SYS_INTR1); 420 DUMPCORE(HDMI_CORE_SYS_INTR2); 421 DUMPCORE(HDMI_CORE_SYS_INTR3); 422 DUMPCORE(HDMI_CORE_SYS_INTR4); 423 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1); 424 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2); 425 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3); 426 DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4); 427 DUMPCORE(HDMI_CORE_SYS_INTR_CTRL); 428 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL); 429 430 DUMPCORE(HDMI_CORE_DDC_ADDR); 431 DUMPCORE(HDMI_CORE_DDC_SEGM); 432 DUMPCORE(HDMI_CORE_DDC_OFFSET); 433 DUMPCORE(HDMI_CORE_DDC_COUNT1); 434 DUMPCORE(HDMI_CORE_DDC_COUNT2); 435 DUMPCORE(HDMI_CORE_DDC_STATUS); 436 DUMPCORE(HDMI_CORE_DDC_CMD); 437 DUMPCORE(HDMI_CORE_DDC_DATA); 438 439 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL); 440 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL); 441 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1); 442 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2); 443 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3); 444 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1); 445 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2); 446 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3); 447 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1); 448 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2); 449 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3); 450 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE); 451 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL); 452 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS); 453 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S); 454 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH); 455 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP); 456 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL); 457 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0); 458 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1); 459 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2); 460 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4); 461 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5); 462 DUMPCOREAV(HDMI_CORE_AV_ASRC); 463 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN); 464 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL); 465 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT); 466 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1); 467 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2); 468 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3); 469 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL); 470 DUMPCOREAV(HDMI_CORE_AV_DPD); 471 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1); 472 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2); 473 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE); 474 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS); 475 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN); 476 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM); 477 478 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++) 479 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE); 480 481 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE); 482 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS); 483 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN); 484 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM); 485 486 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++) 487 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE); 488 489 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE); 490 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS); 491 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN); 492 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM); 493 494 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++) 495 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE); 496 497 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE); 498 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS); 499 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN); 500 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM); 501 502 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++) 503 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE); 504 505 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++) 506 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE); 507 508 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1); 509 510 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++) 511 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE); 512 513 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID); 514 } 515 516 static void hdmi_core_audio_config(struct hdmi_core_data *core, 517 struct hdmi_core_audio_config *cfg) 518 { 519 u32 r; 520 void __iomem *av_base = hdmi_av_base(core); 521 522 /* 523 * Parameters for generation of Audio Clock Recovery packets 524 */ 525 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0); 526 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0); 527 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0); 528 529 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) { 530 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0); 531 REG_FLD_MOD(av_base, 532 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0); 533 REG_FLD_MOD(av_base, 534 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0); 535 } else { 536 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1, 537 cfg->aud_par_busclk, 7, 0); 538 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2, 539 (cfg->aud_par_busclk >> 8), 7, 0); 540 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3, 541 (cfg->aud_par_busclk >> 16), 7, 0); 542 } 543 544 /* Set ACR clock divisor */ 545 REG_FLD_MOD(av_base, 546 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0); 547 548 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL); 549 /* 550 * Use TMDS clock for ACR packets. For devices that use 551 * the MCLK, this is the first part of the MCLK initialization. 552 */ 553 r = FLD_MOD(r, 0, 2, 2); 554 555 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1); 556 r = FLD_MOD(r, cfg->cts_mode, 0, 0); 557 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r); 558 559 /* For devices using MCLK, this completes its initialization. */ 560 if (cfg->use_mclk) 561 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2); 562 563 /* Override of SPDIF sample frequency with value in I2S_CHST4 */ 564 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL, 565 cfg->fs_override, 1, 1); 566 567 /* 568 * Set IEC-60958-3 channel status word. It is passed to the IP 569 * just as it is received. The user of the driver is responsible 570 * for its contents. 571 */ 572 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0, 573 cfg->iec60958_cfg->status[0]); 574 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1, 575 cfg->iec60958_cfg->status[1]); 576 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2, 577 cfg->iec60958_cfg->status[2]); 578 /* yes, this is correct: status[3] goes to CHST4 register */ 579 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4, 580 cfg->iec60958_cfg->status[3]); 581 /* yes, this is correct: status[4] goes to CHST5 register */ 582 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, 583 cfg->iec60958_cfg->status[4]); 584 585 /* set I2S parameters */ 586 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL); 587 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6); 588 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4); 589 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2); 590 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1); 591 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0); 592 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r); 593 594 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN, 595 cfg->i2s_cfg.in_length_bits, 3, 0); 596 597 /* Audio channels and mode parameters */ 598 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1); 599 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE); 600 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4); 601 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3); 602 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2); 603 r = FLD_MOD(r, cfg->en_spdif, 1, 1); 604 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r); 605 606 /* Audio channel mappings */ 607 /* TODO: Make channel mapping dynamic. For now, map channels 608 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as 609 * HDMI speaker order is different. See CEA-861 Section 6.6.2. 610 */ 611 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78); 612 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5); 613 } 614 615 static void hdmi_core_audio_infoframe_cfg(struct hdmi_core_data *core, 616 struct snd_cea_861_aud_if *info_aud) 617 { 618 u8 sum = 0, checksum = 0; 619 void __iomem *av_base = hdmi_av_base(core); 620 621 /* 622 * Set audio info frame type, version and length as 623 * described in HDMI 1.4a Section 8.2.2 specification. 624 * Checksum calculation is defined in Section 5.3.5. 625 */ 626 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84); 627 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01); 628 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a); 629 sum += 0x84 + 0x001 + 0x00a; 630 631 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), 632 info_aud->db1_ct_cc); 633 sum += info_aud->db1_ct_cc; 634 635 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), 636 info_aud->db2_sf_ss); 637 sum += info_aud->db2_sf_ss; 638 639 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3); 640 sum += info_aud->db3; 641 642 /* 643 * The OMAP HDMI IP requires to use the 8-channel channel code when 644 * transmitting more than two channels. 645 */ 646 if (info_aud->db4_ca != 0x00) 647 info_aud->db4_ca = 0x13; 648 649 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca); 650 sum += info_aud->db4_ca; 651 652 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), 653 info_aud->db5_dminh_lsv); 654 sum += info_aud->db5_dminh_lsv; 655 656 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00); 657 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00); 658 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00); 659 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00); 660 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00); 661 662 checksum = 0x100 - sum; 663 hdmi_write_reg(av_base, 664 HDMI_CORE_AV_AUDIO_CHSUM, checksum); 665 666 /* 667 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing 668 * is available. 669 */ 670 } 671 672 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 673 struct omap_dss_audio *audio, u32 pclk) 674 { 675 struct hdmi_audio_format audio_format; 676 struct hdmi_audio_dma audio_dma; 677 struct hdmi_core_audio_config acore; 678 int err, n, cts, channel_count; 679 unsigned int fs_nr; 680 bool word_length_16b = false; 681 682 if (!audio || !audio->iec || !audio->cea || !core) 683 return -EINVAL; 684 685 acore.iec60958_cfg = audio->iec; 686 /* 687 * In the IEC-60958 status word, check if the audio sample word length 688 * is 16-bit as several optimizations can be performed in such case. 689 */ 690 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)) 691 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16) 692 word_length_16b = true; 693 694 /* I2S configuration. See Phillips' specification */ 695 if (word_length_16b) 696 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT; 697 else 698 acore.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 699 /* 700 * The I2S input word length is twice the length given in the IEC-60958 701 * status word. If the word size is greater than 702 * 20 bits, increment by one. 703 */ 704 acore.i2s_cfg.in_length_bits = audio->iec->status[4] 705 & IEC958_AES4_CON_WORDLEN; 706 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24) 707 acore.i2s_cfg.in_length_bits++; 708 acore.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING; 709 acore.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM; 710 acore.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST; 711 acore.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT; 712 713 /* convert sample frequency to a number */ 714 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) { 715 case IEC958_AES3_CON_FS_32000: 716 fs_nr = 32000; 717 break; 718 case IEC958_AES3_CON_FS_44100: 719 fs_nr = 44100; 720 break; 721 case IEC958_AES3_CON_FS_48000: 722 fs_nr = 48000; 723 break; 724 case IEC958_AES3_CON_FS_88200: 725 fs_nr = 88200; 726 break; 727 case IEC958_AES3_CON_FS_96000: 728 fs_nr = 96000; 729 break; 730 case IEC958_AES3_CON_FS_176400: 731 fs_nr = 176400; 732 break; 733 case IEC958_AES3_CON_FS_192000: 734 fs_nr = 192000; 735 break; 736 default: 737 return -EINVAL; 738 } 739 740 err = hdmi_compute_acr(pclk, fs_nr, &n, &cts); 741 742 /* Audio clock regeneration settings */ 743 acore.n = n; 744 acore.cts = cts; 745 if (core->cts_swmode) { 746 acore.aud_par_busclk = 0; 747 acore.cts_mode = HDMI_AUDIO_CTS_MODE_SW; 748 acore.use_mclk = core->audio_use_mclk; 749 } else { 750 acore.aud_par_busclk = (((128 * 31) - 1) << 8); 751 acore.cts_mode = HDMI_AUDIO_CTS_MODE_HW; 752 acore.use_mclk = true; 753 } 754 755 if (acore.use_mclk) 756 acore.mclk_mode = HDMI_AUDIO_MCLK_128FS; 757 758 /* Audio channels settings */ 759 channel_count = (audio->cea->db1_ct_cc & 760 CEA861_AUDIO_INFOFRAME_DB1CC) + 1; 761 762 switch (channel_count) { 763 case 2: 764 audio_format.active_chnnls_msk = 0x03; 765 break; 766 case 3: 767 audio_format.active_chnnls_msk = 0x07; 768 break; 769 case 4: 770 audio_format.active_chnnls_msk = 0x0f; 771 break; 772 case 5: 773 audio_format.active_chnnls_msk = 0x1f; 774 break; 775 case 6: 776 audio_format.active_chnnls_msk = 0x3f; 777 break; 778 case 7: 779 audio_format.active_chnnls_msk = 0x7f; 780 break; 781 case 8: 782 audio_format.active_chnnls_msk = 0xff; 783 break; 784 default: 785 return -EINVAL; 786 } 787 788 /* 789 * the HDMI IP needs to enable four stereo channels when transmitting 790 * more than 2 audio channels. Similarly, the channel count in the 791 * Audio InfoFrame has to match the sample_present bits (some channels 792 * are padded with zeroes) 793 */ 794 if (channel_count == 2) { 795 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL; 796 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN; 797 acore.layout = HDMI_AUDIO_LAYOUT_2CH; 798 } else { 799 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS; 800 acore.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN | 801 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN | 802 HDMI_AUDIO_I2S_SD3_EN; 803 acore.layout = HDMI_AUDIO_LAYOUT_8CH; 804 audio->cea->db1_ct_cc = 7; 805 } 806 807 acore.en_spdif = false; 808 /* use sample frequency from channel status word */ 809 acore.fs_override = true; 810 /* enable ACR packets */ 811 acore.en_acr_pkt = true; 812 /* disable direct streaming digital audio */ 813 acore.en_dsd_audio = false; 814 /* use parallel audio interface */ 815 acore.en_parallel_aud_input = true; 816 817 /* DMA settings */ 818 if (word_length_16b) 819 audio_dma.transfer_size = 0x10; 820 else 821 audio_dma.transfer_size = 0x20; 822 audio_dma.block_size = 0xC0; 823 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA; 824 audio_dma.fifo_threshold = 0x20; /* in number of samples */ 825 826 /* audio FIFO format settings */ 827 if (word_length_16b) { 828 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES; 829 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS; 830 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT; 831 } else { 832 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE; 833 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS; 834 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT; 835 } 836 audio_format.type = HDMI_AUDIO_TYPE_LPCM; 837 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST; 838 /* disable start/stop signals of IEC 60958 blocks */ 839 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON; 840 841 /* configure DMA and audio FIFO format*/ 842 hdmi_wp_audio_config_dma(wp, &audio_dma); 843 hdmi_wp_audio_config_format(wp, &audio_format); 844 845 /* configure the core*/ 846 hdmi_core_audio_config(core, &acore); 847 848 /* configure CEA 861 audio infoframe*/ 849 hdmi_core_audio_infoframe_cfg(core, audio->cea); 850 851 return 0; 852 } 853 854 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 855 { 856 REG_FLD_MOD(hdmi_av_base(core), 857 HDMI_CORE_AV_AUD_MODE, true, 0, 0); 858 859 hdmi_wp_audio_core_req_enable(wp, true); 860 861 return 0; 862 } 863 864 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) 865 { 866 REG_FLD_MOD(hdmi_av_base(core), 867 HDMI_CORE_AV_AUD_MODE, false, 0, 0); 868 869 hdmi_wp_audio_core_req_enable(wp, false); 870 } 871 872 struct hdmi4_features { 873 bool cts_swmode; 874 bool audio_use_mclk; 875 }; 876 877 static const struct hdmi4_features hdmi4430_es1_features = { 878 .cts_swmode = false, 879 .audio_use_mclk = false, 880 }; 881 882 static const struct hdmi4_features hdmi4430_es2_features = { 883 .cts_swmode = true, 884 .audio_use_mclk = false, 885 }; 886 887 static const struct hdmi4_features hdmi4_features = { 888 .cts_swmode = true, 889 .audio_use_mclk = true, 890 }; 891 892 static const struct soc_device_attribute hdmi4_soc_devices[] = { 893 { 894 .machine = "OMAP4430", 895 .revision = "ES1.?", 896 .data = &hdmi4430_es1_features, 897 }, 898 { 899 .machine = "OMAP4430", 900 .revision = "ES2.?", 901 .data = &hdmi4430_es2_features, 902 }, 903 { 904 .family = "OMAP4", 905 .data = &hdmi4_features, 906 }, 907 { /* sentinel */ } 908 }; 909 910 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core) 911 { 912 const struct hdmi4_features *features; 913 struct resource *res; 914 const struct soc_device_attribute *soc; 915 916 soc = soc_device_match(hdmi4_soc_devices); 917 if (!soc) 918 return -ENODEV; 919 920 features = soc->data; 921 core->cts_swmode = features->cts_swmode; 922 core->audio_use_mclk = features->audio_use_mclk; 923 924 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 925 core->base = devm_ioremap_resource(&pdev->dev, res); 926 if (IS_ERR(core->base)) 927 return PTR_ERR(core->base); 928 929 return 0; 930 } 931