1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NV3051D MIPI-DSI panel driver for Anbernic RG353x 4 * Copyright (C) 2022 Chris Morgan 5 * 6 * based on 7 * 8 * Elida kd35t133 3.5" MIPI-DSI panel driver 9 * Copyright (C) Theobroma Systems 2020 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/media-bus-format.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <video/display_timing.h> 20 #include <video/mipi_display.h> 21 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_modes.h> 24 #include <drm/drm_panel.h> 25 26 struct nv3051d_panel_info { 27 const struct drm_display_mode *display_modes; 28 unsigned int num_modes; 29 u16 width_mm, height_mm; 30 u32 bus_flags; 31 }; 32 33 struct panel_nv3051d { 34 struct device *dev; 35 struct drm_panel panel; 36 struct gpio_desc *reset_gpio; 37 const struct nv3051d_panel_info *panel_info; 38 struct regulator *vdd; 39 }; 40 41 static inline struct panel_nv3051d *panel_to_panelnv3051d(struct drm_panel *panel) 42 { 43 return container_of(panel, struct panel_nv3051d, panel); 44 } 45 46 static int panel_nv3051d_init_sequence(struct panel_nv3051d *ctx) 47 { 48 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 49 50 /* 51 * Init sequence was supplied by device vendor with no 52 * documentation. 53 */ 54 55 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); 56 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); 57 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x01); 58 mipi_dsi_dcs_write_seq(dsi, 0xE3, 0x00); 59 mipi_dsi_dcs_write_seq(dsi, 0x03, 0x40); 60 mipi_dsi_dcs_write_seq(dsi, 0x04, 0x00); 61 mipi_dsi_dcs_write_seq(dsi, 0x05, 0x03); 62 mipi_dsi_dcs_write_seq(dsi, 0x24, 0x12); 63 mipi_dsi_dcs_write_seq(dsi, 0x25, 0x1E); 64 mipi_dsi_dcs_write_seq(dsi, 0x26, 0x28); 65 mipi_dsi_dcs_write_seq(dsi, 0x27, 0x52); 66 mipi_dsi_dcs_write_seq(dsi, 0x28, 0x57); 67 mipi_dsi_dcs_write_seq(dsi, 0x29, 0x01); 68 mipi_dsi_dcs_write_seq(dsi, 0x2A, 0xDF); 69 mipi_dsi_dcs_write_seq(dsi, 0x38, 0x9C); 70 mipi_dsi_dcs_write_seq(dsi, 0x39, 0xA7); 71 mipi_dsi_dcs_write_seq(dsi, 0x3A, 0x53); 72 mipi_dsi_dcs_write_seq(dsi, 0x44, 0x00); 73 mipi_dsi_dcs_write_seq(dsi, 0x49, 0x3C); 74 mipi_dsi_dcs_write_seq(dsi, 0x59, 0xFE); 75 mipi_dsi_dcs_write_seq(dsi, 0x5C, 0x00); 76 mipi_dsi_dcs_write_seq(dsi, 0x91, 0x77); 77 mipi_dsi_dcs_write_seq(dsi, 0x92, 0x77); 78 mipi_dsi_dcs_write_seq(dsi, 0xA0, 0x55); 79 mipi_dsi_dcs_write_seq(dsi, 0xA1, 0x50); 80 mipi_dsi_dcs_write_seq(dsi, 0xA4, 0x9C); 81 mipi_dsi_dcs_write_seq(dsi, 0xA7, 0x02); 82 mipi_dsi_dcs_write_seq(dsi, 0xA8, 0x01); 83 mipi_dsi_dcs_write_seq(dsi, 0xA9, 0x01); 84 mipi_dsi_dcs_write_seq(dsi, 0xAA, 0xFC); 85 mipi_dsi_dcs_write_seq(dsi, 0xAB, 0x28); 86 mipi_dsi_dcs_write_seq(dsi, 0xAC, 0x06); 87 mipi_dsi_dcs_write_seq(dsi, 0xAD, 0x06); 88 mipi_dsi_dcs_write_seq(dsi, 0xAE, 0x06); 89 mipi_dsi_dcs_write_seq(dsi, 0xAF, 0x03); 90 mipi_dsi_dcs_write_seq(dsi, 0xB0, 0x08); 91 mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x26); 92 mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x28); 93 mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x28); 94 mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x33); 95 mipi_dsi_dcs_write_seq(dsi, 0xB5, 0x08); 96 mipi_dsi_dcs_write_seq(dsi, 0xB6, 0x26); 97 mipi_dsi_dcs_write_seq(dsi, 0xB7, 0x08); 98 mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x26); 99 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); 100 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); 101 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x02); 102 mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x0E); 103 mipi_dsi_dcs_write_seq(dsi, 0xD1, 0x0E); 104 mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x29); 105 mipi_dsi_dcs_write_seq(dsi, 0xD4, 0x2B); 106 mipi_dsi_dcs_write_seq(dsi, 0xB2, 0x0C); 107 mipi_dsi_dcs_write_seq(dsi, 0xD2, 0x0A); 108 mipi_dsi_dcs_write_seq(dsi, 0xB3, 0x28); 109 mipi_dsi_dcs_write_seq(dsi, 0xD3, 0x28); 110 mipi_dsi_dcs_write_seq(dsi, 0xB6, 0x11); 111 mipi_dsi_dcs_write_seq(dsi, 0xD6, 0x0D); 112 mipi_dsi_dcs_write_seq(dsi, 0xB7, 0x32); 113 mipi_dsi_dcs_write_seq(dsi, 0xD7, 0x30); 114 mipi_dsi_dcs_write_seq(dsi, 0xC1, 0x04); 115 mipi_dsi_dcs_write_seq(dsi, 0xE1, 0x06); 116 mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x0A); 117 mipi_dsi_dcs_write_seq(dsi, 0xD8, 0x0A); 118 mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x01); 119 mipi_dsi_dcs_write_seq(dsi, 0xD9, 0x01); 120 mipi_dsi_dcs_write_seq(dsi, 0xBD, 0x13); 121 mipi_dsi_dcs_write_seq(dsi, 0xDD, 0x13); 122 mipi_dsi_dcs_write_seq(dsi, 0xBC, 0x11); 123 mipi_dsi_dcs_write_seq(dsi, 0xDC, 0x11); 124 mipi_dsi_dcs_write_seq(dsi, 0xBB, 0x0F); 125 mipi_dsi_dcs_write_seq(dsi, 0xDB, 0x0F); 126 mipi_dsi_dcs_write_seq(dsi, 0xBA, 0x0F); 127 mipi_dsi_dcs_write_seq(dsi, 0xDA, 0x0F); 128 mipi_dsi_dcs_write_seq(dsi, 0xBE, 0x18); 129 mipi_dsi_dcs_write_seq(dsi, 0xDE, 0x18); 130 mipi_dsi_dcs_write_seq(dsi, 0xBF, 0x0F); 131 mipi_dsi_dcs_write_seq(dsi, 0xDF, 0x0F); 132 mipi_dsi_dcs_write_seq(dsi, 0xC0, 0x17); 133 mipi_dsi_dcs_write_seq(dsi, 0xE0, 0x17); 134 mipi_dsi_dcs_write_seq(dsi, 0xB5, 0x3B); 135 mipi_dsi_dcs_write_seq(dsi, 0xD5, 0x3C); 136 mipi_dsi_dcs_write_seq(dsi, 0xB0, 0x0B); 137 mipi_dsi_dcs_write_seq(dsi, 0xD0, 0x0C); 138 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); 139 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); 140 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x03); 141 mipi_dsi_dcs_write_seq(dsi, 0x00, 0x2A); 142 mipi_dsi_dcs_write_seq(dsi, 0x01, 0x2A); 143 mipi_dsi_dcs_write_seq(dsi, 0x02, 0x2A); 144 mipi_dsi_dcs_write_seq(dsi, 0x03, 0x2A); 145 mipi_dsi_dcs_write_seq(dsi, 0x04, 0x61); 146 mipi_dsi_dcs_write_seq(dsi, 0x05, 0x80); 147 mipi_dsi_dcs_write_seq(dsi, 0x06, 0xC7); 148 mipi_dsi_dcs_write_seq(dsi, 0x07, 0x01); 149 mipi_dsi_dcs_write_seq(dsi, 0x08, 0x82); 150 mipi_dsi_dcs_write_seq(dsi, 0x09, 0x83); 151 mipi_dsi_dcs_write_seq(dsi, 0x30, 0x2A); 152 mipi_dsi_dcs_write_seq(dsi, 0x31, 0x2A); 153 mipi_dsi_dcs_write_seq(dsi, 0x32, 0x2A); 154 mipi_dsi_dcs_write_seq(dsi, 0x33, 0x2A); 155 mipi_dsi_dcs_write_seq(dsi, 0x34, 0x61); 156 mipi_dsi_dcs_write_seq(dsi, 0x35, 0xC5); 157 mipi_dsi_dcs_write_seq(dsi, 0x36, 0x80); 158 mipi_dsi_dcs_write_seq(dsi, 0x37, 0x23); 159 mipi_dsi_dcs_write_seq(dsi, 0x40, 0x82); 160 mipi_dsi_dcs_write_seq(dsi, 0x41, 0x83); 161 mipi_dsi_dcs_write_seq(dsi, 0x42, 0x80); 162 mipi_dsi_dcs_write_seq(dsi, 0x43, 0x81); 163 mipi_dsi_dcs_write_seq(dsi, 0x44, 0x11); 164 mipi_dsi_dcs_write_seq(dsi, 0x45, 0xF2); 165 mipi_dsi_dcs_write_seq(dsi, 0x46, 0xF1); 166 mipi_dsi_dcs_write_seq(dsi, 0x47, 0x11); 167 mipi_dsi_dcs_write_seq(dsi, 0x48, 0xF4); 168 mipi_dsi_dcs_write_seq(dsi, 0x49, 0xF3); 169 mipi_dsi_dcs_write_seq(dsi, 0x50, 0x02); 170 mipi_dsi_dcs_write_seq(dsi, 0x51, 0x01); 171 mipi_dsi_dcs_write_seq(dsi, 0x52, 0x04); 172 mipi_dsi_dcs_write_seq(dsi, 0x53, 0x03); 173 mipi_dsi_dcs_write_seq(dsi, 0x54, 0x11); 174 mipi_dsi_dcs_write_seq(dsi, 0x55, 0xF6); 175 mipi_dsi_dcs_write_seq(dsi, 0x56, 0xF5); 176 mipi_dsi_dcs_write_seq(dsi, 0x57, 0x11); 177 mipi_dsi_dcs_write_seq(dsi, 0x58, 0xF8); 178 mipi_dsi_dcs_write_seq(dsi, 0x59, 0xF7); 179 mipi_dsi_dcs_write_seq(dsi, 0x7E, 0x02); 180 mipi_dsi_dcs_write_seq(dsi, 0x7F, 0x80); 181 mipi_dsi_dcs_write_seq(dsi, 0xE0, 0x5A); 182 mipi_dsi_dcs_write_seq(dsi, 0xB1, 0x00); 183 mipi_dsi_dcs_write_seq(dsi, 0xB4, 0x0E); 184 mipi_dsi_dcs_write_seq(dsi, 0xB5, 0x0F); 185 mipi_dsi_dcs_write_seq(dsi, 0xB6, 0x04); 186 mipi_dsi_dcs_write_seq(dsi, 0xB7, 0x07); 187 mipi_dsi_dcs_write_seq(dsi, 0xB8, 0x06); 188 mipi_dsi_dcs_write_seq(dsi, 0xB9, 0x05); 189 mipi_dsi_dcs_write_seq(dsi, 0xBA, 0x0F); 190 mipi_dsi_dcs_write_seq(dsi, 0xC7, 0x00); 191 mipi_dsi_dcs_write_seq(dsi, 0xCA, 0x0E); 192 mipi_dsi_dcs_write_seq(dsi, 0xCB, 0x0F); 193 mipi_dsi_dcs_write_seq(dsi, 0xCC, 0x04); 194 mipi_dsi_dcs_write_seq(dsi, 0xCD, 0x07); 195 mipi_dsi_dcs_write_seq(dsi, 0xCE, 0x06); 196 mipi_dsi_dcs_write_seq(dsi, 0xCF, 0x05); 197 mipi_dsi_dcs_write_seq(dsi, 0xD0, 0x0F); 198 mipi_dsi_dcs_write_seq(dsi, 0x81, 0x0F); 199 mipi_dsi_dcs_write_seq(dsi, 0x84, 0x0E); 200 mipi_dsi_dcs_write_seq(dsi, 0x85, 0x0F); 201 mipi_dsi_dcs_write_seq(dsi, 0x86, 0x07); 202 mipi_dsi_dcs_write_seq(dsi, 0x87, 0x04); 203 mipi_dsi_dcs_write_seq(dsi, 0x88, 0x05); 204 mipi_dsi_dcs_write_seq(dsi, 0x89, 0x06); 205 mipi_dsi_dcs_write_seq(dsi, 0x8A, 0x00); 206 mipi_dsi_dcs_write_seq(dsi, 0x97, 0x0F); 207 mipi_dsi_dcs_write_seq(dsi, 0x9A, 0x0E); 208 mipi_dsi_dcs_write_seq(dsi, 0x9B, 0x0F); 209 mipi_dsi_dcs_write_seq(dsi, 0x9C, 0x07); 210 mipi_dsi_dcs_write_seq(dsi, 0x9D, 0x04); 211 mipi_dsi_dcs_write_seq(dsi, 0x9E, 0x05); 212 mipi_dsi_dcs_write_seq(dsi, 0x9F, 0x06); 213 mipi_dsi_dcs_write_seq(dsi, 0xA0, 0x00); 214 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); 215 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); 216 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x02); 217 mipi_dsi_dcs_write_seq(dsi, 0x01, 0x01); 218 mipi_dsi_dcs_write_seq(dsi, 0x02, 0xDA); 219 mipi_dsi_dcs_write_seq(dsi, 0x03, 0xBA); 220 mipi_dsi_dcs_write_seq(dsi, 0x04, 0xA8); 221 mipi_dsi_dcs_write_seq(dsi, 0x05, 0x9A); 222 mipi_dsi_dcs_write_seq(dsi, 0x06, 0x70); 223 mipi_dsi_dcs_write_seq(dsi, 0x07, 0xFF); 224 mipi_dsi_dcs_write_seq(dsi, 0x08, 0x91); 225 mipi_dsi_dcs_write_seq(dsi, 0x09, 0x90); 226 mipi_dsi_dcs_write_seq(dsi, 0x0A, 0xFF); 227 mipi_dsi_dcs_write_seq(dsi, 0x0B, 0x8F); 228 mipi_dsi_dcs_write_seq(dsi, 0x0C, 0x60); 229 mipi_dsi_dcs_write_seq(dsi, 0x0D, 0x58); 230 mipi_dsi_dcs_write_seq(dsi, 0x0E, 0x48); 231 mipi_dsi_dcs_write_seq(dsi, 0x0F, 0x38); 232 mipi_dsi_dcs_write_seq(dsi, 0x10, 0x2B); 233 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x30); 234 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x52); 235 mipi_dsi_dcs_write_seq(dsi, 0xFF, 0x00); 236 mipi_dsi_dcs_write_seq(dsi, 0x36, 0x02); 237 mipi_dsi_dcs_write_seq(dsi, 0x3A, 0x70); 238 239 dev_dbg(ctx->dev, "Panel init sequence done\n"); 240 241 return 0; 242 } 243 244 static int panel_nv3051d_unprepare(struct drm_panel *panel) 245 { 246 struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel); 247 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 248 int ret; 249 250 ret = mipi_dsi_dcs_set_display_off(dsi); 251 if (ret < 0) 252 dev_err(ctx->dev, "failed to set display off: %d\n", ret); 253 254 msleep(20); 255 256 ret = mipi_dsi_dcs_enter_sleep_mode(dsi); 257 if (ret < 0) { 258 dev_err(ctx->dev, "failed to enter sleep mode: %d\n", ret); 259 return ret; 260 } 261 262 usleep_range(10000, 15000); 263 264 regulator_disable(ctx->vdd); 265 266 return 0; 267 } 268 269 static int panel_nv3051d_prepare(struct drm_panel *panel) 270 { 271 struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel); 272 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); 273 int ret; 274 275 dev_dbg(ctx->dev, "Resetting the panel\n"); 276 ret = regulator_enable(ctx->vdd); 277 if (ret < 0) { 278 dev_err(ctx->dev, "Failed to enable vdd supply: %d\n", ret); 279 return ret; 280 } 281 282 usleep_range(2000, 3000); 283 gpiod_set_value_cansleep(ctx->reset_gpio, 1); 284 msleep(150); 285 gpiod_set_value_cansleep(ctx->reset_gpio, 0); 286 msleep(20); 287 288 ret = panel_nv3051d_init_sequence(ctx); 289 if (ret < 0) { 290 dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret); 291 goto disable_vdd; 292 } 293 294 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); 295 if (ret < 0) { 296 dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret); 297 goto disable_vdd; 298 } 299 300 msleep(200); 301 302 ret = mipi_dsi_dcs_set_display_on(dsi); 303 if (ret < 0) { 304 dev_err(ctx->dev, "Failed to set display on: %d\n", ret); 305 goto disable_vdd; 306 } 307 308 usleep_range(10000, 15000); 309 310 return 0; 311 312 disable_vdd: 313 regulator_disable(ctx->vdd); 314 return ret; 315 } 316 317 static int panel_nv3051d_get_modes(struct drm_panel *panel, 318 struct drm_connector *connector) 319 { 320 struct panel_nv3051d *ctx = panel_to_panelnv3051d(panel); 321 const struct nv3051d_panel_info *panel_info = ctx->panel_info; 322 struct drm_display_mode *mode; 323 unsigned int i; 324 325 for (i = 0; i < panel_info->num_modes; i++) { 326 mode = drm_mode_duplicate(connector->dev, 327 &panel_info->display_modes[i]); 328 if (!mode) 329 return -ENOMEM; 330 331 drm_mode_set_name(mode); 332 333 mode->type = DRM_MODE_TYPE_DRIVER; 334 if (panel_info->num_modes == 1) 335 mode->type |= DRM_MODE_TYPE_PREFERRED; 336 337 drm_mode_probed_add(connector, mode); 338 } 339 340 connector->display_info.bpc = 8; 341 connector->display_info.width_mm = panel_info->width_mm; 342 connector->display_info.height_mm = panel_info->height_mm; 343 connector->display_info.bus_flags = panel_info->bus_flags; 344 345 return panel_info->num_modes; 346 } 347 348 static const struct drm_panel_funcs panel_nv3051d_funcs = { 349 .unprepare = panel_nv3051d_unprepare, 350 .prepare = panel_nv3051d_prepare, 351 .get_modes = panel_nv3051d_get_modes, 352 }; 353 354 static int panel_nv3051d_probe(struct mipi_dsi_device *dsi) 355 { 356 struct device *dev = &dsi->dev; 357 struct panel_nv3051d *ctx; 358 int ret; 359 360 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 361 if (!ctx) 362 return -ENOMEM; 363 364 ctx->dev = dev; 365 366 ctx->panel_info = of_device_get_match_data(dev); 367 if (!ctx->panel_info) 368 return -EINVAL; 369 370 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 371 if (IS_ERR(ctx->reset_gpio)) { 372 dev_err(dev, "cannot get reset gpio\n"); 373 return PTR_ERR(ctx->reset_gpio); 374 } 375 376 ctx->vdd = devm_regulator_get(dev, "vdd"); 377 if (IS_ERR(ctx->vdd)) { 378 ret = PTR_ERR(ctx->vdd); 379 if (ret != -EPROBE_DEFER) 380 dev_err(dev, "Failed to request vdd regulator: %d\n", ret); 381 return ret; 382 } 383 384 mipi_dsi_set_drvdata(dsi, ctx); 385 386 dsi->lanes = 4; 387 dsi->format = MIPI_DSI_FMT_RGB888; 388 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 389 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET; 390 391 /* 392 * The panel in the RG351V is identical to the 353P, except it 393 * requires MIPI_DSI_CLOCK_NON_CONTINUOUS to operate correctly. 394 */ 395 if (of_device_is_compatible(dev->of_node, "anbernic,rg351v-panel")) 396 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 397 398 drm_panel_init(&ctx->panel, &dsi->dev, &panel_nv3051d_funcs, 399 DRM_MODE_CONNECTOR_DSI); 400 401 ret = drm_panel_of_backlight(&ctx->panel); 402 if (ret) 403 return ret; 404 405 drm_panel_add(&ctx->panel); 406 407 ret = mipi_dsi_attach(dsi); 408 if (ret < 0) { 409 dev_err(dev, "mipi_dsi_attach failed: %d\n", ret); 410 drm_panel_remove(&ctx->panel); 411 return ret; 412 } 413 414 return 0; 415 } 416 417 static void panel_nv3051d_shutdown(struct mipi_dsi_device *dsi) 418 { 419 struct panel_nv3051d *ctx = mipi_dsi_get_drvdata(dsi); 420 int ret; 421 422 ret = drm_panel_unprepare(&ctx->panel); 423 if (ret < 0) 424 dev_err(&dsi->dev, "Failed to unprepare panel: %d\n", ret); 425 426 ret = drm_panel_disable(&ctx->panel); 427 if (ret < 0) 428 dev_err(&dsi->dev, "Failed to disable panel: %d\n", ret); 429 } 430 431 static void panel_nv3051d_remove(struct mipi_dsi_device *dsi) 432 { 433 struct panel_nv3051d *ctx = mipi_dsi_get_drvdata(dsi); 434 int ret; 435 436 panel_nv3051d_shutdown(dsi); 437 438 ret = mipi_dsi_detach(dsi); 439 if (ret < 0) 440 dev_err(&dsi->dev, "Failed to detach from DSI host: %d\n", ret); 441 442 drm_panel_remove(&ctx->panel); 443 } 444 445 static const struct drm_display_mode nv3051d_rgxx3_modes[] = { 446 { /* 120hz */ 447 .hdisplay = 640, 448 .hsync_start = 640 + 40, 449 .hsync_end = 640 + 40 + 2, 450 .htotal = 640 + 40 + 2 + 80, 451 .vdisplay = 480, 452 .vsync_start = 480 + 18, 453 .vsync_end = 480 + 18 + 2, 454 .vtotal = 480 + 18 + 2 + 28, 455 .clock = 48300, 456 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 457 }, 458 { /* 100hz */ 459 .hdisplay = 640, 460 .hsync_start = 640 + 40, 461 .hsync_end = 640 + 40 + 2, 462 .htotal = 640 + 40 + 2 + 80, 463 .vdisplay = 480, 464 .vsync_start = 480 + 18, 465 .vsync_end = 480 + 18 + 2, 466 .vtotal = 480 + 18 + 2 + 28, 467 .clock = 40250, 468 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 469 }, 470 { /* 60hz */ 471 .hdisplay = 640, 472 .hsync_start = 640 + 40, 473 .hsync_end = 640 + 40 + 2, 474 .htotal = 640 + 40 + 2 + 80, 475 .vdisplay = 480, 476 .vsync_start = 480 + 18, 477 .vsync_end = 480 + 18 + 2, 478 .vtotal = 480 + 18 + 2 + 28, 479 .clock = 24150, 480 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 481 }, 482 }; 483 484 static const struct nv3051d_panel_info nv3051d_rgxx3_info = { 485 .display_modes = nv3051d_rgxx3_modes, 486 .num_modes = ARRAY_SIZE(nv3051d_rgxx3_modes), 487 .width_mm = 70, 488 .height_mm = 57, 489 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 490 }; 491 492 static const struct of_device_id newvision_nv3051d_of_match[] = { 493 { .compatible = "newvision,nv3051d", .data = &nv3051d_rgxx3_info }, 494 { /* sentinel */ } 495 }; 496 MODULE_DEVICE_TABLE(of, newvision_nv3051d_of_match); 497 498 static struct mipi_dsi_driver newvision_nv3051d_driver = { 499 .driver = { 500 .name = "panel-newvision-nv3051d", 501 .of_match_table = newvision_nv3051d_of_match, 502 }, 503 .probe = panel_nv3051d_probe, 504 .remove = panel_nv3051d_remove, 505 .shutdown = panel_nv3051d_shutdown, 506 }; 507 module_mipi_dsi_driver(newvision_nv3051d_driver); 508 509 MODULE_AUTHOR("Chris Morgan <macromorgan@hotmail.com>"); 510 MODULE_DESCRIPTION("DRM driver for Newvision NV3051D based MIPI DSI panels"); 511 MODULE_LICENSE("GPL"); 512