1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 44 /** 45 * struct panel_desc - Describes a simple panel. 46 */ 47 struct panel_desc { 48 /** 49 * @modes: Pointer to array of fixed modes appropriate for this panel. 50 * 51 * If only one mode then this can just be the address of the mode. 52 * NOTE: cannot be used with "timings" and also if this is specified 53 * then you cannot override the mode in the device tree. 54 */ 55 const struct drm_display_mode *modes; 56 57 /** @num_modes: Number of elements in modes array. */ 58 unsigned int num_modes; 59 60 /** 61 * @timings: Pointer to array of display timings 62 * 63 * NOTE: cannot be used with "modes" and also these will be used to 64 * validate a device tree override if one is present. 65 */ 66 const struct display_timing *timings; 67 68 /** @num_timings: Number of elements in timings array. */ 69 unsigned int num_timings; 70 71 /** @bpc: Bits per color. */ 72 unsigned int bpc; 73 74 /** @size: Structure containing the physical size of this panel. */ 75 struct { 76 /** 77 * @size.width: Width (in mm) of the active display area. 78 */ 79 unsigned int width; 80 81 /** 82 * @size.height: Height (in mm) of the active display area. 83 */ 84 unsigned int height; 85 } size; 86 87 /** @delay: Structure containing various delay values for this panel. */ 88 struct { 89 /** 90 * @delay.prepare: Time for the panel to become ready. 91 * 92 * The time (in milliseconds) that it takes for the panel to 93 * become ready and start receiving video data 94 */ 95 unsigned int prepare; 96 97 /** 98 * @delay.enable: Time for the panel to display a valid frame. 99 * 100 * The time (in milliseconds) that it takes for the panel to 101 * display the first valid frame after starting to receive 102 * video data. 103 */ 104 unsigned int enable; 105 106 /** 107 * @delay.disable: Time for the panel to turn the display off. 108 * 109 * The time (in milliseconds) that it takes for the panel to 110 * turn the display off (no content is visible). 111 */ 112 unsigned int disable; 113 114 /** 115 * @delay.unprepare: Time to power down completely. 116 * 117 * The time (in milliseconds) that it takes for the panel 118 * to power itself down completely. 119 * 120 * This time is used to prevent a future "prepare" from 121 * starting until at least this many milliseconds has passed. 122 * If at prepare time less time has passed since unprepare 123 * finished, the driver waits for the remaining time. 124 */ 125 unsigned int unprepare; 126 } delay; 127 128 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 129 u32 bus_format; 130 131 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 132 u32 bus_flags; 133 134 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 135 int connector_type; 136 }; 137 138 struct panel_simple { 139 struct drm_panel base; 140 bool enabled; 141 142 bool prepared; 143 144 ktime_t unprepared_time; 145 146 const struct panel_desc *desc; 147 148 struct regulator *supply; 149 struct i2c_adapter *ddc; 150 151 struct gpio_desc *enable_gpio; 152 153 struct edid *edid; 154 155 struct drm_display_mode override_mode; 156 157 enum drm_panel_orientation orientation; 158 }; 159 160 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 161 { 162 return container_of(panel, struct panel_simple, base); 163 } 164 165 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 166 struct drm_connector *connector) 167 { 168 struct drm_display_mode *mode; 169 unsigned int i, num = 0; 170 171 for (i = 0; i < panel->desc->num_timings; i++) { 172 const struct display_timing *dt = &panel->desc->timings[i]; 173 struct videomode vm; 174 175 videomode_from_timing(dt, &vm); 176 mode = drm_mode_create(connector->dev); 177 if (!mode) { 178 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 179 dt->hactive.typ, dt->vactive.typ); 180 continue; 181 } 182 183 drm_display_mode_from_videomode(&vm, mode); 184 185 mode->type |= DRM_MODE_TYPE_DRIVER; 186 187 if (panel->desc->num_timings == 1) 188 mode->type |= DRM_MODE_TYPE_PREFERRED; 189 190 drm_mode_probed_add(connector, mode); 191 num++; 192 } 193 194 return num; 195 } 196 197 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 198 struct drm_connector *connector) 199 { 200 struct drm_display_mode *mode; 201 unsigned int i, num = 0; 202 203 for (i = 0; i < panel->desc->num_modes; i++) { 204 const struct drm_display_mode *m = &panel->desc->modes[i]; 205 206 mode = drm_mode_duplicate(connector->dev, m); 207 if (!mode) { 208 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 209 m->hdisplay, m->vdisplay, 210 drm_mode_vrefresh(m)); 211 continue; 212 } 213 214 mode->type |= DRM_MODE_TYPE_DRIVER; 215 216 if (panel->desc->num_modes == 1) 217 mode->type |= DRM_MODE_TYPE_PREFERRED; 218 219 drm_mode_set_name(mode); 220 221 drm_mode_probed_add(connector, mode); 222 num++; 223 } 224 225 return num; 226 } 227 228 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 229 struct drm_connector *connector) 230 { 231 struct drm_display_mode *mode; 232 bool has_override = panel->override_mode.type; 233 unsigned int num = 0; 234 235 if (!panel->desc) 236 return 0; 237 238 if (has_override) { 239 mode = drm_mode_duplicate(connector->dev, 240 &panel->override_mode); 241 if (mode) { 242 drm_mode_probed_add(connector, mode); 243 num = 1; 244 } else { 245 dev_err(panel->base.dev, "failed to add override mode\n"); 246 } 247 } 248 249 /* Only add timings if override was not there or failed to validate */ 250 if (num == 0 && panel->desc->num_timings) 251 num = panel_simple_get_timings_modes(panel, connector); 252 253 /* 254 * Only add fixed modes if timings/override added no mode. 255 * 256 * We should only ever have either the display timings specified 257 * or a fixed mode. Anything else is rather bogus. 258 */ 259 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 260 if (num == 0) 261 num = panel_simple_get_display_modes(panel, connector); 262 263 connector->display_info.bpc = panel->desc->bpc; 264 connector->display_info.width_mm = panel->desc->size.width; 265 connector->display_info.height_mm = panel->desc->size.height; 266 if (panel->desc->bus_format) 267 drm_display_info_set_bus_formats(&connector->display_info, 268 &panel->desc->bus_format, 1); 269 connector->display_info.bus_flags = panel->desc->bus_flags; 270 271 return num; 272 } 273 274 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 275 { 276 ktime_t now_ktime, min_ktime; 277 278 if (!min_ms) 279 return; 280 281 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 282 now_ktime = ktime_get_boottime(); 283 284 if (ktime_before(now_ktime, min_ktime)) 285 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 286 } 287 288 static int panel_simple_disable(struct drm_panel *panel) 289 { 290 struct panel_simple *p = to_panel_simple(panel); 291 292 if (!p->enabled) 293 return 0; 294 295 if (p->desc->delay.disable) 296 msleep(p->desc->delay.disable); 297 298 p->enabled = false; 299 300 return 0; 301 } 302 303 static int panel_simple_suspend(struct device *dev) 304 { 305 struct panel_simple *p = dev_get_drvdata(dev); 306 307 gpiod_set_value_cansleep(p->enable_gpio, 0); 308 regulator_disable(p->supply); 309 p->unprepared_time = ktime_get_boottime(); 310 311 kfree(p->edid); 312 p->edid = NULL; 313 314 return 0; 315 } 316 317 static int panel_simple_unprepare(struct drm_panel *panel) 318 { 319 struct panel_simple *p = to_panel_simple(panel); 320 int ret; 321 322 /* Unpreparing when already unprepared is a no-op */ 323 if (!p->prepared) 324 return 0; 325 326 pm_runtime_mark_last_busy(panel->dev); 327 ret = pm_runtime_put_autosuspend(panel->dev); 328 if (ret < 0) 329 return ret; 330 p->prepared = false; 331 332 return 0; 333 } 334 335 static int panel_simple_resume(struct device *dev) 336 { 337 struct panel_simple *p = dev_get_drvdata(dev); 338 int err; 339 340 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 341 342 err = regulator_enable(p->supply); 343 if (err < 0) { 344 dev_err(dev, "failed to enable supply: %d\n", err); 345 return err; 346 } 347 348 gpiod_set_value_cansleep(p->enable_gpio, 1); 349 350 if (p->desc->delay.prepare) 351 msleep(p->desc->delay.prepare); 352 353 return 0; 354 } 355 356 static int panel_simple_prepare(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 int ret; 360 361 /* Preparing when already prepared is a no-op */ 362 if (p->prepared) 363 return 0; 364 365 ret = pm_runtime_get_sync(panel->dev); 366 if (ret < 0) { 367 pm_runtime_put_autosuspend(panel->dev); 368 return ret; 369 } 370 371 p->prepared = true; 372 373 return 0; 374 } 375 376 static int panel_simple_enable(struct drm_panel *panel) 377 { 378 struct panel_simple *p = to_panel_simple(panel); 379 380 if (p->enabled) 381 return 0; 382 383 if (p->desc->delay.enable) 384 msleep(p->desc->delay.enable); 385 386 p->enabled = true; 387 388 return 0; 389 } 390 391 static int panel_simple_get_modes(struct drm_panel *panel, 392 struct drm_connector *connector) 393 { 394 struct panel_simple *p = to_panel_simple(panel); 395 int num = 0; 396 397 /* probe EDID if a DDC bus is available */ 398 if (p->ddc) { 399 pm_runtime_get_sync(panel->dev); 400 401 if (!p->edid) 402 p->edid = drm_get_edid(connector, p->ddc); 403 404 if (p->edid) 405 num += drm_add_edid_modes(connector, p->edid); 406 407 pm_runtime_mark_last_busy(panel->dev); 408 pm_runtime_put_autosuspend(panel->dev); 409 } 410 411 /* add hard-coded panel modes */ 412 num += panel_simple_get_non_edid_modes(p, connector); 413 414 /* 415 * TODO: Remove once all drm drivers call 416 * drm_connector_set_orientation_from_panel() 417 */ 418 drm_connector_set_panel_orientation(connector, p->orientation); 419 420 return num; 421 } 422 423 static int panel_simple_get_timings(struct drm_panel *panel, 424 unsigned int num_timings, 425 struct display_timing *timings) 426 { 427 struct panel_simple *p = to_panel_simple(panel); 428 unsigned int i; 429 430 if (p->desc->num_timings < num_timings) 431 num_timings = p->desc->num_timings; 432 433 if (timings) 434 for (i = 0; i < num_timings; i++) 435 timings[i] = p->desc->timings[i]; 436 437 return p->desc->num_timings; 438 } 439 440 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 441 { 442 struct panel_simple *p = to_panel_simple(panel); 443 444 return p->orientation; 445 } 446 447 static const struct drm_panel_funcs panel_simple_funcs = { 448 .disable = panel_simple_disable, 449 .unprepare = panel_simple_unprepare, 450 .prepare = panel_simple_prepare, 451 .enable = panel_simple_enable, 452 .get_modes = panel_simple_get_modes, 453 .get_orientation = panel_simple_get_orientation, 454 .get_timings = panel_simple_get_timings, 455 }; 456 457 static struct panel_desc panel_dpi; 458 459 static int panel_dpi_probe(struct device *dev, 460 struct panel_simple *panel) 461 { 462 struct display_timing *timing; 463 const struct device_node *np; 464 struct panel_desc *desc; 465 unsigned int bus_flags; 466 struct videomode vm; 467 int ret; 468 469 np = dev->of_node; 470 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 471 if (!desc) 472 return -ENOMEM; 473 474 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 475 if (!timing) 476 return -ENOMEM; 477 478 ret = of_get_display_timing(np, "panel-timing", timing); 479 if (ret < 0) { 480 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 481 np); 482 return ret; 483 } 484 485 desc->timings = timing; 486 desc->num_timings = 1; 487 488 of_property_read_u32(np, "width-mm", &desc->size.width); 489 of_property_read_u32(np, "height-mm", &desc->size.height); 490 491 /* Extract bus_flags from display_timing */ 492 bus_flags = 0; 493 vm.flags = timing->flags; 494 drm_bus_flags_from_videomode(&vm, &bus_flags); 495 desc->bus_flags = bus_flags; 496 497 /* We do not know the connector for the DT node, so guess it */ 498 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 499 500 panel->desc = desc; 501 502 return 0; 503 } 504 505 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 506 (to_check->field.typ >= bounds->field.min && \ 507 to_check->field.typ <= bounds->field.max) 508 static void panel_simple_parse_panel_timing_node(struct device *dev, 509 struct panel_simple *panel, 510 const struct display_timing *ot) 511 { 512 const struct panel_desc *desc = panel->desc; 513 struct videomode vm; 514 unsigned int i; 515 516 if (WARN_ON(desc->num_modes)) { 517 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 518 return; 519 } 520 if (WARN_ON(!desc->num_timings)) { 521 dev_err(dev, "Reject override mode: no timings specified\n"); 522 return; 523 } 524 525 for (i = 0; i < panel->desc->num_timings; i++) { 526 const struct display_timing *dt = &panel->desc->timings[i]; 527 528 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 529 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 536 continue; 537 538 if (ot->flags != dt->flags) 539 continue; 540 541 videomode_from_timing(ot, &vm); 542 drm_display_mode_from_videomode(&vm, &panel->override_mode); 543 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 544 DRM_MODE_TYPE_PREFERRED; 545 break; 546 } 547 548 if (WARN_ON(!panel->override_mode.type)) 549 dev_err(dev, "Reject override mode: No display_timing found\n"); 550 } 551 552 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 553 { 554 struct panel_simple *panel; 555 struct display_timing dt; 556 struct device_node *ddc; 557 int connector_type; 558 u32 bus_flags; 559 int err; 560 561 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 562 if (!panel) 563 return -ENOMEM; 564 565 panel->enabled = false; 566 panel->desc = desc; 567 568 panel->supply = devm_regulator_get(dev, "power"); 569 if (IS_ERR(panel->supply)) 570 return PTR_ERR(panel->supply); 571 572 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 573 GPIOD_OUT_LOW); 574 if (IS_ERR(panel->enable_gpio)) 575 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 576 "failed to request GPIO\n"); 577 578 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 579 if (err) { 580 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 581 return err; 582 } 583 584 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 585 if (ddc) { 586 panel->ddc = of_find_i2c_adapter_by_node(ddc); 587 of_node_put(ddc); 588 589 if (!panel->ddc) 590 return -EPROBE_DEFER; 591 } 592 593 if (desc == &panel_dpi) { 594 /* Handle the generic panel-dpi binding */ 595 err = panel_dpi_probe(dev, panel); 596 if (err) 597 goto free_ddc; 598 desc = panel->desc; 599 } else { 600 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 601 panel_simple_parse_panel_timing_node(dev, panel, &dt); 602 } 603 604 connector_type = desc->connector_type; 605 /* Catch common mistakes for panels. */ 606 switch (connector_type) { 607 case 0: 608 dev_warn(dev, "Specify missing connector_type\n"); 609 connector_type = DRM_MODE_CONNECTOR_DPI; 610 break; 611 case DRM_MODE_CONNECTOR_LVDS: 612 WARN_ON(desc->bus_flags & 613 ~(DRM_BUS_FLAG_DE_LOW | 614 DRM_BUS_FLAG_DE_HIGH | 615 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 616 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 617 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 618 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 619 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 620 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 621 desc->bpc != 6); 622 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 623 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 624 desc->bpc != 8); 625 break; 626 case DRM_MODE_CONNECTOR_eDP: 627 dev_warn(dev, "eDP panels moved to panel-edp\n"); 628 err = -EINVAL; 629 goto free_ddc; 630 case DRM_MODE_CONNECTOR_DSI: 631 if (desc->bpc != 6 && desc->bpc != 8) 632 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 633 break; 634 case DRM_MODE_CONNECTOR_DPI: 635 bus_flags = DRM_BUS_FLAG_DE_LOW | 636 DRM_BUS_FLAG_DE_HIGH | 637 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 638 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 639 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 640 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 641 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 642 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 643 if (desc->bus_flags & ~bus_flags) 644 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 645 if (!(desc->bus_flags & bus_flags)) 646 dev_warn(dev, "Specify missing bus_flags\n"); 647 if (desc->bus_format == 0) 648 dev_warn(dev, "Specify missing bus_format\n"); 649 if (desc->bpc != 6 && desc->bpc != 8) 650 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 651 break; 652 default: 653 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 654 connector_type = DRM_MODE_CONNECTOR_DPI; 655 break; 656 } 657 658 dev_set_drvdata(dev, panel); 659 660 /* 661 * We use runtime PM for prepare / unprepare since those power the panel 662 * on and off and those can be very slow operations. This is important 663 * to optimize powering the panel on briefly to read the EDID before 664 * fully enabling the panel. 665 */ 666 pm_runtime_enable(dev); 667 pm_runtime_set_autosuspend_delay(dev, 1000); 668 pm_runtime_use_autosuspend(dev); 669 670 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 671 672 err = drm_panel_of_backlight(&panel->base); 673 if (err) { 674 dev_err_probe(dev, err, "Could not find backlight\n"); 675 goto disable_pm_runtime; 676 } 677 678 drm_panel_add(&panel->base); 679 680 return 0; 681 682 disable_pm_runtime: 683 pm_runtime_dont_use_autosuspend(dev); 684 pm_runtime_disable(dev); 685 free_ddc: 686 if (panel->ddc) 687 put_device(&panel->ddc->dev); 688 689 return err; 690 } 691 692 static void panel_simple_remove(struct device *dev) 693 { 694 struct panel_simple *panel = dev_get_drvdata(dev); 695 696 drm_panel_remove(&panel->base); 697 drm_panel_disable(&panel->base); 698 drm_panel_unprepare(&panel->base); 699 700 pm_runtime_dont_use_autosuspend(dev); 701 pm_runtime_disable(dev); 702 if (panel->ddc) 703 put_device(&panel->ddc->dev); 704 } 705 706 static void panel_simple_shutdown(struct device *dev) 707 { 708 struct panel_simple *panel = dev_get_drvdata(dev); 709 710 drm_panel_disable(&panel->base); 711 drm_panel_unprepare(&panel->base); 712 } 713 714 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 715 .clock = 71100, 716 .hdisplay = 1280, 717 .hsync_start = 1280 + 40, 718 .hsync_end = 1280 + 40 + 80, 719 .htotal = 1280 + 40 + 80 + 40, 720 .vdisplay = 800, 721 .vsync_start = 800 + 3, 722 .vsync_end = 800 + 3 + 10, 723 .vtotal = 800 + 3 + 10 + 10, 724 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 725 }; 726 727 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 728 .modes = &ire_am_1280800n3tzqw_t00h_mode, 729 .num_modes = 1, 730 .bpc = 8, 731 .size = { 732 .width = 217, 733 .height = 136, 734 }, 735 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 736 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 737 .connector_type = DRM_MODE_CONNECTOR_LVDS, 738 }; 739 740 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 741 .clock = 9000, 742 .hdisplay = 480, 743 .hsync_start = 480 + 2, 744 .hsync_end = 480 + 2 + 41, 745 .htotal = 480 + 2 + 41 + 2, 746 .vdisplay = 272, 747 .vsync_start = 272 + 2, 748 .vsync_end = 272 + 2 + 10, 749 .vtotal = 272 + 2 + 10 + 2, 750 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 751 }; 752 753 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 754 .modes = &ire_am_480272h3tmqw_t01h_mode, 755 .num_modes = 1, 756 .bpc = 8, 757 .size = { 758 .width = 99, 759 .height = 58, 760 }, 761 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 762 }; 763 764 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 765 .clock = 33333, 766 .hdisplay = 800, 767 .hsync_start = 800 + 0, 768 .hsync_end = 800 + 0 + 255, 769 .htotal = 800 + 0 + 255 + 0, 770 .vdisplay = 480, 771 .vsync_start = 480 + 2, 772 .vsync_end = 480 + 2 + 45, 773 .vtotal = 480 + 2 + 45 + 0, 774 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 775 }; 776 777 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 778 .pixelclock = { 29930000, 33260000, 36590000 }, 779 .hactive = { 800, 800, 800 }, 780 .hfront_porch = { 1, 40, 168 }, 781 .hback_porch = { 88, 88, 88 }, 782 .hsync_len = { 1, 128, 128 }, 783 .vactive = { 480, 480, 480 }, 784 .vfront_porch = { 1, 35, 37 }, 785 .vback_porch = { 8, 8, 8 }, 786 .vsync_len = { 1, 2, 2 }, 787 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 788 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 789 DISPLAY_FLAGS_SYNC_POSEDGE, 790 }; 791 792 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 793 .timings = &ire_am_800480l1tmqw_t00h_timing, 794 .num_timings = 1, 795 .bpc = 8, 796 .size = { 797 .width = 111, 798 .height = 67, 799 }, 800 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 801 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 802 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 803 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 804 .connector_type = DRM_MODE_CONNECTOR_DPI, 805 }; 806 807 static const struct panel_desc ampire_am800480r3tmqwa1h = { 808 .modes = &ire_am800480r3tmqwa1h_mode, 809 .num_modes = 1, 810 .bpc = 6, 811 .size = { 812 .width = 152, 813 .height = 91, 814 }, 815 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 816 }; 817 818 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 819 .pixelclock = { 34500000, 39600000, 50400000 }, 820 .hactive = { 800, 800, 800 }, 821 .hfront_porch = { 12, 112, 312 }, 822 .hback_porch = { 87, 87, 48 }, 823 .hsync_len = { 1, 1, 40 }, 824 .vactive = { 600, 600, 600 }, 825 .vfront_porch = { 1, 21, 61 }, 826 .vback_porch = { 38, 38, 19 }, 827 .vsync_len = { 1, 1, 20 }, 828 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 829 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 830 DISPLAY_FLAGS_SYNC_POSEDGE, 831 }; 832 833 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 834 .timings = &ire_am800600p5tmqw_tb8h_timing, 835 .num_timings = 1, 836 .bpc = 6, 837 .size = { 838 .width = 162, 839 .height = 122, 840 }, 841 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 842 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 843 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 844 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 845 .connector_type = DRM_MODE_CONNECTOR_DPI, 846 }; 847 848 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 849 .pixelclock = { 26400000, 33300000, 46800000 }, 850 .hactive = { 800, 800, 800 }, 851 .hfront_porch = { 16, 210, 354 }, 852 .hback_porch = { 45, 36, 6 }, 853 .hsync_len = { 1, 10, 40 }, 854 .vactive = { 480, 480, 480 }, 855 .vfront_porch = { 7, 22, 147 }, 856 .vback_porch = { 22, 13, 3 }, 857 .vsync_len = { 1, 10, 20 }, 858 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 859 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 860 }; 861 862 static const struct panel_desc armadeus_st0700_adapt = { 863 .timings = &santek_st0700i5y_rbslw_f_timing, 864 .num_timings = 1, 865 .bpc = 6, 866 .size = { 867 .width = 154, 868 .height = 86, 869 }, 870 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 871 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 872 }; 873 874 static const struct drm_display_mode auo_b101aw03_mode = { 875 .clock = 51450, 876 .hdisplay = 1024, 877 .hsync_start = 1024 + 156, 878 .hsync_end = 1024 + 156 + 8, 879 .htotal = 1024 + 156 + 8 + 156, 880 .vdisplay = 600, 881 .vsync_start = 600 + 16, 882 .vsync_end = 600 + 16 + 6, 883 .vtotal = 600 + 16 + 6 + 16, 884 }; 885 886 static const struct panel_desc auo_b101aw03 = { 887 .modes = &auo_b101aw03_mode, 888 .num_modes = 1, 889 .bpc = 6, 890 .size = { 891 .width = 223, 892 .height = 125, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 896 .connector_type = DRM_MODE_CONNECTOR_LVDS, 897 }; 898 899 static const struct drm_display_mode auo_b101xtn01_mode = { 900 .clock = 72000, 901 .hdisplay = 1366, 902 .hsync_start = 1366 + 20, 903 .hsync_end = 1366 + 20 + 70, 904 .htotal = 1366 + 20 + 70, 905 .vdisplay = 768, 906 .vsync_start = 768 + 14, 907 .vsync_end = 768 + 14 + 42, 908 .vtotal = 768 + 14 + 42, 909 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 910 }; 911 912 static const struct panel_desc auo_b101xtn01 = { 913 .modes = &auo_b101xtn01_mode, 914 .num_modes = 1, 915 .bpc = 6, 916 .size = { 917 .width = 223, 918 .height = 125, 919 }, 920 }; 921 922 static const struct display_timing auo_g070vvn01_timings = { 923 .pixelclock = { 33300000, 34209000, 45000000 }, 924 .hactive = { 800, 800, 800 }, 925 .hfront_porch = { 20, 40, 200 }, 926 .hback_porch = { 87, 40, 1 }, 927 .hsync_len = { 1, 48, 87 }, 928 .vactive = { 480, 480, 480 }, 929 .vfront_porch = { 5, 13, 200 }, 930 .vback_porch = { 31, 31, 29 }, 931 .vsync_len = { 1, 1, 3 }, 932 }; 933 934 static const struct panel_desc auo_g070vvn01 = { 935 .timings = &auo_g070vvn01_timings, 936 .num_timings = 1, 937 .bpc = 8, 938 .size = { 939 .width = 152, 940 .height = 91, 941 }, 942 .delay = { 943 .prepare = 200, 944 .enable = 50, 945 .disable = 50, 946 .unprepare = 1000, 947 }, 948 }; 949 950 static const struct drm_display_mode auo_g101evn010_mode = { 951 .clock = 68930, 952 .hdisplay = 1280, 953 .hsync_start = 1280 + 82, 954 .hsync_end = 1280 + 82 + 2, 955 .htotal = 1280 + 82 + 2 + 84, 956 .vdisplay = 800, 957 .vsync_start = 800 + 8, 958 .vsync_end = 800 + 8 + 2, 959 .vtotal = 800 + 8 + 2 + 6, 960 }; 961 962 static const struct panel_desc auo_g101evn010 = { 963 .modes = &auo_g101evn010_mode, 964 .num_modes = 1, 965 .bpc = 6, 966 .size = { 967 .width = 216, 968 .height = 135, 969 }, 970 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 971 .connector_type = DRM_MODE_CONNECTOR_LVDS, 972 }; 973 974 static const struct drm_display_mode auo_g104sn02_mode = { 975 .clock = 40000, 976 .hdisplay = 800, 977 .hsync_start = 800 + 40, 978 .hsync_end = 800 + 40 + 216, 979 .htotal = 800 + 40 + 216 + 128, 980 .vdisplay = 600, 981 .vsync_start = 600 + 10, 982 .vsync_end = 600 + 10 + 35, 983 .vtotal = 600 + 10 + 35 + 2, 984 }; 985 986 static const struct panel_desc auo_g104sn02 = { 987 .modes = &auo_g104sn02_mode, 988 .num_modes = 1, 989 .bpc = 8, 990 .size = { 991 .width = 211, 992 .height = 158, 993 }, 994 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 995 .connector_type = DRM_MODE_CONNECTOR_LVDS, 996 }; 997 998 static const struct display_timing auo_g121ean01_timing = { 999 .pixelclock = { 60000000, 74400000, 90000000 }, 1000 .hactive = { 1280, 1280, 1280 }, 1001 .hfront_porch = { 20, 50, 100 }, 1002 .hback_porch = { 20, 50, 100 }, 1003 .hsync_len = { 30, 100, 200 }, 1004 .vactive = { 800, 800, 800 }, 1005 .vfront_porch = { 2, 10, 25 }, 1006 .vback_porch = { 2, 10, 25 }, 1007 .vsync_len = { 4, 18, 50 }, 1008 }; 1009 1010 static const struct panel_desc auo_g121ean01 = { 1011 .timings = &auo_g121ean01_timing, 1012 .num_timings = 1, 1013 .bpc = 8, 1014 .size = { 1015 .width = 261, 1016 .height = 163, 1017 }, 1018 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1019 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1020 }; 1021 1022 static const struct display_timing auo_g133han01_timings = { 1023 .pixelclock = { 134000000, 141200000, 149000000 }, 1024 .hactive = { 1920, 1920, 1920 }, 1025 .hfront_porch = { 39, 58, 77 }, 1026 .hback_porch = { 59, 88, 117 }, 1027 .hsync_len = { 28, 42, 56 }, 1028 .vactive = { 1080, 1080, 1080 }, 1029 .vfront_porch = { 3, 8, 11 }, 1030 .vback_porch = { 5, 14, 19 }, 1031 .vsync_len = { 4, 14, 19 }, 1032 }; 1033 1034 static const struct panel_desc auo_g133han01 = { 1035 .timings = &auo_g133han01_timings, 1036 .num_timings = 1, 1037 .bpc = 8, 1038 .size = { 1039 .width = 293, 1040 .height = 165, 1041 }, 1042 .delay = { 1043 .prepare = 200, 1044 .enable = 50, 1045 .disable = 50, 1046 .unprepare = 1000, 1047 }, 1048 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1049 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1050 }; 1051 1052 static const struct drm_display_mode auo_g156xtn01_mode = { 1053 .clock = 76000, 1054 .hdisplay = 1366, 1055 .hsync_start = 1366 + 33, 1056 .hsync_end = 1366 + 33 + 67, 1057 .htotal = 1560, 1058 .vdisplay = 768, 1059 .vsync_start = 768 + 4, 1060 .vsync_end = 768 + 4 + 4, 1061 .vtotal = 806, 1062 }; 1063 1064 static const struct panel_desc auo_g156xtn01 = { 1065 .modes = &auo_g156xtn01_mode, 1066 .num_modes = 1, 1067 .bpc = 8, 1068 .size = { 1069 .width = 344, 1070 .height = 194, 1071 }, 1072 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1073 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1074 }; 1075 1076 static const struct display_timing auo_g185han01_timings = { 1077 .pixelclock = { 120000000, 144000000, 175000000 }, 1078 .hactive = { 1920, 1920, 1920 }, 1079 .hfront_porch = { 36, 120, 148 }, 1080 .hback_porch = { 24, 88, 108 }, 1081 .hsync_len = { 20, 48, 64 }, 1082 .vactive = { 1080, 1080, 1080 }, 1083 .vfront_porch = { 6, 10, 40 }, 1084 .vback_porch = { 2, 5, 20 }, 1085 .vsync_len = { 2, 5, 20 }, 1086 }; 1087 1088 static const struct panel_desc auo_g185han01 = { 1089 .timings = &auo_g185han01_timings, 1090 .num_timings = 1, 1091 .bpc = 8, 1092 .size = { 1093 .width = 409, 1094 .height = 230, 1095 }, 1096 .delay = { 1097 .prepare = 50, 1098 .enable = 200, 1099 .disable = 110, 1100 .unprepare = 1000, 1101 }, 1102 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1103 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1104 }; 1105 1106 static const struct display_timing auo_g190ean01_timings = { 1107 .pixelclock = { 90000000, 108000000, 135000000 }, 1108 .hactive = { 1280, 1280, 1280 }, 1109 .hfront_porch = { 126, 184, 1266 }, 1110 .hback_porch = { 84, 122, 844 }, 1111 .hsync_len = { 70, 102, 704 }, 1112 .vactive = { 1024, 1024, 1024 }, 1113 .vfront_porch = { 4, 26, 76 }, 1114 .vback_porch = { 2, 8, 25 }, 1115 .vsync_len = { 2, 8, 25 }, 1116 }; 1117 1118 static const struct panel_desc auo_g190ean01 = { 1119 .timings = &auo_g190ean01_timings, 1120 .num_timings = 1, 1121 .bpc = 8, 1122 .size = { 1123 .width = 376, 1124 .height = 301, 1125 }, 1126 .delay = { 1127 .prepare = 50, 1128 .enable = 200, 1129 .disable = 110, 1130 .unprepare = 1000, 1131 }, 1132 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1133 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1134 }; 1135 1136 static const struct display_timing auo_p320hvn03_timings = { 1137 .pixelclock = { 106000000, 148500000, 164000000 }, 1138 .hactive = { 1920, 1920, 1920 }, 1139 .hfront_porch = { 25, 50, 130 }, 1140 .hback_porch = { 25, 50, 130 }, 1141 .hsync_len = { 20, 40, 105 }, 1142 .vactive = { 1080, 1080, 1080 }, 1143 .vfront_porch = { 8, 17, 150 }, 1144 .vback_porch = { 8, 17, 150 }, 1145 .vsync_len = { 4, 11, 100 }, 1146 }; 1147 1148 static const struct panel_desc auo_p320hvn03 = { 1149 .timings = &auo_p320hvn03_timings, 1150 .num_timings = 1, 1151 .bpc = 8, 1152 .size = { 1153 .width = 698, 1154 .height = 393, 1155 }, 1156 .delay = { 1157 .prepare = 1, 1158 .enable = 450, 1159 .unprepare = 500, 1160 }, 1161 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1162 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1163 }; 1164 1165 static const struct drm_display_mode auo_t215hvn01_mode = { 1166 .clock = 148800, 1167 .hdisplay = 1920, 1168 .hsync_start = 1920 + 88, 1169 .hsync_end = 1920 + 88 + 44, 1170 .htotal = 1920 + 88 + 44 + 148, 1171 .vdisplay = 1080, 1172 .vsync_start = 1080 + 4, 1173 .vsync_end = 1080 + 4 + 5, 1174 .vtotal = 1080 + 4 + 5 + 36, 1175 }; 1176 1177 static const struct panel_desc auo_t215hvn01 = { 1178 .modes = &auo_t215hvn01_mode, 1179 .num_modes = 1, 1180 .bpc = 8, 1181 .size = { 1182 .width = 430, 1183 .height = 270, 1184 }, 1185 .delay = { 1186 .disable = 5, 1187 .unprepare = 1000, 1188 }, 1189 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1190 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1191 }; 1192 1193 static const struct drm_display_mode avic_tm070ddh03_mode = { 1194 .clock = 51200, 1195 .hdisplay = 1024, 1196 .hsync_start = 1024 + 160, 1197 .hsync_end = 1024 + 160 + 4, 1198 .htotal = 1024 + 160 + 4 + 156, 1199 .vdisplay = 600, 1200 .vsync_start = 600 + 17, 1201 .vsync_end = 600 + 17 + 1, 1202 .vtotal = 600 + 17 + 1 + 17, 1203 }; 1204 1205 static const struct panel_desc avic_tm070ddh03 = { 1206 .modes = &avic_tm070ddh03_mode, 1207 .num_modes = 1, 1208 .bpc = 8, 1209 .size = { 1210 .width = 154, 1211 .height = 90, 1212 }, 1213 .delay = { 1214 .prepare = 20, 1215 .enable = 200, 1216 .disable = 200, 1217 }, 1218 }; 1219 1220 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1221 .clock = 30000, 1222 .hdisplay = 800, 1223 .hsync_start = 800 + 40, 1224 .hsync_end = 800 + 40 + 48, 1225 .htotal = 800 + 40 + 48 + 40, 1226 .vdisplay = 480, 1227 .vsync_start = 480 + 13, 1228 .vsync_end = 480 + 13 + 3, 1229 .vtotal = 480 + 13 + 3 + 29, 1230 }; 1231 1232 static const struct panel_desc bananapi_s070wv20_ct16 = { 1233 .modes = &bananapi_s070wv20_ct16_mode, 1234 .num_modes = 1, 1235 .bpc = 6, 1236 .size = { 1237 .width = 154, 1238 .height = 86, 1239 }, 1240 }; 1241 1242 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1243 .pixelclock = { 69922000, 71000000, 72293000 }, 1244 .hactive = { 1280, 1280, 1280 }, 1245 .hfront_porch = { 48, 48, 48 }, 1246 .hback_porch = { 80, 80, 80 }, 1247 .hsync_len = { 32, 32, 32 }, 1248 .vactive = { 800, 800, 800 }, 1249 .vfront_porch = { 3, 3, 3 }, 1250 .vback_porch = { 14, 14, 14 }, 1251 .vsync_len = { 6, 6, 6 }, 1252 }; 1253 1254 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1255 .timings = &boe_ev121wxm_n10_1850_timing, 1256 .num_timings = 1, 1257 .bpc = 8, 1258 .size = { 1259 .width = 261, 1260 .height = 163, 1261 }, 1262 .delay = { 1263 .prepare = 9, 1264 .enable = 300, 1265 .unprepare = 300, 1266 .disable = 560, 1267 }, 1268 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1269 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1270 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1271 }; 1272 1273 static const struct drm_display_mode boe_hv070wsa_mode = { 1274 .clock = 42105, 1275 .hdisplay = 1024, 1276 .hsync_start = 1024 + 30, 1277 .hsync_end = 1024 + 30 + 30, 1278 .htotal = 1024 + 30 + 30 + 30, 1279 .vdisplay = 600, 1280 .vsync_start = 600 + 10, 1281 .vsync_end = 600 + 10 + 10, 1282 .vtotal = 600 + 10 + 10 + 10, 1283 }; 1284 1285 static const struct panel_desc boe_hv070wsa = { 1286 .modes = &boe_hv070wsa_mode, 1287 .num_modes = 1, 1288 .bpc = 8, 1289 .size = { 1290 .width = 154, 1291 .height = 90, 1292 }, 1293 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1294 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1295 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1296 }; 1297 1298 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1299 .clock = 9000, 1300 .hdisplay = 480, 1301 .hsync_start = 480 + 5, 1302 .hsync_end = 480 + 5 + 5, 1303 .htotal = 480 + 5 + 5 + 40, 1304 .vdisplay = 272, 1305 .vsync_start = 272 + 8, 1306 .vsync_end = 272 + 8 + 8, 1307 .vtotal = 272 + 8 + 8 + 8, 1308 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1309 }; 1310 1311 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1312 .modes = &cdtech_s043wq26h_ct7_mode, 1313 .num_modes = 1, 1314 .bpc = 8, 1315 .size = { 1316 .width = 95, 1317 .height = 54, 1318 }, 1319 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1320 }; 1321 1322 /* S070PWS19HP-FC21 2017/04/22 */ 1323 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1324 .clock = 51200, 1325 .hdisplay = 1024, 1326 .hsync_start = 1024 + 160, 1327 .hsync_end = 1024 + 160 + 20, 1328 .htotal = 1024 + 160 + 20 + 140, 1329 .vdisplay = 600, 1330 .vsync_start = 600 + 12, 1331 .vsync_end = 600 + 12 + 3, 1332 .vtotal = 600 + 12 + 3 + 20, 1333 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1334 }; 1335 1336 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1337 .modes = &cdtech_s070pws19hp_fc21_mode, 1338 .num_modes = 1, 1339 .bpc = 6, 1340 .size = { 1341 .width = 154, 1342 .height = 86, 1343 }, 1344 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1345 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1346 .connector_type = DRM_MODE_CONNECTOR_DPI, 1347 }; 1348 1349 /* S070SWV29HG-DC44 2017/09/21 */ 1350 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1351 .clock = 33300, 1352 .hdisplay = 800, 1353 .hsync_start = 800 + 210, 1354 .hsync_end = 800 + 210 + 2, 1355 .htotal = 800 + 210 + 2 + 44, 1356 .vdisplay = 480, 1357 .vsync_start = 480 + 22, 1358 .vsync_end = 480 + 22 + 2, 1359 .vtotal = 480 + 22 + 2 + 21, 1360 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1361 }; 1362 1363 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1364 .modes = &cdtech_s070swv29hg_dc44_mode, 1365 .num_modes = 1, 1366 .bpc = 6, 1367 .size = { 1368 .width = 154, 1369 .height = 86, 1370 }, 1371 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1372 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1373 .connector_type = DRM_MODE_CONNECTOR_DPI, 1374 }; 1375 1376 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1377 .clock = 35000, 1378 .hdisplay = 800, 1379 .hsync_start = 800 + 40, 1380 .hsync_end = 800 + 40 + 40, 1381 .htotal = 800 + 40 + 40 + 48, 1382 .vdisplay = 480, 1383 .vsync_start = 480 + 29, 1384 .vsync_end = 480 + 29 + 13, 1385 .vtotal = 480 + 29 + 13 + 3, 1386 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1387 }; 1388 1389 static const struct panel_desc cdtech_s070wv95_ct16 = { 1390 .modes = &cdtech_s070wv95_ct16_mode, 1391 .num_modes = 1, 1392 .bpc = 8, 1393 .size = { 1394 .width = 154, 1395 .height = 85, 1396 }, 1397 }; 1398 1399 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1400 .pixelclock = { 68900000, 71100000, 73400000 }, 1401 .hactive = { 1280, 1280, 1280 }, 1402 .hfront_porch = { 65, 80, 95 }, 1403 .hback_porch = { 64, 79, 94 }, 1404 .hsync_len = { 1, 1, 1 }, 1405 .vactive = { 800, 800, 800 }, 1406 .vfront_porch = { 7, 11, 14 }, 1407 .vback_porch = { 7, 11, 14 }, 1408 .vsync_len = { 1, 1, 1 }, 1409 .flags = DISPLAY_FLAGS_DE_HIGH, 1410 }; 1411 1412 static const struct panel_desc chefree_ch101olhlwh_002 = { 1413 .timings = &chefree_ch101olhlwh_002_timing, 1414 .num_timings = 1, 1415 .bpc = 8, 1416 .size = { 1417 .width = 217, 1418 .height = 135, 1419 }, 1420 .delay = { 1421 .enable = 200, 1422 .disable = 200, 1423 }, 1424 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1425 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1426 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1427 }; 1428 1429 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1430 .clock = 66770, 1431 .hdisplay = 800, 1432 .hsync_start = 800 + 49, 1433 .hsync_end = 800 + 49 + 33, 1434 .htotal = 800 + 49 + 33 + 17, 1435 .vdisplay = 1280, 1436 .vsync_start = 1280 + 1, 1437 .vsync_end = 1280 + 1 + 7, 1438 .vtotal = 1280 + 1 + 7 + 15, 1439 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1440 }; 1441 1442 static const struct panel_desc chunghwa_claa070wp03xg = { 1443 .modes = &chunghwa_claa070wp03xg_mode, 1444 .num_modes = 1, 1445 .bpc = 6, 1446 .size = { 1447 .width = 94, 1448 .height = 150, 1449 }, 1450 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1451 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1452 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1453 }; 1454 1455 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1456 .clock = 72070, 1457 .hdisplay = 1366, 1458 .hsync_start = 1366 + 58, 1459 .hsync_end = 1366 + 58 + 58, 1460 .htotal = 1366 + 58 + 58 + 58, 1461 .vdisplay = 768, 1462 .vsync_start = 768 + 4, 1463 .vsync_end = 768 + 4 + 4, 1464 .vtotal = 768 + 4 + 4 + 4, 1465 }; 1466 1467 static const struct panel_desc chunghwa_claa101wa01a = { 1468 .modes = &chunghwa_claa101wa01a_mode, 1469 .num_modes = 1, 1470 .bpc = 6, 1471 .size = { 1472 .width = 220, 1473 .height = 120, 1474 }, 1475 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1476 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1477 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1478 }; 1479 1480 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1481 .clock = 69300, 1482 .hdisplay = 1366, 1483 .hsync_start = 1366 + 48, 1484 .hsync_end = 1366 + 48 + 32, 1485 .htotal = 1366 + 48 + 32 + 20, 1486 .vdisplay = 768, 1487 .vsync_start = 768 + 16, 1488 .vsync_end = 768 + 16 + 8, 1489 .vtotal = 768 + 16 + 8 + 16, 1490 }; 1491 1492 static const struct panel_desc chunghwa_claa101wb01 = { 1493 .modes = &chunghwa_claa101wb01_mode, 1494 .num_modes = 1, 1495 .bpc = 6, 1496 .size = { 1497 .width = 223, 1498 .height = 125, 1499 }, 1500 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1501 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1502 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1503 }; 1504 1505 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1506 .pixelclock = { 5000000, 9000000, 12000000 }, 1507 .hactive = { 480, 480, 480 }, 1508 .hfront_porch = { 12, 12, 12 }, 1509 .hback_porch = { 12, 12, 12 }, 1510 .hsync_len = { 21, 21, 21 }, 1511 .vactive = { 272, 272, 272 }, 1512 .vfront_porch = { 4, 4, 4 }, 1513 .vback_porch = { 4, 4, 4 }, 1514 .vsync_len = { 8, 8, 8 }, 1515 }; 1516 1517 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1518 .timings = &dataimage_fg040346dsswbg04_timing, 1519 .num_timings = 1, 1520 .bpc = 8, 1521 .size = { 1522 .width = 95, 1523 .height = 54, 1524 }, 1525 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1526 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1527 .connector_type = DRM_MODE_CONNECTOR_DPI, 1528 }; 1529 1530 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1531 .pixelclock = { 68900000, 71110000, 73400000 }, 1532 .hactive = { 1280, 1280, 1280 }, 1533 .vactive = { 800, 800, 800 }, 1534 .hback_porch = { 100, 100, 100 }, 1535 .hfront_porch = { 100, 100, 100 }, 1536 .vback_porch = { 5, 5, 5 }, 1537 .vfront_porch = { 5, 5, 5 }, 1538 .hsync_len = { 24, 24, 24 }, 1539 .vsync_len = { 3, 3, 3 }, 1540 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1541 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1542 }; 1543 1544 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1545 .timings = &dataimage_fg1001l0dsswmg01_timing, 1546 .num_timings = 1, 1547 .bpc = 8, 1548 .size = { 1549 .width = 217, 1550 .height = 136, 1551 }, 1552 }; 1553 1554 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1555 .clock = 33260, 1556 .hdisplay = 800, 1557 .hsync_start = 800 + 40, 1558 .hsync_end = 800 + 40 + 128, 1559 .htotal = 800 + 40 + 128 + 88, 1560 .vdisplay = 480, 1561 .vsync_start = 480 + 10, 1562 .vsync_end = 480 + 10 + 2, 1563 .vtotal = 480 + 10 + 2 + 33, 1564 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1565 }; 1566 1567 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1568 .modes = &dataimage_scf0700c48ggu18_mode, 1569 .num_modes = 1, 1570 .bpc = 8, 1571 .size = { 1572 .width = 152, 1573 .height = 91, 1574 }, 1575 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1576 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1577 }; 1578 1579 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1580 .pixelclock = { 45000000, 51200000, 57000000 }, 1581 .hactive = { 1024, 1024, 1024 }, 1582 .hfront_porch = { 100, 106, 113 }, 1583 .hback_porch = { 100, 106, 113 }, 1584 .hsync_len = { 100, 108, 114 }, 1585 .vactive = { 600, 600, 600 }, 1586 .vfront_porch = { 8, 11, 15 }, 1587 .vback_porch = { 8, 11, 15 }, 1588 .vsync_len = { 9, 13, 15 }, 1589 .flags = DISPLAY_FLAGS_DE_HIGH, 1590 }; 1591 1592 static const struct panel_desc dlc_dlc0700yzg_1 = { 1593 .timings = &dlc_dlc0700yzg_1_timing, 1594 .num_timings = 1, 1595 .bpc = 6, 1596 .size = { 1597 .width = 154, 1598 .height = 86, 1599 }, 1600 .delay = { 1601 .prepare = 30, 1602 .enable = 200, 1603 .disable = 200, 1604 }, 1605 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1606 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1607 }; 1608 1609 static const struct display_timing dlc_dlc1010gig_timing = { 1610 .pixelclock = { 68900000, 71100000, 73400000 }, 1611 .hactive = { 1280, 1280, 1280 }, 1612 .hfront_porch = { 43, 53, 63 }, 1613 .hback_porch = { 43, 53, 63 }, 1614 .hsync_len = { 44, 54, 64 }, 1615 .vactive = { 800, 800, 800 }, 1616 .vfront_porch = { 5, 8, 11 }, 1617 .vback_porch = { 5, 8, 11 }, 1618 .vsync_len = { 5, 7, 11 }, 1619 .flags = DISPLAY_FLAGS_DE_HIGH, 1620 }; 1621 1622 static const struct panel_desc dlc_dlc1010gig = { 1623 .timings = &dlc_dlc1010gig_timing, 1624 .num_timings = 1, 1625 .bpc = 8, 1626 .size = { 1627 .width = 216, 1628 .height = 135, 1629 }, 1630 .delay = { 1631 .prepare = 60, 1632 .enable = 150, 1633 .disable = 100, 1634 .unprepare = 60, 1635 }, 1636 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1637 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1638 }; 1639 1640 static const struct drm_display_mode edt_et035012dm6_mode = { 1641 .clock = 6500, 1642 .hdisplay = 320, 1643 .hsync_start = 320 + 20, 1644 .hsync_end = 320 + 20 + 30, 1645 .htotal = 320 + 20 + 68, 1646 .vdisplay = 240, 1647 .vsync_start = 240 + 4, 1648 .vsync_end = 240 + 4 + 4, 1649 .vtotal = 240 + 4 + 4 + 14, 1650 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1651 }; 1652 1653 static const struct panel_desc edt_et035012dm6 = { 1654 .modes = &edt_et035012dm6_mode, 1655 .num_modes = 1, 1656 .bpc = 8, 1657 .size = { 1658 .width = 70, 1659 .height = 52, 1660 }, 1661 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1662 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1663 }; 1664 1665 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1666 .clock = 6520, 1667 .hdisplay = 320, 1668 .hsync_start = 320 + 20, 1669 .hsync_end = 320 + 20 + 68, 1670 .htotal = 320 + 20 + 68, 1671 .vdisplay = 240, 1672 .vsync_start = 240 + 4, 1673 .vsync_end = 240 + 4 + 18, 1674 .vtotal = 240 + 4 + 18, 1675 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1676 }; 1677 1678 static const struct panel_desc edt_etm0350g0dh6 = { 1679 .modes = &edt_etm0350g0dh6_mode, 1680 .num_modes = 1, 1681 .bpc = 6, 1682 .size = { 1683 .width = 70, 1684 .height = 53, 1685 }, 1686 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1687 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1688 .connector_type = DRM_MODE_CONNECTOR_DPI, 1689 }; 1690 1691 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1692 .clock = 10870, 1693 .hdisplay = 480, 1694 .hsync_start = 480 + 8, 1695 .hsync_end = 480 + 8 + 4, 1696 .htotal = 480 + 8 + 4 + 41, 1697 1698 /* 1699 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1700 * fb_align 1701 */ 1702 1703 .vdisplay = 288, 1704 .vsync_start = 288 + 2, 1705 .vsync_end = 288 + 2 + 4, 1706 .vtotal = 288 + 2 + 4 + 10, 1707 }; 1708 1709 static const struct panel_desc edt_etm043080dh6gp = { 1710 .modes = &edt_etm043080dh6gp_mode, 1711 .num_modes = 1, 1712 .bpc = 8, 1713 .size = { 1714 .width = 100, 1715 .height = 65, 1716 }, 1717 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1718 .connector_type = DRM_MODE_CONNECTOR_DPI, 1719 }; 1720 1721 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1722 .clock = 9000, 1723 .hdisplay = 480, 1724 .hsync_start = 480 + 2, 1725 .hsync_end = 480 + 2 + 41, 1726 .htotal = 480 + 2 + 41 + 2, 1727 .vdisplay = 272, 1728 .vsync_start = 272 + 2, 1729 .vsync_end = 272 + 2 + 10, 1730 .vtotal = 272 + 2 + 10 + 2, 1731 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1732 }; 1733 1734 static const struct panel_desc edt_etm0430g0dh6 = { 1735 .modes = &edt_etm0430g0dh6_mode, 1736 .num_modes = 1, 1737 .bpc = 6, 1738 .size = { 1739 .width = 95, 1740 .height = 54, 1741 }, 1742 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1743 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1744 .connector_type = DRM_MODE_CONNECTOR_DPI, 1745 }; 1746 1747 static const struct drm_display_mode edt_et057090dhu_mode = { 1748 .clock = 25175, 1749 .hdisplay = 640, 1750 .hsync_start = 640 + 16, 1751 .hsync_end = 640 + 16 + 30, 1752 .htotal = 640 + 16 + 30 + 114, 1753 .vdisplay = 480, 1754 .vsync_start = 480 + 10, 1755 .vsync_end = 480 + 10 + 3, 1756 .vtotal = 480 + 10 + 3 + 32, 1757 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1758 }; 1759 1760 static const struct panel_desc edt_et057090dhu = { 1761 .modes = &edt_et057090dhu_mode, 1762 .num_modes = 1, 1763 .bpc = 6, 1764 .size = { 1765 .width = 115, 1766 .height = 86, 1767 }, 1768 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1769 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1770 .connector_type = DRM_MODE_CONNECTOR_DPI, 1771 }; 1772 1773 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1774 .clock = 33260, 1775 .hdisplay = 800, 1776 .hsync_start = 800 + 40, 1777 .hsync_end = 800 + 40 + 128, 1778 .htotal = 800 + 40 + 128 + 88, 1779 .vdisplay = 480, 1780 .vsync_start = 480 + 10, 1781 .vsync_end = 480 + 10 + 2, 1782 .vtotal = 480 + 10 + 2 + 33, 1783 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1784 }; 1785 1786 static const struct panel_desc edt_etm0700g0dh6 = { 1787 .modes = &edt_etm0700g0dh6_mode, 1788 .num_modes = 1, 1789 .bpc = 6, 1790 .size = { 1791 .width = 152, 1792 .height = 91, 1793 }, 1794 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1795 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1796 .connector_type = DRM_MODE_CONNECTOR_DPI, 1797 }; 1798 1799 static const struct panel_desc edt_etm0700g0bdh6 = { 1800 .modes = &edt_etm0700g0dh6_mode, 1801 .num_modes = 1, 1802 .bpc = 6, 1803 .size = { 1804 .width = 152, 1805 .height = 91, 1806 }, 1807 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1808 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1809 .connector_type = DRM_MODE_CONNECTOR_DPI, 1810 }; 1811 1812 static const struct display_timing edt_etml0700y5dha_timing = { 1813 .pixelclock = { 40800000, 51200000, 67200000 }, 1814 .hactive = { 1024, 1024, 1024 }, 1815 .hfront_porch = { 30, 106, 125 }, 1816 .hback_porch = { 30, 106, 125 }, 1817 .hsync_len = { 30, 108, 126 }, 1818 .vactive = { 600, 600, 600 }, 1819 .vfront_porch = { 3, 12, 67}, 1820 .vback_porch = { 3, 12, 67 }, 1821 .vsync_len = { 4, 11, 66 }, 1822 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1823 DISPLAY_FLAGS_DE_HIGH, 1824 }; 1825 1826 static const struct panel_desc edt_etml0700y5dha = { 1827 .timings = &edt_etml0700y5dha_timing, 1828 .num_timings = 1, 1829 .bpc = 8, 1830 .size = { 1831 .width = 155, 1832 .height = 86, 1833 }, 1834 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1835 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1836 }; 1837 1838 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 1839 .clock = 25175, 1840 .hdisplay = 640, 1841 .hsync_start = 640, 1842 .hsync_end = 640 + 16, 1843 .htotal = 640 + 16 + 30 + 114, 1844 .vdisplay = 480, 1845 .vsync_start = 480 + 10, 1846 .vsync_end = 480 + 10 + 3, 1847 .vtotal = 480 + 10 + 3 + 35, 1848 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 1849 }; 1850 1851 static const struct panel_desc edt_etmv570g2dhu = { 1852 .modes = &edt_etmv570g2dhu_mode, 1853 .num_modes = 1, 1854 .bpc = 6, 1855 .size = { 1856 .width = 115, 1857 .height = 86, 1858 }, 1859 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1860 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1861 .connector_type = DRM_MODE_CONNECTOR_DPI, 1862 }; 1863 1864 static const struct display_timing eink_vb3300_kca_timing = { 1865 .pixelclock = { 40000000, 40000000, 40000000 }, 1866 .hactive = { 334, 334, 334 }, 1867 .hfront_porch = { 1, 1, 1 }, 1868 .hback_porch = { 1, 1, 1 }, 1869 .hsync_len = { 1, 1, 1 }, 1870 .vactive = { 1405, 1405, 1405 }, 1871 .vfront_porch = { 1, 1, 1 }, 1872 .vback_porch = { 1, 1, 1 }, 1873 .vsync_len = { 1, 1, 1 }, 1874 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1875 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 1876 }; 1877 1878 static const struct panel_desc eink_vb3300_kca = { 1879 .timings = &eink_vb3300_kca_timing, 1880 .num_timings = 1, 1881 .bpc = 6, 1882 .size = { 1883 .width = 157, 1884 .height = 209, 1885 }, 1886 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1887 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1888 .connector_type = DRM_MODE_CONNECTOR_DPI, 1889 }; 1890 1891 static const struct display_timing evervision_vgg804821_timing = { 1892 .pixelclock = { 27600000, 33300000, 50000000 }, 1893 .hactive = { 800, 800, 800 }, 1894 .hfront_porch = { 40, 66, 70 }, 1895 .hback_porch = { 40, 67, 70 }, 1896 .hsync_len = { 40, 67, 70 }, 1897 .vactive = { 480, 480, 480 }, 1898 .vfront_porch = { 6, 10, 10 }, 1899 .vback_porch = { 7, 11, 11 }, 1900 .vsync_len = { 7, 11, 11 }, 1901 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 1902 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 1903 DISPLAY_FLAGS_SYNC_NEGEDGE, 1904 }; 1905 1906 static const struct panel_desc evervision_vgg804821 = { 1907 .timings = &evervision_vgg804821_timing, 1908 .num_timings = 1, 1909 .bpc = 8, 1910 .size = { 1911 .width = 108, 1912 .height = 64, 1913 }, 1914 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1915 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1916 }; 1917 1918 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 1919 .clock = 32260, 1920 .hdisplay = 800, 1921 .hsync_start = 800 + 168, 1922 .hsync_end = 800 + 168 + 64, 1923 .htotal = 800 + 168 + 64 + 88, 1924 .vdisplay = 480, 1925 .vsync_start = 480 + 37, 1926 .vsync_end = 480 + 37 + 2, 1927 .vtotal = 480 + 37 + 2 + 8, 1928 }; 1929 1930 static const struct panel_desc foxlink_fl500wvr00_a0t = { 1931 .modes = &foxlink_fl500wvr00_a0t_mode, 1932 .num_modes = 1, 1933 .bpc = 8, 1934 .size = { 1935 .width = 108, 1936 .height = 65, 1937 }, 1938 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1939 }; 1940 1941 static const struct drm_display_mode frida_frd350h54004_modes[] = { 1942 { /* 60 Hz */ 1943 .clock = 6000, 1944 .hdisplay = 320, 1945 .hsync_start = 320 + 44, 1946 .hsync_end = 320 + 44 + 16, 1947 .htotal = 320 + 44 + 16 + 20, 1948 .vdisplay = 240, 1949 .vsync_start = 240 + 2, 1950 .vsync_end = 240 + 2 + 6, 1951 .vtotal = 240 + 2 + 6 + 2, 1952 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1953 }, 1954 { /* 50 Hz */ 1955 .clock = 5400, 1956 .hdisplay = 320, 1957 .hsync_start = 320 + 56, 1958 .hsync_end = 320 + 56 + 16, 1959 .htotal = 320 + 56 + 16 + 40, 1960 .vdisplay = 240, 1961 .vsync_start = 240 + 2, 1962 .vsync_end = 240 + 2 + 6, 1963 .vtotal = 240 + 2 + 6 + 2, 1964 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1965 }, 1966 }; 1967 1968 static const struct panel_desc frida_frd350h54004 = { 1969 .modes = frida_frd350h54004_modes, 1970 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 1971 .bpc = 8, 1972 .size = { 1973 .width = 77, 1974 .height = 64, 1975 }, 1976 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1977 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1978 .connector_type = DRM_MODE_CONNECTOR_DPI, 1979 }; 1980 1981 static const struct drm_display_mode friendlyarm_hd702e_mode = { 1982 .clock = 67185, 1983 .hdisplay = 800, 1984 .hsync_start = 800 + 20, 1985 .hsync_end = 800 + 20 + 24, 1986 .htotal = 800 + 20 + 24 + 20, 1987 .vdisplay = 1280, 1988 .vsync_start = 1280 + 4, 1989 .vsync_end = 1280 + 4 + 8, 1990 .vtotal = 1280 + 4 + 8 + 4, 1991 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1992 }; 1993 1994 static const struct panel_desc friendlyarm_hd702e = { 1995 .modes = &friendlyarm_hd702e_mode, 1996 .num_modes = 1, 1997 .size = { 1998 .width = 94, 1999 .height = 151, 2000 }, 2001 }; 2002 2003 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2004 .clock = 9000, 2005 .hdisplay = 480, 2006 .hsync_start = 480 + 5, 2007 .hsync_end = 480 + 5 + 1, 2008 .htotal = 480 + 5 + 1 + 40, 2009 .vdisplay = 272, 2010 .vsync_start = 272 + 8, 2011 .vsync_end = 272 + 8 + 1, 2012 .vtotal = 272 + 8 + 1 + 8, 2013 }; 2014 2015 static const struct panel_desc giantplus_gpg482739qs5 = { 2016 .modes = &giantplus_gpg482739qs5_mode, 2017 .num_modes = 1, 2018 .bpc = 8, 2019 .size = { 2020 .width = 95, 2021 .height = 54, 2022 }, 2023 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2024 }; 2025 2026 static const struct display_timing giantplus_gpm940b0_timing = { 2027 .pixelclock = { 13500000, 27000000, 27500000 }, 2028 .hactive = { 320, 320, 320 }, 2029 .hfront_porch = { 14, 686, 718 }, 2030 .hback_porch = { 50, 70, 255 }, 2031 .hsync_len = { 1, 1, 1 }, 2032 .vactive = { 240, 240, 240 }, 2033 .vfront_porch = { 1, 1, 179 }, 2034 .vback_porch = { 1, 21, 31 }, 2035 .vsync_len = { 1, 1, 6 }, 2036 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2037 }; 2038 2039 static const struct panel_desc giantplus_gpm940b0 = { 2040 .timings = &giantplus_gpm940b0_timing, 2041 .num_timings = 1, 2042 .bpc = 8, 2043 .size = { 2044 .width = 60, 2045 .height = 45, 2046 }, 2047 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2048 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2049 }; 2050 2051 static const struct display_timing hannstar_hsd070pww1_timing = { 2052 .pixelclock = { 64300000, 71100000, 82000000 }, 2053 .hactive = { 1280, 1280, 1280 }, 2054 .hfront_porch = { 1, 1, 10 }, 2055 .hback_porch = { 1, 1, 10 }, 2056 /* 2057 * According to the data sheet, the minimum horizontal blanking interval 2058 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2059 * minimum working horizontal blanking interval to be 60 clocks. 2060 */ 2061 .hsync_len = { 58, 158, 661 }, 2062 .vactive = { 800, 800, 800 }, 2063 .vfront_porch = { 1, 1, 10 }, 2064 .vback_porch = { 1, 1, 10 }, 2065 .vsync_len = { 1, 21, 203 }, 2066 .flags = DISPLAY_FLAGS_DE_HIGH, 2067 }; 2068 2069 static const struct panel_desc hannstar_hsd070pww1 = { 2070 .timings = &hannstar_hsd070pww1_timing, 2071 .num_timings = 1, 2072 .bpc = 6, 2073 .size = { 2074 .width = 151, 2075 .height = 94, 2076 }, 2077 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2078 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2079 }; 2080 2081 static const struct display_timing hannstar_hsd100pxn1_timing = { 2082 .pixelclock = { 55000000, 65000000, 75000000 }, 2083 .hactive = { 1024, 1024, 1024 }, 2084 .hfront_porch = { 40, 40, 40 }, 2085 .hback_porch = { 220, 220, 220 }, 2086 .hsync_len = { 20, 60, 100 }, 2087 .vactive = { 768, 768, 768 }, 2088 .vfront_porch = { 7, 7, 7 }, 2089 .vback_porch = { 21, 21, 21 }, 2090 .vsync_len = { 10, 10, 10 }, 2091 .flags = DISPLAY_FLAGS_DE_HIGH, 2092 }; 2093 2094 static const struct panel_desc hannstar_hsd100pxn1 = { 2095 .timings = &hannstar_hsd100pxn1_timing, 2096 .num_timings = 1, 2097 .bpc = 6, 2098 .size = { 2099 .width = 203, 2100 .height = 152, 2101 }, 2102 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2103 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2104 }; 2105 2106 static const struct display_timing hannstar_hsd101pww2_timing = { 2107 .pixelclock = { 64300000, 71100000, 82000000 }, 2108 .hactive = { 1280, 1280, 1280 }, 2109 .hfront_porch = { 1, 1, 10 }, 2110 .hback_porch = { 1, 1, 10 }, 2111 .hsync_len = { 58, 158, 661 }, 2112 .vactive = { 800, 800, 800 }, 2113 .vfront_porch = { 1, 1, 10 }, 2114 .vback_porch = { 1, 1, 10 }, 2115 .vsync_len = { 1, 21, 203 }, 2116 .flags = DISPLAY_FLAGS_DE_HIGH, 2117 }; 2118 2119 static const struct panel_desc hannstar_hsd101pww2 = { 2120 .timings = &hannstar_hsd101pww2_timing, 2121 .num_timings = 1, 2122 .bpc = 8, 2123 .size = { 2124 .width = 217, 2125 .height = 136, 2126 }, 2127 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2128 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2129 }; 2130 2131 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2132 .clock = 33333, 2133 .hdisplay = 800, 2134 .hsync_start = 800 + 85, 2135 .hsync_end = 800 + 85 + 86, 2136 .htotal = 800 + 85 + 86 + 85, 2137 .vdisplay = 480, 2138 .vsync_start = 480 + 16, 2139 .vsync_end = 480 + 16 + 13, 2140 .vtotal = 480 + 16 + 13 + 16, 2141 }; 2142 2143 static const struct panel_desc hitachi_tx23d38vm0caa = { 2144 .modes = &hitachi_tx23d38vm0caa_mode, 2145 .num_modes = 1, 2146 .bpc = 6, 2147 .size = { 2148 .width = 195, 2149 .height = 117, 2150 }, 2151 .delay = { 2152 .enable = 160, 2153 .disable = 160, 2154 }, 2155 }; 2156 2157 static const struct drm_display_mode innolux_at043tn24_mode = { 2158 .clock = 9000, 2159 .hdisplay = 480, 2160 .hsync_start = 480 + 2, 2161 .hsync_end = 480 + 2 + 41, 2162 .htotal = 480 + 2 + 41 + 2, 2163 .vdisplay = 272, 2164 .vsync_start = 272 + 2, 2165 .vsync_end = 272 + 2 + 10, 2166 .vtotal = 272 + 2 + 10 + 2, 2167 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2168 }; 2169 2170 static const struct panel_desc innolux_at043tn24 = { 2171 .modes = &innolux_at043tn24_mode, 2172 .num_modes = 1, 2173 .bpc = 8, 2174 .size = { 2175 .width = 95, 2176 .height = 54, 2177 }, 2178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2179 .connector_type = DRM_MODE_CONNECTOR_DPI, 2180 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2181 }; 2182 2183 static const struct drm_display_mode innolux_at070tn92_mode = { 2184 .clock = 33333, 2185 .hdisplay = 800, 2186 .hsync_start = 800 + 210, 2187 .hsync_end = 800 + 210 + 20, 2188 .htotal = 800 + 210 + 20 + 46, 2189 .vdisplay = 480, 2190 .vsync_start = 480 + 22, 2191 .vsync_end = 480 + 22 + 10, 2192 .vtotal = 480 + 22 + 23 + 10, 2193 }; 2194 2195 static const struct panel_desc innolux_at070tn92 = { 2196 .modes = &innolux_at070tn92_mode, 2197 .num_modes = 1, 2198 .size = { 2199 .width = 154, 2200 .height = 86, 2201 }, 2202 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2203 }; 2204 2205 static const struct display_timing innolux_g070ace_l01_timing = { 2206 .pixelclock = { 25200000, 35000000, 35700000 }, 2207 .hactive = { 800, 800, 800 }, 2208 .hfront_porch = { 30, 32, 87 }, 2209 .hback_porch = { 30, 32, 87 }, 2210 .hsync_len = { 1, 1, 1 }, 2211 .vactive = { 480, 480, 480 }, 2212 .vfront_porch = { 3, 3, 3 }, 2213 .vback_porch = { 13, 13, 13 }, 2214 .vsync_len = { 1, 1, 4 }, 2215 .flags = DISPLAY_FLAGS_DE_HIGH, 2216 }; 2217 2218 static const struct panel_desc innolux_g070ace_l01 = { 2219 .timings = &innolux_g070ace_l01_timing, 2220 .num_timings = 1, 2221 .bpc = 8, 2222 .size = { 2223 .width = 152, 2224 .height = 91, 2225 }, 2226 .delay = { 2227 .prepare = 10, 2228 .enable = 50, 2229 .disable = 50, 2230 .unprepare = 500, 2231 }, 2232 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2233 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2234 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2235 }; 2236 2237 static const struct display_timing innolux_g070y2_l01_timing = { 2238 .pixelclock = { 28000000, 29500000, 32000000 }, 2239 .hactive = { 800, 800, 800 }, 2240 .hfront_porch = { 61, 91, 141 }, 2241 .hback_porch = { 60, 90, 140 }, 2242 .hsync_len = { 12, 12, 12 }, 2243 .vactive = { 480, 480, 480 }, 2244 .vfront_porch = { 4, 9, 30 }, 2245 .vback_porch = { 4, 8, 28 }, 2246 .vsync_len = { 2, 2, 2 }, 2247 .flags = DISPLAY_FLAGS_DE_HIGH, 2248 }; 2249 2250 static const struct panel_desc innolux_g070y2_l01 = { 2251 .timings = &innolux_g070y2_l01_timing, 2252 .num_timings = 1, 2253 .bpc = 8, 2254 .size = { 2255 .width = 152, 2256 .height = 91, 2257 }, 2258 .delay = { 2259 .prepare = 10, 2260 .enable = 100, 2261 .disable = 100, 2262 .unprepare = 800, 2263 }, 2264 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2265 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2266 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2267 }; 2268 2269 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2270 .clock = 33333, 2271 .hdisplay = 800, 2272 .hsync_start = 800 + 210, 2273 .hsync_end = 800 + 210 + 20, 2274 .htotal = 800 + 210 + 20 + 46, 2275 .vdisplay = 480, 2276 .vsync_start = 480 + 22, 2277 .vsync_end = 480 + 22 + 10, 2278 .vtotal = 480 + 22 + 23 + 10, 2279 }; 2280 2281 static const struct panel_desc innolux_g070y2_t02 = { 2282 .modes = &innolux_g070y2_t02_mode, 2283 .num_modes = 1, 2284 .bpc = 8, 2285 .size = { 2286 .width = 152, 2287 .height = 92, 2288 }, 2289 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2290 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2291 .connector_type = DRM_MODE_CONNECTOR_DPI, 2292 }; 2293 2294 static const struct display_timing innolux_g101ice_l01_timing = { 2295 .pixelclock = { 60400000, 71100000, 74700000 }, 2296 .hactive = { 1280, 1280, 1280 }, 2297 .hfront_porch = { 41, 80, 100 }, 2298 .hback_porch = { 40, 79, 99 }, 2299 .hsync_len = { 1, 1, 1 }, 2300 .vactive = { 800, 800, 800 }, 2301 .vfront_porch = { 5, 11, 14 }, 2302 .vback_porch = { 4, 11, 14 }, 2303 .vsync_len = { 1, 1, 1 }, 2304 .flags = DISPLAY_FLAGS_DE_HIGH, 2305 }; 2306 2307 static const struct panel_desc innolux_g101ice_l01 = { 2308 .timings = &innolux_g101ice_l01_timing, 2309 .num_timings = 1, 2310 .bpc = 8, 2311 .size = { 2312 .width = 217, 2313 .height = 135, 2314 }, 2315 .delay = { 2316 .enable = 200, 2317 .disable = 200, 2318 }, 2319 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2320 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2321 }; 2322 2323 static const struct display_timing innolux_g121i1_l01_timing = { 2324 .pixelclock = { 67450000, 71000000, 74550000 }, 2325 .hactive = { 1280, 1280, 1280 }, 2326 .hfront_porch = { 40, 80, 160 }, 2327 .hback_porch = { 39, 79, 159 }, 2328 .hsync_len = { 1, 1, 1 }, 2329 .vactive = { 800, 800, 800 }, 2330 .vfront_porch = { 5, 11, 100 }, 2331 .vback_porch = { 4, 11, 99 }, 2332 .vsync_len = { 1, 1, 1 }, 2333 }; 2334 2335 static const struct panel_desc innolux_g121i1_l01 = { 2336 .timings = &innolux_g121i1_l01_timing, 2337 .num_timings = 1, 2338 .bpc = 6, 2339 .size = { 2340 .width = 261, 2341 .height = 163, 2342 }, 2343 .delay = { 2344 .enable = 200, 2345 .disable = 20, 2346 }, 2347 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2348 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2349 }; 2350 2351 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2352 .clock = 65000, 2353 .hdisplay = 1024, 2354 .hsync_start = 1024 + 0, 2355 .hsync_end = 1024 + 1, 2356 .htotal = 1024 + 0 + 1 + 320, 2357 .vdisplay = 768, 2358 .vsync_start = 768 + 38, 2359 .vsync_end = 768 + 38 + 1, 2360 .vtotal = 768 + 38 + 1 + 0, 2361 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2362 }; 2363 2364 static const struct panel_desc innolux_g121x1_l03 = { 2365 .modes = &innolux_g121x1_l03_mode, 2366 .num_modes = 1, 2367 .bpc = 6, 2368 .size = { 2369 .width = 246, 2370 .height = 185, 2371 }, 2372 .delay = { 2373 .enable = 200, 2374 .unprepare = 200, 2375 .disable = 400, 2376 }, 2377 }; 2378 2379 static const struct display_timing innolux_g156hce_l01_timings = { 2380 .pixelclock = { 120000000, 141860000, 150000000 }, 2381 .hactive = { 1920, 1920, 1920 }, 2382 .hfront_porch = { 80, 90, 100 }, 2383 .hback_porch = { 80, 90, 100 }, 2384 .hsync_len = { 20, 30, 30 }, 2385 .vactive = { 1080, 1080, 1080 }, 2386 .vfront_porch = { 3, 10, 20 }, 2387 .vback_porch = { 3, 10, 20 }, 2388 .vsync_len = { 4, 10, 10 }, 2389 }; 2390 2391 static const struct panel_desc innolux_g156hce_l01 = { 2392 .timings = &innolux_g156hce_l01_timings, 2393 .num_timings = 1, 2394 .bpc = 8, 2395 .size = { 2396 .width = 344, 2397 .height = 194, 2398 }, 2399 .delay = { 2400 .prepare = 1, /* T1+T2 */ 2401 .enable = 450, /* T5 */ 2402 .disable = 200, /* T6 */ 2403 .unprepare = 10, /* T3+T7 */ 2404 }, 2405 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2406 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2407 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2408 }; 2409 2410 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2411 .clock = 69300, 2412 .hdisplay = 1366, 2413 .hsync_start = 1366 + 16, 2414 .hsync_end = 1366 + 16 + 34, 2415 .htotal = 1366 + 16 + 34 + 50, 2416 .vdisplay = 768, 2417 .vsync_start = 768 + 2, 2418 .vsync_end = 768 + 2 + 6, 2419 .vtotal = 768 + 2 + 6 + 12, 2420 }; 2421 2422 static const struct panel_desc innolux_n156bge_l21 = { 2423 .modes = &innolux_n156bge_l21_mode, 2424 .num_modes = 1, 2425 .bpc = 6, 2426 .size = { 2427 .width = 344, 2428 .height = 193, 2429 }, 2430 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2431 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2433 }; 2434 2435 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2436 .clock = 51501, 2437 .hdisplay = 1024, 2438 .hsync_start = 1024 + 128, 2439 .hsync_end = 1024 + 128 + 64, 2440 .htotal = 1024 + 128 + 64 + 128, 2441 .vdisplay = 600, 2442 .vsync_start = 600 + 16, 2443 .vsync_end = 600 + 16 + 4, 2444 .vtotal = 600 + 16 + 4 + 16, 2445 }; 2446 2447 static const struct panel_desc innolux_zj070na_01p = { 2448 .modes = &innolux_zj070na_01p_mode, 2449 .num_modes = 1, 2450 .bpc = 6, 2451 .size = { 2452 .width = 154, 2453 .height = 90, 2454 }, 2455 }; 2456 2457 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2458 .pixelclock = { 5580000, 5850000, 6200000 }, 2459 .hactive = { 320, 320, 320 }, 2460 .hfront_porch = { 30, 30, 30 }, 2461 .hback_porch = { 30, 30, 30 }, 2462 .hsync_len = { 1, 5, 17 }, 2463 .vactive = { 240, 240, 240 }, 2464 .vfront_porch = { 6, 6, 6 }, 2465 .vback_porch = { 5, 5, 5 }, 2466 .vsync_len = { 1, 2, 11 }, 2467 .flags = DISPLAY_FLAGS_DE_HIGH, 2468 }; 2469 2470 static const struct panel_desc koe_tx14d24vm1bpa = { 2471 .timings = &koe_tx14d24vm1bpa_timing, 2472 .num_timings = 1, 2473 .bpc = 6, 2474 .size = { 2475 .width = 115, 2476 .height = 86, 2477 }, 2478 }; 2479 2480 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2481 .pixelclock = { 151820000, 156720000, 159780000 }, 2482 .hactive = { 1920, 1920, 1920 }, 2483 .hfront_porch = { 105, 130, 142 }, 2484 .hback_porch = { 45, 70, 82 }, 2485 .hsync_len = { 30, 30, 30 }, 2486 .vactive = { 1200, 1200, 1200}, 2487 .vfront_porch = { 3, 5, 10 }, 2488 .vback_porch = { 2, 5, 10 }, 2489 .vsync_len = { 5, 5, 5 }, 2490 }; 2491 2492 static const struct panel_desc koe_tx26d202vm0bwa = { 2493 .timings = &koe_tx26d202vm0bwa_timing, 2494 .num_timings = 1, 2495 .bpc = 8, 2496 .size = { 2497 .width = 217, 2498 .height = 136, 2499 }, 2500 .delay = { 2501 .prepare = 1000, 2502 .enable = 1000, 2503 .unprepare = 1000, 2504 .disable = 1000, 2505 }, 2506 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2507 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2508 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2509 }; 2510 2511 static const struct display_timing koe_tx31d200vm0baa_timing = { 2512 .pixelclock = { 39600000, 43200000, 48000000 }, 2513 .hactive = { 1280, 1280, 1280 }, 2514 .hfront_porch = { 16, 36, 56 }, 2515 .hback_porch = { 16, 36, 56 }, 2516 .hsync_len = { 8, 8, 8 }, 2517 .vactive = { 480, 480, 480 }, 2518 .vfront_porch = { 6, 21, 33 }, 2519 .vback_porch = { 6, 21, 33 }, 2520 .vsync_len = { 8, 8, 8 }, 2521 .flags = DISPLAY_FLAGS_DE_HIGH, 2522 }; 2523 2524 static const struct panel_desc koe_tx31d200vm0baa = { 2525 .timings = &koe_tx31d200vm0baa_timing, 2526 .num_timings = 1, 2527 .bpc = 6, 2528 .size = { 2529 .width = 292, 2530 .height = 109, 2531 }, 2532 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2533 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2534 }; 2535 2536 static const struct display_timing kyo_tcg121xglp_timing = { 2537 .pixelclock = { 52000000, 65000000, 71000000 }, 2538 .hactive = { 1024, 1024, 1024 }, 2539 .hfront_porch = { 2, 2, 2 }, 2540 .hback_porch = { 2, 2, 2 }, 2541 .hsync_len = { 86, 124, 244 }, 2542 .vactive = { 768, 768, 768 }, 2543 .vfront_porch = { 2, 2, 2 }, 2544 .vback_porch = { 2, 2, 2 }, 2545 .vsync_len = { 6, 34, 73 }, 2546 .flags = DISPLAY_FLAGS_DE_HIGH, 2547 }; 2548 2549 static const struct panel_desc kyo_tcg121xglp = { 2550 .timings = &kyo_tcg121xglp_timing, 2551 .num_timings = 1, 2552 .bpc = 8, 2553 .size = { 2554 .width = 246, 2555 .height = 184, 2556 }, 2557 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2558 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2559 }; 2560 2561 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2562 .clock = 7000, 2563 .hdisplay = 320, 2564 .hsync_start = 320 + 20, 2565 .hsync_end = 320 + 20 + 30, 2566 .htotal = 320 + 20 + 30 + 38, 2567 .vdisplay = 240, 2568 .vsync_start = 240 + 4, 2569 .vsync_end = 240 + 4 + 3, 2570 .vtotal = 240 + 4 + 3 + 15, 2571 }; 2572 2573 static const struct panel_desc lemaker_bl035_rgb_002 = { 2574 .modes = &lemaker_bl035_rgb_002_mode, 2575 .num_modes = 1, 2576 .size = { 2577 .width = 70, 2578 .height = 52, 2579 }, 2580 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2581 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2582 }; 2583 2584 static const struct drm_display_mode lg_lb070wv8_mode = { 2585 .clock = 33246, 2586 .hdisplay = 800, 2587 .hsync_start = 800 + 88, 2588 .hsync_end = 800 + 88 + 80, 2589 .htotal = 800 + 88 + 80 + 88, 2590 .vdisplay = 480, 2591 .vsync_start = 480 + 10, 2592 .vsync_end = 480 + 10 + 25, 2593 .vtotal = 480 + 10 + 25 + 10, 2594 }; 2595 2596 static const struct panel_desc lg_lb070wv8 = { 2597 .modes = &lg_lb070wv8_mode, 2598 .num_modes = 1, 2599 .bpc = 8, 2600 .size = { 2601 .width = 151, 2602 .height = 91, 2603 }, 2604 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2605 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2606 }; 2607 2608 static const struct display_timing logictechno_lt161010_2nh_timing = { 2609 .pixelclock = { 26400000, 33300000, 46800000 }, 2610 .hactive = { 800, 800, 800 }, 2611 .hfront_porch = { 16, 210, 354 }, 2612 .hback_porch = { 46, 46, 46 }, 2613 .hsync_len = { 1, 20, 40 }, 2614 .vactive = { 480, 480, 480 }, 2615 .vfront_porch = { 7, 22, 147 }, 2616 .vback_porch = { 23, 23, 23 }, 2617 .vsync_len = { 1, 10, 20 }, 2618 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2619 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2620 DISPLAY_FLAGS_SYNC_POSEDGE, 2621 }; 2622 2623 static const struct panel_desc logictechno_lt161010_2nh = { 2624 .timings = &logictechno_lt161010_2nh_timing, 2625 .num_timings = 1, 2626 .bpc = 6, 2627 .size = { 2628 .width = 154, 2629 .height = 86, 2630 }, 2631 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2632 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2633 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2634 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2635 .connector_type = DRM_MODE_CONNECTOR_DPI, 2636 }; 2637 2638 static const struct display_timing logictechno_lt170410_2whc_timing = { 2639 .pixelclock = { 68900000, 71100000, 73400000 }, 2640 .hactive = { 1280, 1280, 1280 }, 2641 .hfront_porch = { 23, 60, 71 }, 2642 .hback_porch = { 23, 60, 71 }, 2643 .hsync_len = { 15, 40, 47 }, 2644 .vactive = { 800, 800, 800 }, 2645 .vfront_porch = { 5, 7, 10 }, 2646 .vback_porch = { 5, 7, 10 }, 2647 .vsync_len = { 6, 9, 12 }, 2648 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2649 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2650 DISPLAY_FLAGS_SYNC_POSEDGE, 2651 }; 2652 2653 static const struct panel_desc logictechno_lt170410_2whc = { 2654 .timings = &logictechno_lt170410_2whc_timing, 2655 .num_timings = 1, 2656 .bpc = 8, 2657 .size = { 2658 .width = 217, 2659 .height = 136, 2660 }, 2661 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2662 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2663 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2664 }; 2665 2666 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2667 .clock = 33000, 2668 .hdisplay = 800, 2669 .hsync_start = 800 + 112, 2670 .hsync_end = 800 + 112 + 3, 2671 .htotal = 800 + 112 + 3 + 85, 2672 .vdisplay = 480, 2673 .vsync_start = 480 + 38, 2674 .vsync_end = 480 + 38 + 3, 2675 .vtotal = 480 + 38 + 3 + 29, 2676 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2677 }; 2678 2679 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2680 .modes = &logictechno_lttd800480070_l2rt_mode, 2681 .num_modes = 1, 2682 .bpc = 8, 2683 .size = { 2684 .width = 154, 2685 .height = 86, 2686 }, 2687 .delay = { 2688 .prepare = 45, 2689 .enable = 100, 2690 .disable = 100, 2691 .unprepare = 45 2692 }, 2693 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2694 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2695 .connector_type = DRM_MODE_CONNECTOR_DPI, 2696 }; 2697 2698 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2699 .clock = 33000, 2700 .hdisplay = 800, 2701 .hsync_start = 800 + 154, 2702 .hsync_end = 800 + 154 + 3, 2703 .htotal = 800 + 154 + 3 + 43, 2704 .vdisplay = 480, 2705 .vsync_start = 480 + 47, 2706 .vsync_end = 480 + 47 + 3, 2707 .vtotal = 480 + 47 + 3 + 20, 2708 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2709 }; 2710 2711 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2712 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2713 .num_modes = 1, 2714 .bpc = 8, 2715 .size = { 2716 .width = 154, 2717 .height = 86, 2718 }, 2719 .delay = { 2720 .prepare = 45, 2721 .enable = 100, 2722 .disable = 100, 2723 .unprepare = 45 2724 }, 2725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2726 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2727 .connector_type = DRM_MODE_CONNECTOR_DPI, 2728 }; 2729 2730 static const struct drm_display_mode logicpd_type_28_mode = { 2731 .clock = 9107, 2732 .hdisplay = 480, 2733 .hsync_start = 480 + 3, 2734 .hsync_end = 480 + 3 + 42, 2735 .htotal = 480 + 3 + 42 + 2, 2736 2737 .vdisplay = 272, 2738 .vsync_start = 272 + 2, 2739 .vsync_end = 272 + 2 + 11, 2740 .vtotal = 272 + 2 + 11 + 3, 2741 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2742 }; 2743 2744 static const struct panel_desc logicpd_type_28 = { 2745 .modes = &logicpd_type_28_mode, 2746 .num_modes = 1, 2747 .bpc = 8, 2748 .size = { 2749 .width = 105, 2750 .height = 67, 2751 }, 2752 .delay = { 2753 .prepare = 200, 2754 .enable = 200, 2755 .unprepare = 200, 2756 .disable = 200, 2757 }, 2758 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2759 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2760 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2761 .connector_type = DRM_MODE_CONNECTOR_DPI, 2762 }; 2763 2764 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2765 .clock = 30400, 2766 .hdisplay = 800, 2767 .hsync_start = 800 + 0, 2768 .hsync_end = 800 + 1, 2769 .htotal = 800 + 0 + 1 + 160, 2770 .vdisplay = 480, 2771 .vsync_start = 480 + 0, 2772 .vsync_end = 480 + 48 + 1, 2773 .vtotal = 480 + 48 + 1 + 0, 2774 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2775 }; 2776 2777 static const struct panel_desc mitsubishi_aa070mc01 = { 2778 .modes = &mitsubishi_aa070mc01_mode, 2779 .num_modes = 1, 2780 .bpc = 8, 2781 .size = { 2782 .width = 152, 2783 .height = 91, 2784 }, 2785 2786 .delay = { 2787 .enable = 200, 2788 .unprepare = 200, 2789 .disable = 400, 2790 }, 2791 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2792 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2793 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2794 }; 2795 2796 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 2797 .pixelclock = { 29000000, 33000000, 38000000 }, 2798 .hactive = { 800, 800, 800 }, 2799 .hfront_porch = { 180, 210, 240 }, 2800 .hback_porch = { 16, 16, 16 }, 2801 .hsync_len = { 30, 30, 30 }, 2802 .vactive = { 480, 480, 480 }, 2803 .vfront_porch = { 12, 22, 32 }, 2804 .vback_porch = { 10, 10, 10 }, 2805 .vsync_len = { 13, 13, 13 }, 2806 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2807 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2808 DISPLAY_FLAGS_SYNC_POSEDGE, 2809 }; 2810 2811 static const struct panel_desc multi_inno_mi0700s4t_6 = { 2812 .timings = &multi_inno_mi0700s4t_6_timing, 2813 .num_timings = 1, 2814 .bpc = 8, 2815 .size = { 2816 .width = 154, 2817 .height = 86, 2818 }, 2819 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2820 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2821 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2822 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2823 .connector_type = DRM_MODE_CONNECTOR_DPI, 2824 }; 2825 2826 static const struct display_timing multi_inno_mi0800ft_9_timing = { 2827 .pixelclock = { 32000000, 40000000, 50000000 }, 2828 .hactive = { 800, 800, 800 }, 2829 .hfront_porch = { 16, 210, 354 }, 2830 .hback_porch = { 6, 26, 45 }, 2831 .hsync_len = { 1, 20, 40 }, 2832 .vactive = { 600, 600, 600 }, 2833 .vfront_porch = { 1, 12, 77 }, 2834 .vback_porch = { 3, 13, 22 }, 2835 .vsync_len = { 1, 10, 20 }, 2836 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2837 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2838 DISPLAY_FLAGS_SYNC_POSEDGE, 2839 }; 2840 2841 static const struct panel_desc multi_inno_mi0800ft_9 = { 2842 .timings = &multi_inno_mi0800ft_9_timing, 2843 .num_timings = 1, 2844 .bpc = 8, 2845 .size = { 2846 .width = 162, 2847 .height = 122, 2848 }, 2849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2850 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2851 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2852 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2853 .connector_type = DRM_MODE_CONNECTOR_DPI, 2854 }; 2855 2856 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 2857 .pixelclock = { 68900000, 70000000, 73400000 }, 2858 .hactive = { 1280, 1280, 1280 }, 2859 .hfront_porch = { 30, 60, 71 }, 2860 .hback_porch = { 30, 60, 71 }, 2861 .hsync_len = { 10, 10, 48 }, 2862 .vactive = { 800, 800, 800 }, 2863 .vfront_porch = { 5, 10, 10 }, 2864 .vback_porch = { 5, 10, 10 }, 2865 .vsync_len = { 5, 6, 13 }, 2866 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2867 DISPLAY_FLAGS_DE_HIGH, 2868 }; 2869 2870 static const struct panel_desc multi_inno_mi1010ait_1cp = { 2871 .timings = &multi_inno_mi1010ait_1cp_timing, 2872 .num_timings = 1, 2873 .bpc = 8, 2874 .size = { 2875 .width = 217, 2876 .height = 136, 2877 }, 2878 .delay = { 2879 .enable = 50, 2880 .disable = 50, 2881 }, 2882 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2883 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2884 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2885 }; 2886 2887 static const struct display_timing nec_nl12880bc20_05_timing = { 2888 .pixelclock = { 67000000, 71000000, 75000000 }, 2889 .hactive = { 1280, 1280, 1280 }, 2890 .hfront_porch = { 2, 30, 30 }, 2891 .hback_porch = { 6, 100, 100 }, 2892 .hsync_len = { 2, 30, 30 }, 2893 .vactive = { 800, 800, 800 }, 2894 .vfront_porch = { 5, 5, 5 }, 2895 .vback_porch = { 11, 11, 11 }, 2896 .vsync_len = { 7, 7, 7 }, 2897 }; 2898 2899 static const struct panel_desc nec_nl12880bc20_05 = { 2900 .timings = &nec_nl12880bc20_05_timing, 2901 .num_timings = 1, 2902 .bpc = 8, 2903 .size = { 2904 .width = 261, 2905 .height = 163, 2906 }, 2907 .delay = { 2908 .enable = 50, 2909 .disable = 50, 2910 }, 2911 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2912 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2913 }; 2914 2915 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 2916 .clock = 10870, 2917 .hdisplay = 480, 2918 .hsync_start = 480 + 2, 2919 .hsync_end = 480 + 2 + 41, 2920 .htotal = 480 + 2 + 41 + 2, 2921 .vdisplay = 272, 2922 .vsync_start = 272 + 2, 2923 .vsync_end = 272 + 2 + 4, 2924 .vtotal = 272 + 2 + 4 + 2, 2925 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2926 }; 2927 2928 static const struct panel_desc nec_nl4827hc19_05b = { 2929 .modes = &nec_nl4827hc19_05b_mode, 2930 .num_modes = 1, 2931 .bpc = 8, 2932 .size = { 2933 .width = 95, 2934 .height = 54, 2935 }, 2936 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2937 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2938 }; 2939 2940 static const struct drm_display_mode netron_dy_e231732_mode = { 2941 .clock = 66000, 2942 .hdisplay = 1024, 2943 .hsync_start = 1024 + 160, 2944 .hsync_end = 1024 + 160 + 70, 2945 .htotal = 1024 + 160 + 70 + 90, 2946 .vdisplay = 600, 2947 .vsync_start = 600 + 127, 2948 .vsync_end = 600 + 127 + 20, 2949 .vtotal = 600 + 127 + 20 + 3, 2950 }; 2951 2952 static const struct panel_desc netron_dy_e231732 = { 2953 .modes = &netron_dy_e231732_mode, 2954 .num_modes = 1, 2955 .size = { 2956 .width = 154, 2957 .height = 87, 2958 }, 2959 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2960 }; 2961 2962 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 2963 .clock = 9000, 2964 .hdisplay = 480, 2965 .hsync_start = 480 + 2, 2966 .hsync_end = 480 + 2 + 41, 2967 .htotal = 480 + 2 + 41 + 2, 2968 .vdisplay = 272, 2969 .vsync_start = 272 + 2, 2970 .vsync_end = 272 + 2 + 10, 2971 .vtotal = 272 + 2 + 10 + 2, 2972 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2973 }; 2974 2975 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 2976 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 2977 .num_modes = 1, 2978 .bpc = 8, 2979 .size = { 2980 .width = 95, 2981 .height = 54, 2982 }, 2983 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2984 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2985 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 2986 .connector_type = DRM_MODE_CONNECTOR_DPI, 2987 }; 2988 2989 static const struct display_timing nlt_nl192108ac18_02d_timing = { 2990 .pixelclock = { 130000000, 148350000, 163000000 }, 2991 .hactive = { 1920, 1920, 1920 }, 2992 .hfront_porch = { 80, 100, 100 }, 2993 .hback_porch = { 100, 120, 120 }, 2994 .hsync_len = { 50, 60, 60 }, 2995 .vactive = { 1080, 1080, 1080 }, 2996 .vfront_porch = { 12, 30, 30 }, 2997 .vback_porch = { 4, 10, 10 }, 2998 .vsync_len = { 4, 5, 5 }, 2999 }; 3000 3001 static const struct panel_desc nlt_nl192108ac18_02d = { 3002 .timings = &nlt_nl192108ac18_02d_timing, 3003 .num_timings = 1, 3004 .bpc = 8, 3005 .size = { 3006 .width = 344, 3007 .height = 194, 3008 }, 3009 .delay = { 3010 .unprepare = 500, 3011 }, 3012 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3013 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3014 }; 3015 3016 static const struct drm_display_mode nvd_9128_mode = { 3017 .clock = 29500, 3018 .hdisplay = 800, 3019 .hsync_start = 800 + 130, 3020 .hsync_end = 800 + 130 + 98, 3021 .htotal = 800 + 0 + 130 + 98, 3022 .vdisplay = 480, 3023 .vsync_start = 480 + 10, 3024 .vsync_end = 480 + 10 + 50, 3025 .vtotal = 480 + 0 + 10 + 50, 3026 }; 3027 3028 static const struct panel_desc nvd_9128 = { 3029 .modes = &nvd_9128_mode, 3030 .num_modes = 1, 3031 .bpc = 8, 3032 .size = { 3033 .width = 156, 3034 .height = 88, 3035 }, 3036 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3037 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3038 }; 3039 3040 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3041 .pixelclock = { 30000000, 30000000, 40000000 }, 3042 .hactive = { 800, 800, 800 }, 3043 .hfront_porch = { 40, 40, 40 }, 3044 .hback_porch = { 40, 40, 40 }, 3045 .hsync_len = { 1, 48, 48 }, 3046 .vactive = { 480, 480, 480 }, 3047 .vfront_porch = { 13, 13, 13 }, 3048 .vback_porch = { 29, 29, 29 }, 3049 .vsync_len = { 3, 3, 3 }, 3050 .flags = DISPLAY_FLAGS_DE_HIGH, 3051 }; 3052 3053 static const struct panel_desc okaya_rs800480t_7x0gp = { 3054 .timings = &okaya_rs800480t_7x0gp_timing, 3055 .num_timings = 1, 3056 .bpc = 6, 3057 .size = { 3058 .width = 154, 3059 .height = 87, 3060 }, 3061 .delay = { 3062 .prepare = 41, 3063 .enable = 50, 3064 .unprepare = 41, 3065 .disable = 50, 3066 }, 3067 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3068 }; 3069 3070 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3071 .clock = 9000, 3072 .hdisplay = 480, 3073 .hsync_start = 480 + 5, 3074 .hsync_end = 480 + 5 + 30, 3075 .htotal = 480 + 5 + 30 + 10, 3076 .vdisplay = 272, 3077 .vsync_start = 272 + 8, 3078 .vsync_end = 272 + 8 + 5, 3079 .vtotal = 272 + 8 + 5 + 3, 3080 }; 3081 3082 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3083 .modes = &olimex_lcd_olinuxino_43ts_mode, 3084 .num_modes = 1, 3085 .size = { 3086 .width = 95, 3087 .height = 54, 3088 }, 3089 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3090 }; 3091 3092 /* 3093 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3094 * pixel clocks, but this is the timing that was being used in the Adafruit 3095 * installation instructions. 3096 */ 3097 static const struct drm_display_mode ontat_yx700wv03_mode = { 3098 .clock = 29500, 3099 .hdisplay = 800, 3100 .hsync_start = 824, 3101 .hsync_end = 896, 3102 .htotal = 992, 3103 .vdisplay = 480, 3104 .vsync_start = 483, 3105 .vsync_end = 493, 3106 .vtotal = 500, 3107 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3108 }; 3109 3110 /* 3111 * Specification at: 3112 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3113 */ 3114 static const struct panel_desc ontat_yx700wv03 = { 3115 .modes = &ontat_yx700wv03_mode, 3116 .num_modes = 1, 3117 .bpc = 8, 3118 .size = { 3119 .width = 154, 3120 .height = 83, 3121 }, 3122 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3123 }; 3124 3125 static const struct drm_display_mode ortustech_com37h3m_mode = { 3126 .clock = 22230, 3127 .hdisplay = 480, 3128 .hsync_start = 480 + 40, 3129 .hsync_end = 480 + 40 + 10, 3130 .htotal = 480 + 40 + 10 + 40, 3131 .vdisplay = 640, 3132 .vsync_start = 640 + 4, 3133 .vsync_end = 640 + 4 + 2, 3134 .vtotal = 640 + 4 + 2 + 4, 3135 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3136 }; 3137 3138 static const struct panel_desc ortustech_com37h3m = { 3139 .modes = &ortustech_com37h3m_mode, 3140 .num_modes = 1, 3141 .bpc = 8, 3142 .size = { 3143 .width = 56, /* 56.16mm */ 3144 .height = 75, /* 74.88mm */ 3145 }, 3146 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3147 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3148 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3149 }; 3150 3151 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3152 .clock = 25000, 3153 .hdisplay = 480, 3154 .hsync_start = 480 + 10, 3155 .hsync_end = 480 + 10 + 10, 3156 .htotal = 480 + 10 + 10 + 15, 3157 .vdisplay = 800, 3158 .vsync_start = 800 + 3, 3159 .vsync_end = 800 + 3 + 3, 3160 .vtotal = 800 + 3 + 3 + 3, 3161 }; 3162 3163 static const struct panel_desc ortustech_com43h4m85ulc = { 3164 .modes = &ortustech_com43h4m85ulc_mode, 3165 .num_modes = 1, 3166 .bpc = 6, 3167 .size = { 3168 .width = 56, 3169 .height = 93, 3170 }, 3171 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3172 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3173 .connector_type = DRM_MODE_CONNECTOR_DPI, 3174 }; 3175 3176 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3177 .clock = 33000, 3178 .hdisplay = 800, 3179 .hsync_start = 800 + 210, 3180 .hsync_end = 800 + 210 + 30, 3181 .htotal = 800 + 210 + 30 + 16, 3182 .vdisplay = 480, 3183 .vsync_start = 480 + 22, 3184 .vsync_end = 480 + 22 + 13, 3185 .vtotal = 480 + 22 + 13 + 10, 3186 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3187 }; 3188 3189 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3190 .modes = &osddisplays_osd070t1718_19ts_mode, 3191 .num_modes = 1, 3192 .bpc = 8, 3193 .size = { 3194 .width = 152, 3195 .height = 91, 3196 }, 3197 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3198 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3199 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3200 .connector_type = DRM_MODE_CONNECTOR_DPI, 3201 }; 3202 3203 static const struct drm_display_mode pda_91_00156_a0_mode = { 3204 .clock = 33300, 3205 .hdisplay = 800, 3206 .hsync_start = 800 + 1, 3207 .hsync_end = 800 + 1 + 64, 3208 .htotal = 800 + 1 + 64 + 64, 3209 .vdisplay = 480, 3210 .vsync_start = 480 + 1, 3211 .vsync_end = 480 + 1 + 23, 3212 .vtotal = 480 + 1 + 23 + 22, 3213 }; 3214 3215 static const struct panel_desc pda_91_00156_a0 = { 3216 .modes = &pda_91_00156_a0_mode, 3217 .num_modes = 1, 3218 .size = { 3219 .width = 152, 3220 .height = 91, 3221 }, 3222 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3223 }; 3224 3225 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3226 .clock = 24750, 3227 .hdisplay = 800, 3228 .hsync_start = 800 + 54, 3229 .hsync_end = 800 + 54 + 2, 3230 .htotal = 800 + 54 + 2 + 44, 3231 .vdisplay = 480, 3232 .vsync_start = 480 + 49, 3233 .vsync_end = 480 + 49 + 2, 3234 .vtotal = 480 + 49 + 2 + 22, 3235 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3236 }; 3237 3238 static const struct panel_desc powertip_ph800480t013_idf02 = { 3239 .modes = &powertip_ph800480t013_idf02_mode, 3240 .num_modes = 1, 3241 .bpc = 8, 3242 .size = { 3243 .width = 152, 3244 .height = 91, 3245 }, 3246 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3247 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3248 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3249 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3250 .connector_type = DRM_MODE_CONNECTOR_DPI, 3251 }; 3252 3253 static const struct drm_display_mode qd43003c0_40_mode = { 3254 .clock = 9000, 3255 .hdisplay = 480, 3256 .hsync_start = 480 + 8, 3257 .hsync_end = 480 + 8 + 4, 3258 .htotal = 480 + 8 + 4 + 39, 3259 .vdisplay = 272, 3260 .vsync_start = 272 + 4, 3261 .vsync_end = 272 + 4 + 10, 3262 .vtotal = 272 + 4 + 10 + 2, 3263 }; 3264 3265 static const struct panel_desc qd43003c0_40 = { 3266 .modes = &qd43003c0_40_mode, 3267 .num_modes = 1, 3268 .bpc = 8, 3269 .size = { 3270 .width = 95, 3271 .height = 53, 3272 }, 3273 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3274 }; 3275 3276 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3277 { /* 60 Hz */ 3278 .clock = 10800, 3279 .hdisplay = 480, 3280 .hsync_start = 480 + 77, 3281 .hsync_end = 480 + 77 + 41, 3282 .htotal = 480 + 77 + 41 + 2, 3283 .vdisplay = 272, 3284 .vsync_start = 272 + 16, 3285 .vsync_end = 272 + 16 + 10, 3286 .vtotal = 272 + 16 + 10 + 2, 3287 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3288 }, 3289 { /* 50 Hz */ 3290 .clock = 10800, 3291 .hdisplay = 480, 3292 .hsync_start = 480 + 17, 3293 .hsync_end = 480 + 17 + 41, 3294 .htotal = 480 + 17 + 41 + 2, 3295 .vdisplay = 272, 3296 .vsync_start = 272 + 116, 3297 .vsync_end = 272 + 116 + 10, 3298 .vtotal = 272 + 116 + 10 + 2, 3299 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3300 }, 3301 }; 3302 3303 static const struct panel_desc qishenglong_gopher2b_lcd = { 3304 .modes = qishenglong_gopher2b_lcd_modes, 3305 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3306 .bpc = 8, 3307 .size = { 3308 .width = 95, 3309 .height = 54, 3310 }, 3311 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3312 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3313 .connector_type = DRM_MODE_CONNECTOR_DPI, 3314 }; 3315 3316 static const struct display_timing rocktech_rk043fn48h_timing = { 3317 .pixelclock = { 6000000, 9000000, 12000000 }, 3318 .hactive = { 480, 480, 480 }, 3319 .hback_porch = { 8, 43, 43 }, 3320 .hfront_porch = { 2, 8, 8 }, 3321 .hsync_len = { 1, 1, 1 }, 3322 .vactive = { 272, 272, 272 }, 3323 .vback_porch = { 2, 12, 12 }, 3324 .vfront_porch = { 1, 4, 4 }, 3325 .vsync_len = { 1, 10, 10 }, 3326 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3327 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3328 }; 3329 3330 static const struct panel_desc rocktech_rk043fn48h = { 3331 .timings = &rocktech_rk043fn48h_timing, 3332 .num_timings = 1, 3333 .bpc = 8, 3334 .size = { 3335 .width = 95, 3336 .height = 54, 3337 }, 3338 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3339 .connector_type = DRM_MODE_CONNECTOR_DPI, 3340 }; 3341 3342 static const struct display_timing rocktech_rk070er9427_timing = { 3343 .pixelclock = { 26400000, 33300000, 46800000 }, 3344 .hactive = { 800, 800, 800 }, 3345 .hfront_porch = { 16, 210, 354 }, 3346 .hback_porch = { 46, 46, 46 }, 3347 .hsync_len = { 1, 1, 1 }, 3348 .vactive = { 480, 480, 480 }, 3349 .vfront_porch = { 7, 22, 147 }, 3350 .vback_porch = { 23, 23, 23 }, 3351 .vsync_len = { 1, 1, 1 }, 3352 .flags = DISPLAY_FLAGS_DE_HIGH, 3353 }; 3354 3355 static const struct panel_desc rocktech_rk070er9427 = { 3356 .timings = &rocktech_rk070er9427_timing, 3357 .num_timings = 1, 3358 .bpc = 6, 3359 .size = { 3360 .width = 154, 3361 .height = 86, 3362 }, 3363 .delay = { 3364 .prepare = 41, 3365 .enable = 50, 3366 .unprepare = 41, 3367 .disable = 50, 3368 }, 3369 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3370 }; 3371 3372 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3373 .clock = 71100, 3374 .hdisplay = 1280, 3375 .hsync_start = 1280 + 48, 3376 .hsync_end = 1280 + 48 + 32, 3377 .htotal = 1280 + 48 + 32 + 80, 3378 .vdisplay = 800, 3379 .vsync_start = 800 + 2, 3380 .vsync_end = 800 + 2 + 5, 3381 .vtotal = 800 + 2 + 5 + 16, 3382 }; 3383 3384 static const struct panel_desc rocktech_rk101ii01d_ct = { 3385 .modes = &rocktech_rk101ii01d_ct_mode, 3386 .bpc = 8, 3387 .num_modes = 1, 3388 .size = { 3389 .width = 217, 3390 .height = 136, 3391 }, 3392 .delay = { 3393 .prepare = 50, 3394 .disable = 50, 3395 }, 3396 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3397 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3399 }; 3400 3401 static const struct display_timing samsung_ltl101al01_timing = { 3402 .pixelclock = { 66663000, 66663000, 66663000 }, 3403 .hactive = { 1280, 1280, 1280 }, 3404 .hfront_porch = { 18, 18, 18 }, 3405 .hback_porch = { 36, 36, 36 }, 3406 .hsync_len = { 16, 16, 16 }, 3407 .vactive = { 800, 800, 800 }, 3408 .vfront_porch = { 4, 4, 4 }, 3409 .vback_porch = { 16, 16, 16 }, 3410 .vsync_len = { 3, 3, 3 }, 3411 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3412 }; 3413 3414 static const struct panel_desc samsung_ltl101al01 = { 3415 .timings = &samsung_ltl101al01_timing, 3416 .num_timings = 1, 3417 .bpc = 8, 3418 .size = { 3419 .width = 217, 3420 .height = 135, 3421 }, 3422 .delay = { 3423 .prepare = 40, 3424 .enable = 300, 3425 .disable = 200, 3426 .unprepare = 600, 3427 }, 3428 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3429 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3430 }; 3431 3432 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3433 .clock = 54030, 3434 .hdisplay = 1024, 3435 .hsync_start = 1024 + 24, 3436 .hsync_end = 1024 + 24 + 136, 3437 .htotal = 1024 + 24 + 136 + 160, 3438 .vdisplay = 600, 3439 .vsync_start = 600 + 3, 3440 .vsync_end = 600 + 3 + 6, 3441 .vtotal = 600 + 3 + 6 + 61, 3442 }; 3443 3444 static const struct panel_desc samsung_ltn101nt05 = { 3445 .modes = &samsung_ltn101nt05_mode, 3446 .num_modes = 1, 3447 .bpc = 6, 3448 .size = { 3449 .width = 223, 3450 .height = 125, 3451 }, 3452 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3453 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3454 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3455 }; 3456 3457 static const struct display_timing satoz_sat050at40h12r2_timing = { 3458 .pixelclock = {33300000, 33300000, 50000000}, 3459 .hactive = {800, 800, 800}, 3460 .hfront_porch = {16, 210, 354}, 3461 .hback_porch = {46, 46, 46}, 3462 .hsync_len = {1, 1, 40}, 3463 .vactive = {480, 480, 480}, 3464 .vfront_porch = {7, 22, 147}, 3465 .vback_porch = {23, 23, 23}, 3466 .vsync_len = {1, 1, 20}, 3467 }; 3468 3469 static const struct panel_desc satoz_sat050at40h12r2 = { 3470 .timings = &satoz_sat050at40h12r2_timing, 3471 .num_timings = 1, 3472 .bpc = 8, 3473 .size = { 3474 .width = 108, 3475 .height = 65, 3476 }, 3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3478 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3479 }; 3480 3481 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3482 .clock = 33260, 3483 .hdisplay = 800, 3484 .hsync_start = 800 + 64, 3485 .hsync_end = 800 + 64 + 128, 3486 .htotal = 800 + 64 + 128 + 64, 3487 .vdisplay = 480, 3488 .vsync_start = 480 + 8, 3489 .vsync_end = 480 + 8 + 2, 3490 .vtotal = 480 + 8 + 2 + 35, 3491 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3492 }; 3493 3494 static const struct panel_desc sharp_lq070y3dg3b = { 3495 .modes = &sharp_lq070y3dg3b_mode, 3496 .num_modes = 1, 3497 .bpc = 8, 3498 .size = { 3499 .width = 152, /* 152.4mm */ 3500 .height = 91, /* 91.4mm */ 3501 }, 3502 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3503 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3504 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3505 }; 3506 3507 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3508 .clock = 5500, 3509 .hdisplay = 240, 3510 .hsync_start = 240 + 16, 3511 .hsync_end = 240 + 16 + 7, 3512 .htotal = 240 + 16 + 7 + 5, 3513 .vdisplay = 320, 3514 .vsync_start = 320 + 9, 3515 .vsync_end = 320 + 9 + 1, 3516 .vtotal = 320 + 9 + 1 + 7, 3517 }; 3518 3519 static const struct panel_desc sharp_lq035q7db03 = { 3520 .modes = &sharp_lq035q7db03_mode, 3521 .num_modes = 1, 3522 .bpc = 6, 3523 .size = { 3524 .width = 54, 3525 .height = 72, 3526 }, 3527 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3528 }; 3529 3530 static const struct display_timing sharp_lq101k1ly04_timing = { 3531 .pixelclock = { 60000000, 65000000, 80000000 }, 3532 .hactive = { 1280, 1280, 1280 }, 3533 .hfront_porch = { 20, 20, 20 }, 3534 .hback_porch = { 20, 20, 20 }, 3535 .hsync_len = { 10, 10, 10 }, 3536 .vactive = { 800, 800, 800 }, 3537 .vfront_porch = { 4, 4, 4 }, 3538 .vback_porch = { 4, 4, 4 }, 3539 .vsync_len = { 4, 4, 4 }, 3540 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3541 }; 3542 3543 static const struct panel_desc sharp_lq101k1ly04 = { 3544 .timings = &sharp_lq101k1ly04_timing, 3545 .num_timings = 1, 3546 .bpc = 8, 3547 .size = { 3548 .width = 217, 3549 .height = 136, 3550 }, 3551 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3552 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3553 }; 3554 3555 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3556 { /* 50 Hz */ 3557 .clock = 3000, 3558 .hdisplay = 240, 3559 .hsync_start = 240 + 58, 3560 .hsync_end = 240 + 58 + 1, 3561 .htotal = 240 + 58 + 1 + 1, 3562 .vdisplay = 160, 3563 .vsync_start = 160 + 24, 3564 .vsync_end = 160 + 24 + 10, 3565 .vtotal = 160 + 24 + 10 + 6, 3566 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3567 }, 3568 { /* 60 Hz */ 3569 .clock = 3000, 3570 .hdisplay = 240, 3571 .hsync_start = 240 + 8, 3572 .hsync_end = 240 + 8 + 1, 3573 .htotal = 240 + 8 + 1 + 1, 3574 .vdisplay = 160, 3575 .vsync_start = 160 + 24, 3576 .vsync_end = 160 + 24 + 10, 3577 .vtotal = 160 + 24 + 10 + 6, 3578 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3579 }, 3580 }; 3581 3582 static const struct panel_desc sharp_ls020b1dd01d = { 3583 .modes = sharp_ls020b1dd01d_modes, 3584 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3585 .bpc = 6, 3586 .size = { 3587 .width = 42, 3588 .height = 28, 3589 }, 3590 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3591 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3592 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3593 | DRM_BUS_FLAG_SHARP_SIGNALS, 3594 }; 3595 3596 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3597 .clock = 33300, 3598 .hdisplay = 800, 3599 .hsync_start = 800 + 1, 3600 .hsync_end = 800 + 1 + 64, 3601 .htotal = 800 + 1 + 64 + 64, 3602 .vdisplay = 480, 3603 .vsync_start = 480 + 1, 3604 .vsync_end = 480 + 1 + 23, 3605 .vtotal = 480 + 1 + 23 + 22, 3606 }; 3607 3608 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3609 .modes = &shelly_sca07010_bfn_lnn_mode, 3610 .num_modes = 1, 3611 .size = { 3612 .width = 152, 3613 .height = 91, 3614 }, 3615 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3616 }; 3617 3618 static const struct drm_display_mode starry_kr070pe2t_mode = { 3619 .clock = 33000, 3620 .hdisplay = 800, 3621 .hsync_start = 800 + 209, 3622 .hsync_end = 800 + 209 + 1, 3623 .htotal = 800 + 209 + 1 + 45, 3624 .vdisplay = 480, 3625 .vsync_start = 480 + 22, 3626 .vsync_end = 480 + 22 + 1, 3627 .vtotal = 480 + 22 + 1 + 22, 3628 }; 3629 3630 static const struct panel_desc starry_kr070pe2t = { 3631 .modes = &starry_kr070pe2t_mode, 3632 .num_modes = 1, 3633 .bpc = 8, 3634 .size = { 3635 .width = 152, 3636 .height = 86, 3637 }, 3638 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3639 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3640 .connector_type = DRM_MODE_CONNECTOR_DPI, 3641 }; 3642 3643 static const struct display_timing startek_kd070wvfpa_mode = { 3644 .pixelclock = { 25200000, 27200000, 30500000 }, 3645 .hactive = { 800, 800, 800 }, 3646 .hfront_porch = { 19, 44, 115 }, 3647 .hback_porch = { 5, 16, 101 }, 3648 .hsync_len = { 1, 2, 100 }, 3649 .vactive = { 480, 480, 480 }, 3650 .vfront_porch = { 5, 43, 67 }, 3651 .vback_porch = { 5, 5, 67 }, 3652 .vsync_len = { 1, 2, 66 }, 3653 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3654 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3655 DISPLAY_FLAGS_SYNC_POSEDGE, 3656 }; 3657 3658 static const struct panel_desc startek_kd070wvfpa = { 3659 .timings = &startek_kd070wvfpa_mode, 3660 .num_timings = 1, 3661 .bpc = 8, 3662 .size = { 3663 .width = 152, 3664 .height = 91, 3665 }, 3666 .delay = { 3667 .prepare = 20, 3668 .enable = 200, 3669 .disable = 200, 3670 }, 3671 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3672 .connector_type = DRM_MODE_CONNECTOR_DPI, 3673 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3674 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3675 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3676 }; 3677 3678 static const struct display_timing tsd_tst043015cmhx_timing = { 3679 .pixelclock = { 5000000, 9000000, 12000000 }, 3680 .hactive = { 480, 480, 480 }, 3681 .hfront_porch = { 4, 5, 65 }, 3682 .hback_porch = { 36, 40, 255 }, 3683 .hsync_len = { 1, 1, 1 }, 3684 .vactive = { 272, 272, 272 }, 3685 .vfront_porch = { 2, 8, 97 }, 3686 .vback_porch = { 3, 8, 31 }, 3687 .vsync_len = { 1, 1, 1 }, 3688 3689 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3690 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3691 }; 3692 3693 static const struct panel_desc tsd_tst043015cmhx = { 3694 .timings = &tsd_tst043015cmhx_timing, 3695 .num_timings = 1, 3696 .bpc = 8, 3697 .size = { 3698 .width = 105, 3699 .height = 67, 3700 }, 3701 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3702 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3703 }; 3704 3705 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3706 .clock = 30000, 3707 .hdisplay = 800, 3708 .hsync_start = 800 + 39, 3709 .hsync_end = 800 + 39 + 47, 3710 .htotal = 800 + 39 + 47 + 39, 3711 .vdisplay = 480, 3712 .vsync_start = 480 + 13, 3713 .vsync_end = 480 + 13 + 2, 3714 .vtotal = 480 + 13 + 2 + 29, 3715 }; 3716 3717 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3718 .modes = &tfc_s9700rtwv43tr_01b_mode, 3719 .num_modes = 1, 3720 .bpc = 8, 3721 .size = { 3722 .width = 155, 3723 .height = 90, 3724 }, 3725 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3726 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3727 }; 3728 3729 static const struct display_timing tianma_tm070jdhg30_timing = { 3730 .pixelclock = { 62600000, 68200000, 78100000 }, 3731 .hactive = { 1280, 1280, 1280 }, 3732 .hfront_porch = { 15, 64, 159 }, 3733 .hback_porch = { 5, 5, 5 }, 3734 .hsync_len = { 1, 1, 256 }, 3735 .vactive = { 800, 800, 800 }, 3736 .vfront_porch = { 3, 40, 99 }, 3737 .vback_porch = { 2, 2, 2 }, 3738 .vsync_len = { 1, 1, 128 }, 3739 .flags = DISPLAY_FLAGS_DE_HIGH, 3740 }; 3741 3742 static const struct panel_desc tianma_tm070jdhg30 = { 3743 .timings = &tianma_tm070jdhg30_timing, 3744 .num_timings = 1, 3745 .bpc = 8, 3746 .size = { 3747 .width = 151, 3748 .height = 95, 3749 }, 3750 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3752 }; 3753 3754 static const struct panel_desc tianma_tm070jvhg33 = { 3755 .timings = &tianma_tm070jdhg30_timing, 3756 .num_timings = 1, 3757 .bpc = 8, 3758 .size = { 3759 .width = 150, 3760 .height = 94, 3761 }, 3762 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3763 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3764 }; 3765 3766 static const struct display_timing tianma_tm070rvhg71_timing = { 3767 .pixelclock = { 27700000, 29200000, 39600000 }, 3768 .hactive = { 800, 800, 800 }, 3769 .hfront_porch = { 12, 40, 212 }, 3770 .hback_porch = { 88, 88, 88 }, 3771 .hsync_len = { 1, 1, 40 }, 3772 .vactive = { 480, 480, 480 }, 3773 .vfront_porch = { 1, 13, 88 }, 3774 .vback_porch = { 32, 32, 32 }, 3775 .vsync_len = { 1, 1, 3 }, 3776 .flags = DISPLAY_FLAGS_DE_HIGH, 3777 }; 3778 3779 static const struct panel_desc tianma_tm070rvhg71 = { 3780 .timings = &tianma_tm070rvhg71_timing, 3781 .num_timings = 1, 3782 .bpc = 8, 3783 .size = { 3784 .width = 154, 3785 .height = 86, 3786 }, 3787 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3788 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3789 }; 3790 3791 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 3792 { 3793 .clock = 10000, 3794 .hdisplay = 320, 3795 .hsync_start = 320 + 50, 3796 .hsync_end = 320 + 50 + 6, 3797 .htotal = 320 + 50 + 6 + 38, 3798 .vdisplay = 240, 3799 .vsync_start = 240 + 3, 3800 .vsync_end = 240 + 3 + 1, 3801 .vtotal = 240 + 3 + 1 + 17, 3802 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3803 }, 3804 }; 3805 3806 static const struct panel_desc ti_nspire_cx_lcd_panel = { 3807 .modes = ti_nspire_cx_lcd_mode, 3808 .num_modes = 1, 3809 .bpc = 8, 3810 .size = { 3811 .width = 65, 3812 .height = 49, 3813 }, 3814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3815 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3816 }; 3817 3818 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 3819 { 3820 .clock = 10000, 3821 .hdisplay = 320, 3822 .hsync_start = 320 + 6, 3823 .hsync_end = 320 + 6 + 6, 3824 .htotal = 320 + 6 + 6 + 6, 3825 .vdisplay = 240, 3826 .vsync_start = 240 + 0, 3827 .vsync_end = 240 + 0 + 1, 3828 .vtotal = 240 + 0 + 1 + 0, 3829 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3830 }, 3831 }; 3832 3833 static const struct panel_desc ti_nspire_classic_lcd_panel = { 3834 .modes = ti_nspire_classic_lcd_mode, 3835 .num_modes = 1, 3836 /* The grayscale panel has 8 bit for the color .. Y (black) */ 3837 .bpc = 8, 3838 .size = { 3839 .width = 71, 3840 .height = 53, 3841 }, 3842 /* This is the grayscale bus format */ 3843 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 3844 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3845 }; 3846 3847 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 3848 .clock = 79500, 3849 .hdisplay = 1280, 3850 .hsync_start = 1280 + 192, 3851 .hsync_end = 1280 + 192 + 128, 3852 .htotal = 1280 + 192 + 128 + 64, 3853 .vdisplay = 768, 3854 .vsync_start = 768 + 20, 3855 .vsync_end = 768 + 20 + 7, 3856 .vtotal = 768 + 20 + 7 + 3, 3857 }; 3858 3859 static const struct panel_desc toshiba_lt089ac29000 = { 3860 .modes = &toshiba_lt089ac29000_mode, 3861 .num_modes = 1, 3862 .size = { 3863 .width = 194, 3864 .height = 116, 3865 }, 3866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3867 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3868 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3869 }; 3870 3871 static const struct drm_display_mode tpk_f07a_0102_mode = { 3872 .clock = 33260, 3873 .hdisplay = 800, 3874 .hsync_start = 800 + 40, 3875 .hsync_end = 800 + 40 + 128, 3876 .htotal = 800 + 40 + 128 + 88, 3877 .vdisplay = 480, 3878 .vsync_start = 480 + 10, 3879 .vsync_end = 480 + 10 + 2, 3880 .vtotal = 480 + 10 + 2 + 33, 3881 }; 3882 3883 static const struct panel_desc tpk_f07a_0102 = { 3884 .modes = &tpk_f07a_0102_mode, 3885 .num_modes = 1, 3886 .size = { 3887 .width = 152, 3888 .height = 91, 3889 }, 3890 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3891 }; 3892 3893 static const struct drm_display_mode tpk_f10a_0102_mode = { 3894 .clock = 45000, 3895 .hdisplay = 1024, 3896 .hsync_start = 1024 + 176, 3897 .hsync_end = 1024 + 176 + 5, 3898 .htotal = 1024 + 176 + 5 + 88, 3899 .vdisplay = 600, 3900 .vsync_start = 600 + 20, 3901 .vsync_end = 600 + 20 + 5, 3902 .vtotal = 600 + 20 + 5 + 25, 3903 }; 3904 3905 static const struct panel_desc tpk_f10a_0102 = { 3906 .modes = &tpk_f10a_0102_mode, 3907 .num_modes = 1, 3908 .size = { 3909 .width = 223, 3910 .height = 125, 3911 }, 3912 }; 3913 3914 static const struct display_timing urt_umsh_8596md_timing = { 3915 .pixelclock = { 33260000, 33260000, 33260000 }, 3916 .hactive = { 800, 800, 800 }, 3917 .hfront_porch = { 41, 41, 41 }, 3918 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 3919 .hsync_len = { 71, 128, 128 }, 3920 .vactive = { 480, 480, 480 }, 3921 .vfront_porch = { 10, 10, 10 }, 3922 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 3923 .vsync_len = { 2, 2, 2 }, 3924 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 3925 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3926 }; 3927 3928 static const struct panel_desc urt_umsh_8596md_lvds = { 3929 .timings = &urt_umsh_8596md_timing, 3930 .num_timings = 1, 3931 .bpc = 6, 3932 .size = { 3933 .width = 152, 3934 .height = 91, 3935 }, 3936 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3937 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3938 }; 3939 3940 static const struct panel_desc urt_umsh_8596md_parallel = { 3941 .timings = &urt_umsh_8596md_timing, 3942 .num_timings = 1, 3943 .bpc = 6, 3944 .size = { 3945 .width = 152, 3946 .height = 91, 3947 }, 3948 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3949 }; 3950 3951 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 3952 .clock = 60000, 3953 .hdisplay = 1024, 3954 .hsync_start = 1024 + 160, 3955 .hsync_end = 1024 + 160 + 100, 3956 .htotal = 1024 + 160 + 100 + 60, 3957 .vdisplay = 600, 3958 .vsync_start = 600 + 12, 3959 .vsync_end = 600 + 12 + 10, 3960 .vtotal = 600 + 12 + 10 + 13, 3961 }; 3962 3963 static const struct panel_desc vivax_tpc9150_panel = { 3964 .modes = &vivax_tpc9150_panel_mode, 3965 .num_modes = 1, 3966 .bpc = 6, 3967 .size = { 3968 .width = 200, 3969 .height = 115, 3970 }, 3971 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3972 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3973 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3974 }; 3975 3976 static const struct drm_display_mode vl050_8048nt_c01_mode = { 3977 .clock = 33333, 3978 .hdisplay = 800, 3979 .hsync_start = 800 + 210, 3980 .hsync_end = 800 + 210 + 20, 3981 .htotal = 800 + 210 + 20 + 46, 3982 .vdisplay = 480, 3983 .vsync_start = 480 + 22, 3984 .vsync_end = 480 + 22 + 10, 3985 .vtotal = 480 + 22 + 10 + 23, 3986 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3987 }; 3988 3989 static const struct panel_desc vl050_8048nt_c01 = { 3990 .modes = &vl050_8048nt_c01_mode, 3991 .num_modes = 1, 3992 .bpc = 8, 3993 .size = { 3994 .width = 120, 3995 .height = 76, 3996 }, 3997 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3998 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3999 }; 4000 4001 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4002 .clock = 6410, 4003 .hdisplay = 320, 4004 .hsync_start = 320 + 20, 4005 .hsync_end = 320 + 20 + 30, 4006 .htotal = 320 + 20 + 30 + 38, 4007 .vdisplay = 240, 4008 .vsync_start = 240 + 4, 4009 .vsync_end = 240 + 4 + 3, 4010 .vtotal = 240 + 4 + 3 + 15, 4011 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4012 }; 4013 4014 static const struct panel_desc winstar_wf35ltiacd = { 4015 .modes = &winstar_wf35ltiacd_mode, 4016 .num_modes = 1, 4017 .bpc = 8, 4018 .size = { 4019 .width = 70, 4020 .height = 53, 4021 }, 4022 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4023 }; 4024 4025 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4026 .clock = 51200, 4027 .hdisplay = 1024, 4028 .hsync_start = 1024 + 100, 4029 .hsync_end = 1024 + 100 + 100, 4030 .htotal = 1024 + 100 + 100 + 120, 4031 .vdisplay = 600, 4032 .vsync_start = 600 + 10, 4033 .vsync_end = 600 + 10 + 10, 4034 .vtotal = 600 + 10 + 10 + 15, 4035 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4036 }; 4037 4038 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4039 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4040 .num_modes = 1, 4041 .bpc = 8, 4042 .size = { 4043 .width = 154, 4044 .height = 90, 4045 }, 4046 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4047 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4048 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4049 }; 4050 4051 static const struct drm_display_mode arm_rtsm_mode[] = { 4052 { 4053 .clock = 65000, 4054 .hdisplay = 1024, 4055 .hsync_start = 1024 + 24, 4056 .hsync_end = 1024 + 24 + 136, 4057 .htotal = 1024 + 24 + 136 + 160, 4058 .vdisplay = 768, 4059 .vsync_start = 768 + 3, 4060 .vsync_end = 768 + 3 + 6, 4061 .vtotal = 768 + 3 + 6 + 29, 4062 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4063 }, 4064 }; 4065 4066 static const struct panel_desc arm_rtsm = { 4067 .modes = arm_rtsm_mode, 4068 .num_modes = 1, 4069 .bpc = 8, 4070 .size = { 4071 .width = 400, 4072 .height = 300, 4073 }, 4074 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4075 }; 4076 4077 static const struct of_device_id platform_of_match[] = { 4078 { 4079 .compatible = "ampire,am-1280800n3tzqw-t00h", 4080 .data = &ire_am_1280800n3tzqw_t00h, 4081 }, { 4082 .compatible = "ampire,am-480272h3tmqw-t01h", 4083 .data = &ire_am_480272h3tmqw_t01h, 4084 }, { 4085 .compatible = "ampire,am-800480l1tmqw-t00h", 4086 .data = &ire_am_800480l1tmqw_t00h, 4087 }, { 4088 .compatible = "ampire,am800480r3tmqwa1h", 4089 .data = &ire_am800480r3tmqwa1h, 4090 }, { 4091 .compatible = "ampire,am800600p5tmqw-tb8h", 4092 .data = &ire_am800600p5tmqwtb8h, 4093 }, { 4094 .compatible = "arm,rtsm-display", 4095 .data = &arm_rtsm, 4096 }, { 4097 .compatible = "armadeus,st0700-adapt", 4098 .data = &armadeus_st0700_adapt, 4099 }, { 4100 .compatible = "auo,b101aw03", 4101 .data = &auo_b101aw03, 4102 }, { 4103 .compatible = "auo,b101xtn01", 4104 .data = &auo_b101xtn01, 4105 }, { 4106 .compatible = "auo,g070vvn01", 4107 .data = &auo_g070vvn01, 4108 }, { 4109 .compatible = "auo,g101evn010", 4110 .data = &auo_g101evn010, 4111 }, { 4112 .compatible = "auo,g104sn02", 4113 .data = &auo_g104sn02, 4114 }, { 4115 .compatible = "auo,g121ean01", 4116 .data = &auo_g121ean01, 4117 }, { 4118 .compatible = "auo,g133han01", 4119 .data = &auo_g133han01, 4120 }, { 4121 .compatible = "auo,g156xtn01", 4122 .data = &auo_g156xtn01, 4123 }, { 4124 .compatible = "auo,g185han01", 4125 .data = &auo_g185han01, 4126 }, { 4127 .compatible = "auo,g190ean01", 4128 .data = &auo_g190ean01, 4129 }, { 4130 .compatible = "auo,p320hvn03", 4131 .data = &auo_p320hvn03, 4132 }, { 4133 .compatible = "auo,t215hvn01", 4134 .data = &auo_t215hvn01, 4135 }, { 4136 .compatible = "avic,tm070ddh03", 4137 .data = &avic_tm070ddh03, 4138 }, { 4139 .compatible = "bananapi,s070wv20-ct16", 4140 .data = &bananapi_s070wv20_ct16, 4141 }, { 4142 .compatible = "boe,ev121wxm-n10-1850", 4143 .data = &boe_ev121wxm_n10_1850, 4144 }, { 4145 .compatible = "boe,hv070wsa-100", 4146 .data = &boe_hv070wsa 4147 }, { 4148 .compatible = "cdtech,s043wq26h-ct7", 4149 .data = &cdtech_s043wq26h_ct7, 4150 }, { 4151 .compatible = "cdtech,s070pws19hp-fc21", 4152 .data = &cdtech_s070pws19hp_fc21, 4153 }, { 4154 .compatible = "cdtech,s070swv29hg-dc44", 4155 .data = &cdtech_s070swv29hg_dc44, 4156 }, { 4157 .compatible = "cdtech,s070wv95-ct16", 4158 .data = &cdtech_s070wv95_ct16, 4159 }, { 4160 .compatible = "chefree,ch101olhlwh-002", 4161 .data = &chefree_ch101olhlwh_002, 4162 }, { 4163 .compatible = "chunghwa,claa070wp03xg", 4164 .data = &chunghwa_claa070wp03xg, 4165 }, { 4166 .compatible = "chunghwa,claa101wa01a", 4167 .data = &chunghwa_claa101wa01a 4168 }, { 4169 .compatible = "chunghwa,claa101wb01", 4170 .data = &chunghwa_claa101wb01 4171 }, { 4172 .compatible = "dataimage,fg040346dsswbg04", 4173 .data = &dataimage_fg040346dsswbg04, 4174 }, { 4175 .compatible = "dataimage,fg1001l0dsswmg01", 4176 .data = &dataimage_fg1001l0dsswmg01, 4177 }, { 4178 .compatible = "dataimage,scf0700c48ggu18", 4179 .data = &dataimage_scf0700c48ggu18, 4180 }, { 4181 .compatible = "dlc,dlc0700yzg-1", 4182 .data = &dlc_dlc0700yzg_1, 4183 }, { 4184 .compatible = "dlc,dlc1010gig", 4185 .data = &dlc_dlc1010gig, 4186 }, { 4187 .compatible = "edt,et035012dm6", 4188 .data = &edt_et035012dm6, 4189 }, { 4190 .compatible = "edt,etm0350g0dh6", 4191 .data = &edt_etm0350g0dh6, 4192 }, { 4193 .compatible = "edt,etm043080dh6gp", 4194 .data = &edt_etm043080dh6gp, 4195 }, { 4196 .compatible = "edt,etm0430g0dh6", 4197 .data = &edt_etm0430g0dh6, 4198 }, { 4199 .compatible = "edt,et057090dhu", 4200 .data = &edt_et057090dhu, 4201 }, { 4202 .compatible = "edt,et070080dh6", 4203 .data = &edt_etm0700g0dh6, 4204 }, { 4205 .compatible = "edt,etm0700g0dh6", 4206 .data = &edt_etm0700g0dh6, 4207 }, { 4208 .compatible = "edt,etm0700g0bdh6", 4209 .data = &edt_etm0700g0bdh6, 4210 }, { 4211 .compatible = "edt,etm0700g0edh6", 4212 .data = &edt_etm0700g0bdh6, 4213 }, { 4214 .compatible = "edt,etml0700y5dha", 4215 .data = &edt_etml0700y5dha, 4216 }, { 4217 .compatible = "edt,etmv570g2dhu", 4218 .data = &edt_etmv570g2dhu, 4219 }, { 4220 .compatible = "eink,vb3300-kca", 4221 .data = &eink_vb3300_kca, 4222 }, { 4223 .compatible = "evervision,vgg804821", 4224 .data = &evervision_vgg804821, 4225 }, { 4226 .compatible = "foxlink,fl500wvr00-a0t", 4227 .data = &foxlink_fl500wvr00_a0t, 4228 }, { 4229 .compatible = "frida,frd350h54004", 4230 .data = &frida_frd350h54004, 4231 }, { 4232 .compatible = "friendlyarm,hd702e", 4233 .data = &friendlyarm_hd702e, 4234 }, { 4235 .compatible = "giantplus,gpg482739qs5", 4236 .data = &giantplus_gpg482739qs5 4237 }, { 4238 .compatible = "giantplus,gpm940b0", 4239 .data = &giantplus_gpm940b0, 4240 }, { 4241 .compatible = "hannstar,hsd070pww1", 4242 .data = &hannstar_hsd070pww1, 4243 }, { 4244 .compatible = "hannstar,hsd100pxn1", 4245 .data = &hannstar_hsd100pxn1, 4246 }, { 4247 .compatible = "hannstar,hsd101pww2", 4248 .data = &hannstar_hsd101pww2, 4249 }, { 4250 .compatible = "hit,tx23d38vm0caa", 4251 .data = &hitachi_tx23d38vm0caa 4252 }, { 4253 .compatible = "innolux,at043tn24", 4254 .data = &innolux_at043tn24, 4255 }, { 4256 .compatible = "innolux,at070tn92", 4257 .data = &innolux_at070tn92, 4258 }, { 4259 .compatible = "innolux,g070ace-l01", 4260 .data = &innolux_g070ace_l01, 4261 }, { 4262 .compatible = "innolux,g070y2-l01", 4263 .data = &innolux_g070y2_l01, 4264 }, { 4265 .compatible = "innolux,g070y2-t02", 4266 .data = &innolux_g070y2_t02, 4267 }, { 4268 .compatible = "innolux,g101ice-l01", 4269 .data = &innolux_g101ice_l01 4270 }, { 4271 .compatible = "innolux,g121i1-l01", 4272 .data = &innolux_g121i1_l01 4273 }, { 4274 .compatible = "innolux,g121x1-l03", 4275 .data = &innolux_g121x1_l03, 4276 }, { 4277 .compatible = "innolux,g156hce-l01", 4278 .data = &innolux_g156hce_l01, 4279 }, { 4280 .compatible = "innolux,n156bge-l21", 4281 .data = &innolux_n156bge_l21, 4282 }, { 4283 .compatible = "innolux,zj070na-01p", 4284 .data = &innolux_zj070na_01p, 4285 }, { 4286 .compatible = "koe,tx14d24vm1bpa", 4287 .data = &koe_tx14d24vm1bpa, 4288 }, { 4289 .compatible = "koe,tx26d202vm0bwa", 4290 .data = &koe_tx26d202vm0bwa, 4291 }, { 4292 .compatible = "koe,tx31d200vm0baa", 4293 .data = &koe_tx31d200vm0baa, 4294 }, { 4295 .compatible = "kyo,tcg121xglp", 4296 .data = &kyo_tcg121xglp, 4297 }, { 4298 .compatible = "lemaker,bl035-rgb-002", 4299 .data = &lemaker_bl035_rgb_002, 4300 }, { 4301 .compatible = "lg,lb070wv8", 4302 .data = &lg_lb070wv8, 4303 }, { 4304 .compatible = "logicpd,type28", 4305 .data = &logicpd_type_28, 4306 }, { 4307 .compatible = "logictechno,lt161010-2nhc", 4308 .data = &logictechno_lt161010_2nh, 4309 }, { 4310 .compatible = "logictechno,lt161010-2nhr", 4311 .data = &logictechno_lt161010_2nh, 4312 }, { 4313 .compatible = "logictechno,lt170410-2whc", 4314 .data = &logictechno_lt170410_2whc, 4315 }, { 4316 .compatible = "logictechno,lttd800480070-l2rt", 4317 .data = &logictechno_lttd800480070_l2rt, 4318 }, { 4319 .compatible = "logictechno,lttd800480070-l6wh-rt", 4320 .data = &logictechno_lttd800480070_l6wh_rt, 4321 }, { 4322 .compatible = "mitsubishi,aa070mc01-ca1", 4323 .data = &mitsubishi_aa070mc01, 4324 }, { 4325 .compatible = "multi-inno,mi0700s4t-6", 4326 .data = &multi_inno_mi0700s4t_6, 4327 }, { 4328 .compatible = "multi-inno,mi0800ft-9", 4329 .data = &multi_inno_mi0800ft_9, 4330 }, { 4331 .compatible = "multi-inno,mi1010ait-1cp", 4332 .data = &multi_inno_mi1010ait_1cp, 4333 }, { 4334 .compatible = "nec,nl12880bc20-05", 4335 .data = &nec_nl12880bc20_05, 4336 }, { 4337 .compatible = "nec,nl4827hc19-05b", 4338 .data = &nec_nl4827hc19_05b, 4339 }, { 4340 .compatible = "netron-dy,e231732", 4341 .data = &netron_dy_e231732, 4342 }, { 4343 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4344 .data = &newhaven_nhd_43_480272ef_atxl, 4345 }, { 4346 .compatible = "nlt,nl192108ac18-02d", 4347 .data = &nlt_nl192108ac18_02d, 4348 }, { 4349 .compatible = "nvd,9128", 4350 .data = &nvd_9128, 4351 }, { 4352 .compatible = "okaya,rs800480t-7x0gp", 4353 .data = &okaya_rs800480t_7x0gp, 4354 }, { 4355 .compatible = "olimex,lcd-olinuxino-43-ts", 4356 .data = &olimex_lcd_olinuxino_43ts, 4357 }, { 4358 .compatible = "ontat,yx700wv03", 4359 .data = &ontat_yx700wv03, 4360 }, { 4361 .compatible = "ortustech,com37h3m05dtc", 4362 .data = &ortustech_com37h3m, 4363 }, { 4364 .compatible = "ortustech,com37h3m99dtc", 4365 .data = &ortustech_com37h3m, 4366 }, { 4367 .compatible = "ortustech,com43h4m85ulc", 4368 .data = &ortustech_com43h4m85ulc, 4369 }, { 4370 .compatible = "osddisplays,osd070t1718-19ts", 4371 .data = &osddisplays_osd070t1718_19ts, 4372 }, { 4373 .compatible = "pda,91-00156-a0", 4374 .data = &pda_91_00156_a0, 4375 }, { 4376 .compatible = "powertip,ph800480t013-idf02", 4377 .data = &powertip_ph800480t013_idf02, 4378 }, { 4379 .compatible = "qiaodian,qd43003c0-40", 4380 .data = &qd43003c0_40, 4381 }, { 4382 .compatible = "qishenglong,gopher2b-lcd", 4383 .data = &qishenglong_gopher2b_lcd, 4384 }, { 4385 .compatible = "rocktech,rk043fn48h", 4386 .data = &rocktech_rk043fn48h, 4387 }, { 4388 .compatible = "rocktech,rk070er9427", 4389 .data = &rocktech_rk070er9427, 4390 }, { 4391 .compatible = "rocktech,rk101ii01d-ct", 4392 .data = &rocktech_rk101ii01d_ct, 4393 }, { 4394 .compatible = "samsung,ltl101al01", 4395 .data = &samsung_ltl101al01, 4396 }, { 4397 .compatible = "samsung,ltn101nt05", 4398 .data = &samsung_ltn101nt05, 4399 }, { 4400 .compatible = "satoz,sat050at40h12r2", 4401 .data = &satoz_sat050at40h12r2, 4402 }, { 4403 .compatible = "sharp,lq035q7db03", 4404 .data = &sharp_lq035q7db03, 4405 }, { 4406 .compatible = "sharp,lq070y3dg3b", 4407 .data = &sharp_lq070y3dg3b, 4408 }, { 4409 .compatible = "sharp,lq101k1ly04", 4410 .data = &sharp_lq101k1ly04, 4411 }, { 4412 .compatible = "sharp,ls020b1dd01d", 4413 .data = &sharp_ls020b1dd01d, 4414 }, { 4415 .compatible = "shelly,sca07010-bfn-lnn", 4416 .data = &shelly_sca07010_bfn_lnn, 4417 }, { 4418 .compatible = "starry,kr070pe2t", 4419 .data = &starry_kr070pe2t, 4420 }, { 4421 .compatible = "startek,kd070wvfpa", 4422 .data = &startek_kd070wvfpa, 4423 }, { 4424 .compatible = "team-source-display,tst043015cmhx", 4425 .data = &tsd_tst043015cmhx, 4426 }, { 4427 .compatible = "tfc,s9700rtwv43tr-01b", 4428 .data = &tfc_s9700rtwv43tr_01b, 4429 }, { 4430 .compatible = "tianma,tm070jdhg30", 4431 .data = &tianma_tm070jdhg30, 4432 }, { 4433 .compatible = "tianma,tm070jvhg33", 4434 .data = &tianma_tm070jvhg33, 4435 }, { 4436 .compatible = "tianma,tm070rvhg71", 4437 .data = &tianma_tm070rvhg71, 4438 }, { 4439 .compatible = "ti,nspire-cx-lcd-panel", 4440 .data = &ti_nspire_cx_lcd_panel, 4441 }, { 4442 .compatible = "ti,nspire-classic-lcd-panel", 4443 .data = &ti_nspire_classic_lcd_panel, 4444 }, { 4445 .compatible = "toshiba,lt089ac29000", 4446 .data = &toshiba_lt089ac29000, 4447 }, { 4448 .compatible = "tpk,f07a-0102", 4449 .data = &tpk_f07a_0102, 4450 }, { 4451 .compatible = "tpk,f10a-0102", 4452 .data = &tpk_f10a_0102, 4453 }, { 4454 .compatible = "urt,umsh-8596md-t", 4455 .data = &urt_umsh_8596md_parallel, 4456 }, { 4457 .compatible = "urt,umsh-8596md-1t", 4458 .data = &urt_umsh_8596md_parallel, 4459 }, { 4460 .compatible = "urt,umsh-8596md-7t", 4461 .data = &urt_umsh_8596md_parallel, 4462 }, { 4463 .compatible = "urt,umsh-8596md-11t", 4464 .data = &urt_umsh_8596md_lvds, 4465 }, { 4466 .compatible = "urt,umsh-8596md-19t", 4467 .data = &urt_umsh_8596md_lvds, 4468 }, { 4469 .compatible = "urt,umsh-8596md-20t", 4470 .data = &urt_umsh_8596md_parallel, 4471 }, { 4472 .compatible = "vivax,tpc9150-panel", 4473 .data = &vivax_tpc9150_panel, 4474 }, { 4475 .compatible = "vxt,vl050-8048nt-c01", 4476 .data = &vl050_8048nt_c01, 4477 }, { 4478 .compatible = "winstar,wf35ltiacd", 4479 .data = &winstar_wf35ltiacd, 4480 }, { 4481 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4482 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4483 }, { 4484 /* Must be the last entry */ 4485 .compatible = "panel-dpi", 4486 .data = &panel_dpi, 4487 }, { 4488 /* sentinel */ 4489 } 4490 }; 4491 MODULE_DEVICE_TABLE(of, platform_of_match); 4492 4493 static int panel_simple_platform_probe(struct platform_device *pdev) 4494 { 4495 const struct panel_desc *desc; 4496 4497 desc = of_device_get_match_data(&pdev->dev); 4498 if (!desc) 4499 return -ENODEV; 4500 4501 return panel_simple_probe(&pdev->dev, desc); 4502 } 4503 4504 static void panel_simple_platform_remove(struct platform_device *pdev) 4505 { 4506 panel_simple_remove(&pdev->dev); 4507 } 4508 4509 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4510 { 4511 panel_simple_shutdown(&pdev->dev); 4512 } 4513 4514 static const struct dev_pm_ops panel_simple_pm_ops = { 4515 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4516 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4517 pm_runtime_force_resume) 4518 }; 4519 4520 static struct platform_driver panel_simple_platform_driver = { 4521 .driver = { 4522 .name = "panel-simple", 4523 .of_match_table = platform_of_match, 4524 .pm = &panel_simple_pm_ops, 4525 }, 4526 .probe = panel_simple_platform_probe, 4527 .remove_new = panel_simple_platform_remove, 4528 .shutdown = panel_simple_platform_shutdown, 4529 }; 4530 4531 struct panel_desc_dsi { 4532 struct panel_desc desc; 4533 4534 unsigned long flags; 4535 enum mipi_dsi_pixel_format format; 4536 unsigned int lanes; 4537 }; 4538 4539 static const struct drm_display_mode auo_b080uan01_mode = { 4540 .clock = 154500, 4541 .hdisplay = 1200, 4542 .hsync_start = 1200 + 62, 4543 .hsync_end = 1200 + 62 + 4, 4544 .htotal = 1200 + 62 + 4 + 62, 4545 .vdisplay = 1920, 4546 .vsync_start = 1920 + 9, 4547 .vsync_end = 1920 + 9 + 2, 4548 .vtotal = 1920 + 9 + 2 + 8, 4549 }; 4550 4551 static const struct panel_desc_dsi auo_b080uan01 = { 4552 .desc = { 4553 .modes = &auo_b080uan01_mode, 4554 .num_modes = 1, 4555 .bpc = 8, 4556 .size = { 4557 .width = 108, 4558 .height = 272, 4559 }, 4560 .connector_type = DRM_MODE_CONNECTOR_DSI, 4561 }, 4562 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4563 .format = MIPI_DSI_FMT_RGB888, 4564 .lanes = 4, 4565 }; 4566 4567 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4568 .clock = 160000, 4569 .hdisplay = 1200, 4570 .hsync_start = 1200 + 120, 4571 .hsync_end = 1200 + 120 + 20, 4572 .htotal = 1200 + 120 + 20 + 21, 4573 .vdisplay = 1920, 4574 .vsync_start = 1920 + 21, 4575 .vsync_end = 1920 + 21 + 3, 4576 .vtotal = 1920 + 21 + 3 + 18, 4577 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4578 }; 4579 4580 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4581 .desc = { 4582 .modes = &boe_tv080wum_nl0_mode, 4583 .num_modes = 1, 4584 .size = { 4585 .width = 107, 4586 .height = 172, 4587 }, 4588 .connector_type = DRM_MODE_CONNECTOR_DSI, 4589 }, 4590 .flags = MIPI_DSI_MODE_VIDEO | 4591 MIPI_DSI_MODE_VIDEO_BURST | 4592 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4593 .format = MIPI_DSI_FMT_RGB888, 4594 .lanes = 4, 4595 }; 4596 4597 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4598 .clock = 71000, 4599 .hdisplay = 800, 4600 .hsync_start = 800 + 32, 4601 .hsync_end = 800 + 32 + 1, 4602 .htotal = 800 + 32 + 1 + 57, 4603 .vdisplay = 1280, 4604 .vsync_start = 1280 + 28, 4605 .vsync_end = 1280 + 28 + 1, 4606 .vtotal = 1280 + 28 + 1 + 14, 4607 }; 4608 4609 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4610 .desc = { 4611 .modes = &lg_ld070wx3_sl01_mode, 4612 .num_modes = 1, 4613 .bpc = 8, 4614 .size = { 4615 .width = 94, 4616 .height = 151, 4617 }, 4618 .connector_type = DRM_MODE_CONNECTOR_DSI, 4619 }, 4620 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4621 .format = MIPI_DSI_FMT_RGB888, 4622 .lanes = 4, 4623 }; 4624 4625 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4626 .clock = 67000, 4627 .hdisplay = 720, 4628 .hsync_start = 720 + 12, 4629 .hsync_end = 720 + 12 + 4, 4630 .htotal = 720 + 12 + 4 + 112, 4631 .vdisplay = 1280, 4632 .vsync_start = 1280 + 8, 4633 .vsync_end = 1280 + 8 + 4, 4634 .vtotal = 1280 + 8 + 4 + 12, 4635 }; 4636 4637 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4638 .desc = { 4639 .modes = &lg_lh500wx1_sd03_mode, 4640 .num_modes = 1, 4641 .bpc = 8, 4642 .size = { 4643 .width = 62, 4644 .height = 110, 4645 }, 4646 .connector_type = DRM_MODE_CONNECTOR_DSI, 4647 }, 4648 .flags = MIPI_DSI_MODE_VIDEO, 4649 .format = MIPI_DSI_FMT_RGB888, 4650 .lanes = 4, 4651 }; 4652 4653 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4654 .clock = 157200, 4655 .hdisplay = 1920, 4656 .hsync_start = 1920 + 154, 4657 .hsync_end = 1920 + 154 + 16, 4658 .htotal = 1920 + 154 + 16 + 32, 4659 .vdisplay = 1200, 4660 .vsync_start = 1200 + 17, 4661 .vsync_end = 1200 + 17 + 2, 4662 .vtotal = 1200 + 17 + 2 + 16, 4663 }; 4664 4665 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4666 .desc = { 4667 .modes = &panasonic_vvx10f004b00_mode, 4668 .num_modes = 1, 4669 .bpc = 8, 4670 .size = { 4671 .width = 217, 4672 .height = 136, 4673 }, 4674 .connector_type = DRM_MODE_CONNECTOR_DSI, 4675 }, 4676 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4677 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4678 .format = MIPI_DSI_FMT_RGB888, 4679 .lanes = 4, 4680 }; 4681 4682 static const struct drm_display_mode lg_acx467akm_7_mode = { 4683 .clock = 150000, 4684 .hdisplay = 1080, 4685 .hsync_start = 1080 + 2, 4686 .hsync_end = 1080 + 2 + 2, 4687 .htotal = 1080 + 2 + 2 + 2, 4688 .vdisplay = 1920, 4689 .vsync_start = 1920 + 2, 4690 .vsync_end = 1920 + 2 + 2, 4691 .vtotal = 1920 + 2 + 2 + 2, 4692 }; 4693 4694 static const struct panel_desc_dsi lg_acx467akm_7 = { 4695 .desc = { 4696 .modes = &lg_acx467akm_7_mode, 4697 .num_modes = 1, 4698 .bpc = 8, 4699 .size = { 4700 .width = 62, 4701 .height = 110, 4702 }, 4703 .connector_type = DRM_MODE_CONNECTOR_DSI, 4704 }, 4705 .flags = 0, 4706 .format = MIPI_DSI_FMT_RGB888, 4707 .lanes = 4, 4708 }; 4709 4710 static const struct drm_display_mode osd101t2045_53ts_mode = { 4711 .clock = 154500, 4712 .hdisplay = 1920, 4713 .hsync_start = 1920 + 112, 4714 .hsync_end = 1920 + 112 + 16, 4715 .htotal = 1920 + 112 + 16 + 32, 4716 .vdisplay = 1200, 4717 .vsync_start = 1200 + 16, 4718 .vsync_end = 1200 + 16 + 2, 4719 .vtotal = 1200 + 16 + 2 + 16, 4720 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4721 }; 4722 4723 static const struct panel_desc_dsi osd101t2045_53ts = { 4724 .desc = { 4725 .modes = &osd101t2045_53ts_mode, 4726 .num_modes = 1, 4727 .bpc = 8, 4728 .size = { 4729 .width = 217, 4730 .height = 136, 4731 }, 4732 .connector_type = DRM_MODE_CONNECTOR_DSI, 4733 }, 4734 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4735 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4736 MIPI_DSI_MODE_NO_EOT_PACKET, 4737 .format = MIPI_DSI_FMT_RGB888, 4738 .lanes = 4, 4739 }; 4740 4741 static const struct of_device_id dsi_of_match[] = { 4742 { 4743 .compatible = "auo,b080uan01", 4744 .data = &auo_b080uan01 4745 }, { 4746 .compatible = "boe,tv080wum-nl0", 4747 .data = &boe_tv080wum_nl0 4748 }, { 4749 .compatible = "lg,ld070wx3-sl01", 4750 .data = &lg_ld070wx3_sl01 4751 }, { 4752 .compatible = "lg,lh500wx1-sd03", 4753 .data = &lg_lh500wx1_sd03 4754 }, { 4755 .compatible = "panasonic,vvx10f004b00", 4756 .data = &panasonic_vvx10f004b00 4757 }, { 4758 .compatible = "lg,acx467akm-7", 4759 .data = &lg_acx467akm_7 4760 }, { 4761 .compatible = "osddisplays,osd101t2045-53ts", 4762 .data = &osd101t2045_53ts 4763 }, { 4764 /* sentinel */ 4765 } 4766 }; 4767 MODULE_DEVICE_TABLE(of, dsi_of_match); 4768 4769 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 4770 { 4771 const struct panel_desc_dsi *desc; 4772 int err; 4773 4774 desc = of_device_get_match_data(&dsi->dev); 4775 if (!desc) 4776 return -ENODEV; 4777 4778 err = panel_simple_probe(&dsi->dev, &desc->desc); 4779 if (err < 0) 4780 return err; 4781 4782 dsi->mode_flags = desc->flags; 4783 dsi->format = desc->format; 4784 dsi->lanes = desc->lanes; 4785 4786 err = mipi_dsi_attach(dsi); 4787 if (err) { 4788 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 4789 4790 drm_panel_remove(&panel->base); 4791 } 4792 4793 return err; 4794 } 4795 4796 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 4797 { 4798 int err; 4799 4800 err = mipi_dsi_detach(dsi); 4801 if (err < 0) 4802 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 4803 4804 panel_simple_remove(&dsi->dev); 4805 } 4806 4807 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 4808 { 4809 panel_simple_shutdown(&dsi->dev); 4810 } 4811 4812 static struct mipi_dsi_driver panel_simple_dsi_driver = { 4813 .driver = { 4814 .name = "panel-simple-dsi", 4815 .of_match_table = dsi_of_match, 4816 .pm = &panel_simple_pm_ops, 4817 }, 4818 .probe = panel_simple_dsi_probe, 4819 .remove = panel_simple_dsi_remove, 4820 .shutdown = panel_simple_dsi_shutdown, 4821 }; 4822 4823 static int __init panel_simple_init(void) 4824 { 4825 int err; 4826 4827 err = platform_driver_register(&panel_simple_platform_driver); 4828 if (err < 0) 4829 return err; 4830 4831 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 4832 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 4833 if (err < 0) 4834 goto err_did_platform_register; 4835 } 4836 4837 return 0; 4838 4839 err_did_platform_register: 4840 platform_driver_unregister(&panel_simple_platform_driver); 4841 4842 return err; 4843 } 4844 module_init(panel_simple_init); 4845 4846 static void __exit panel_simple_exit(void) 4847 { 4848 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 4849 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 4850 4851 platform_driver_unregister(&panel_simple_platform_driver); 4852 } 4853 module_exit(panel_simple_exit); 4854 4855 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 4856 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 4857 MODULE_LICENSE("GPL and additional rights"); 4858