1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 bool enabled; 142 143 bool prepared; 144 145 ktime_t unprepared_time; 146 147 const struct panel_desc *desc; 148 149 struct regulator *supply; 150 struct i2c_adapter *ddc; 151 152 struct gpio_desc *enable_gpio; 153 154 struct edid *edid; 155 156 struct drm_display_mode override_mode; 157 158 enum drm_panel_orientation orientation; 159 }; 160 161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 162 { 163 return container_of(panel, struct panel_simple, base); 164 } 165 166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 167 struct drm_connector *connector) 168 { 169 struct drm_display_mode *mode; 170 unsigned int i, num = 0; 171 172 for (i = 0; i < panel->desc->num_timings; i++) { 173 const struct display_timing *dt = &panel->desc->timings[i]; 174 struct videomode vm; 175 176 videomode_from_timing(dt, &vm); 177 mode = drm_mode_create(connector->dev); 178 if (!mode) { 179 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 180 dt->hactive.typ, dt->vactive.typ); 181 continue; 182 } 183 184 drm_display_mode_from_videomode(&vm, mode); 185 186 mode->type |= DRM_MODE_TYPE_DRIVER; 187 188 if (panel->desc->num_timings == 1) 189 mode->type |= DRM_MODE_TYPE_PREFERRED; 190 191 drm_mode_probed_add(connector, mode); 192 num++; 193 } 194 195 return num; 196 } 197 198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 199 struct drm_connector *connector) 200 { 201 struct drm_display_mode *mode; 202 unsigned int i, num = 0; 203 204 for (i = 0; i < panel->desc->num_modes; i++) { 205 const struct drm_display_mode *m = &panel->desc->modes[i]; 206 207 mode = drm_mode_duplicate(connector->dev, m); 208 if (!mode) { 209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 210 m->hdisplay, m->vdisplay, 211 drm_mode_vrefresh(m)); 212 continue; 213 } 214 215 mode->type |= DRM_MODE_TYPE_DRIVER; 216 217 if (panel->desc->num_modes == 1) 218 mode->type |= DRM_MODE_TYPE_PREFERRED; 219 220 drm_mode_set_name(mode); 221 222 drm_mode_probed_add(connector, mode); 223 num++; 224 } 225 226 return num; 227 } 228 229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 230 struct drm_connector *connector) 231 { 232 struct drm_display_mode *mode; 233 bool has_override = panel->override_mode.type; 234 unsigned int num = 0; 235 236 if (!panel->desc) 237 return 0; 238 239 if (has_override) { 240 mode = drm_mode_duplicate(connector->dev, 241 &panel->override_mode); 242 if (mode) { 243 drm_mode_probed_add(connector, mode); 244 num = 1; 245 } else { 246 dev_err(panel->base.dev, "failed to add override mode\n"); 247 } 248 } 249 250 /* Only add timings if override was not there or failed to validate */ 251 if (num == 0 && panel->desc->num_timings) 252 num = panel_simple_get_timings_modes(panel, connector); 253 254 /* 255 * Only add fixed modes if timings/override added no mode. 256 * 257 * We should only ever have either the display timings specified 258 * or a fixed mode. Anything else is rather bogus. 259 */ 260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 261 if (num == 0) 262 num = panel_simple_get_display_modes(panel, connector); 263 264 connector->display_info.bpc = panel->desc->bpc; 265 connector->display_info.width_mm = panel->desc->size.width; 266 connector->display_info.height_mm = panel->desc->size.height; 267 if (panel->desc->bus_format) 268 drm_display_info_set_bus_formats(&connector->display_info, 269 &panel->desc->bus_format, 1); 270 connector->display_info.bus_flags = panel->desc->bus_flags; 271 272 return num; 273 } 274 275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 276 { 277 ktime_t now_ktime, min_ktime; 278 279 if (!min_ms) 280 return; 281 282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 283 now_ktime = ktime_get_boottime(); 284 285 if (ktime_before(now_ktime, min_ktime)) 286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 287 } 288 289 static int panel_simple_disable(struct drm_panel *panel) 290 { 291 struct panel_simple *p = to_panel_simple(panel); 292 293 if (!p->enabled) 294 return 0; 295 296 if (p->desc->delay.disable) 297 msleep(p->desc->delay.disable); 298 299 p->enabled = false; 300 301 return 0; 302 } 303 304 static int panel_simple_suspend(struct device *dev) 305 { 306 struct panel_simple *p = dev_get_drvdata(dev); 307 308 gpiod_set_value_cansleep(p->enable_gpio, 0); 309 regulator_disable(p->supply); 310 p->unprepared_time = ktime_get_boottime(); 311 312 kfree(p->edid); 313 p->edid = NULL; 314 315 return 0; 316 } 317 318 static int panel_simple_unprepare(struct drm_panel *panel) 319 { 320 struct panel_simple *p = to_panel_simple(panel); 321 int ret; 322 323 /* Unpreparing when already unprepared is a no-op */ 324 if (!p->prepared) 325 return 0; 326 327 pm_runtime_mark_last_busy(panel->dev); 328 ret = pm_runtime_put_autosuspend(panel->dev); 329 if (ret < 0) 330 return ret; 331 p->prepared = false; 332 333 return 0; 334 } 335 336 static int panel_simple_resume(struct device *dev) 337 { 338 struct panel_simple *p = dev_get_drvdata(dev); 339 int err; 340 341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 342 343 err = regulator_enable(p->supply); 344 if (err < 0) { 345 dev_err(dev, "failed to enable supply: %d\n", err); 346 return err; 347 } 348 349 gpiod_set_value_cansleep(p->enable_gpio, 1); 350 351 if (p->desc->delay.prepare) 352 msleep(p->desc->delay.prepare); 353 354 return 0; 355 } 356 357 static int panel_simple_prepare(struct drm_panel *panel) 358 { 359 struct panel_simple *p = to_panel_simple(panel); 360 int ret; 361 362 /* Preparing when already prepared is a no-op */ 363 if (p->prepared) 364 return 0; 365 366 ret = pm_runtime_get_sync(panel->dev); 367 if (ret < 0) { 368 pm_runtime_put_autosuspend(panel->dev); 369 return ret; 370 } 371 372 p->prepared = true; 373 374 return 0; 375 } 376 377 static int panel_simple_enable(struct drm_panel *panel) 378 { 379 struct panel_simple *p = to_panel_simple(panel); 380 381 if (p->enabled) 382 return 0; 383 384 if (p->desc->delay.enable) 385 msleep(p->desc->delay.enable); 386 387 p->enabled = true; 388 389 return 0; 390 } 391 392 static int panel_simple_get_modes(struct drm_panel *panel, 393 struct drm_connector *connector) 394 { 395 struct panel_simple *p = to_panel_simple(panel); 396 int num = 0; 397 398 /* probe EDID if a DDC bus is available */ 399 if (p->ddc) { 400 pm_runtime_get_sync(panel->dev); 401 402 if (!p->edid) 403 p->edid = drm_get_edid(connector, p->ddc); 404 405 if (p->edid) 406 num += drm_add_edid_modes(connector, p->edid); 407 408 pm_runtime_mark_last_busy(panel->dev); 409 pm_runtime_put_autosuspend(panel->dev); 410 } 411 412 /* add hard-coded panel modes */ 413 num += panel_simple_get_non_edid_modes(p, connector); 414 415 /* 416 * TODO: Remove once all drm drivers call 417 * drm_connector_set_orientation_from_panel() 418 */ 419 drm_connector_set_panel_orientation(connector, p->orientation); 420 421 return num; 422 } 423 424 static int panel_simple_get_timings(struct drm_panel *panel, 425 unsigned int num_timings, 426 struct display_timing *timings) 427 { 428 struct panel_simple *p = to_panel_simple(panel); 429 unsigned int i; 430 431 if (p->desc->num_timings < num_timings) 432 num_timings = p->desc->num_timings; 433 434 if (timings) 435 for (i = 0; i < num_timings; i++) 436 timings[i] = p->desc->timings[i]; 437 438 return p->desc->num_timings; 439 } 440 441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 442 { 443 struct panel_simple *p = to_panel_simple(panel); 444 445 return p->orientation; 446 } 447 448 static const struct drm_panel_funcs panel_simple_funcs = { 449 .disable = panel_simple_disable, 450 .unprepare = panel_simple_unprepare, 451 .prepare = panel_simple_prepare, 452 .enable = panel_simple_enable, 453 .get_modes = panel_simple_get_modes, 454 .get_orientation = panel_simple_get_orientation, 455 .get_timings = panel_simple_get_timings, 456 }; 457 458 static struct panel_desc panel_dpi; 459 460 static int panel_dpi_probe(struct device *dev, 461 struct panel_simple *panel) 462 { 463 struct display_timing *timing; 464 const struct device_node *np; 465 struct panel_desc *desc; 466 unsigned int bus_flags; 467 struct videomode vm; 468 int ret; 469 470 np = dev->of_node; 471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 472 if (!desc) 473 return -ENOMEM; 474 475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 476 if (!timing) 477 return -ENOMEM; 478 479 ret = of_get_display_timing(np, "panel-timing", timing); 480 if (ret < 0) { 481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 482 np); 483 return ret; 484 } 485 486 desc->timings = timing; 487 desc->num_timings = 1; 488 489 of_property_read_u32(np, "width-mm", &desc->size.width); 490 of_property_read_u32(np, "height-mm", &desc->size.height); 491 492 /* Extract bus_flags from display_timing */ 493 bus_flags = 0; 494 vm.flags = timing->flags; 495 drm_bus_flags_from_videomode(&vm, &bus_flags); 496 desc->bus_flags = bus_flags; 497 498 /* We do not know the connector for the DT node, so guess it */ 499 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 500 501 panel->desc = desc; 502 503 return 0; 504 } 505 506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 507 (to_check->field.typ >= bounds->field.min && \ 508 to_check->field.typ <= bounds->field.max) 509 static void panel_simple_parse_panel_timing_node(struct device *dev, 510 struct panel_simple *panel, 511 const struct display_timing *ot) 512 { 513 const struct panel_desc *desc = panel->desc; 514 struct videomode vm; 515 unsigned int i; 516 517 if (WARN_ON(desc->num_modes)) { 518 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 519 return; 520 } 521 if (WARN_ON(!desc->num_timings)) { 522 dev_err(dev, "Reject override mode: no timings specified\n"); 523 return; 524 } 525 526 for (i = 0; i < panel->desc->num_timings; i++) { 527 const struct display_timing *dt = &panel->desc->timings[i]; 528 529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 537 continue; 538 539 if (ot->flags != dt->flags) 540 continue; 541 542 videomode_from_timing(ot, &vm); 543 drm_display_mode_from_videomode(&vm, &panel->override_mode); 544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 545 DRM_MODE_TYPE_PREFERRED; 546 break; 547 } 548 549 if (WARN_ON(!panel->override_mode.type)) 550 dev_err(dev, "Reject override mode: No display_timing found\n"); 551 } 552 553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 554 struct panel_simple *panel) 555 { 556 int ret, bpc; 557 558 ret = drm_of_lvds_get_data_mapping(dev->of_node); 559 if (ret < 0) { 560 if (ret == -EINVAL) 561 dev_warn(dev, "Ignore invalid data-mapping property\n"); 562 563 /* 564 * Ignore non-existing or malformatted property, fallback to 565 * default data-mapping, and return 0. 566 */ 567 return 0; 568 } 569 570 switch (ret) { 571 default: 572 WARN_ON(1); 573 fallthrough; 574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 575 fallthrough; 576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 577 bpc = 8; 578 break; 579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 580 bpc = 6; 581 } 582 583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 584 struct panel_desc *override_desc; 585 586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 587 if (!override_desc) 588 return -ENOMEM; 589 590 override_desc->bus_format = ret; 591 override_desc->bpc = bpc; 592 panel->desc = override_desc; 593 } 594 595 return 0; 596 } 597 598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 599 { 600 struct panel_simple *panel; 601 struct display_timing dt; 602 struct device_node *ddc; 603 int connector_type; 604 u32 bus_flags; 605 int err; 606 607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 608 if (!panel) 609 return -ENOMEM; 610 611 panel->enabled = false; 612 panel->desc = desc; 613 614 panel->supply = devm_regulator_get(dev, "power"); 615 if (IS_ERR(panel->supply)) 616 return PTR_ERR(panel->supply); 617 618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 619 GPIOD_OUT_LOW); 620 if (IS_ERR(panel->enable_gpio)) 621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 622 "failed to request GPIO\n"); 623 624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 625 if (err) { 626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 627 return err; 628 } 629 630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 631 if (ddc) { 632 panel->ddc = of_find_i2c_adapter_by_node(ddc); 633 of_node_put(ddc); 634 635 if (!panel->ddc) 636 return -EPROBE_DEFER; 637 } 638 639 if (desc == &panel_dpi) { 640 /* Handle the generic panel-dpi binding */ 641 err = panel_dpi_probe(dev, panel); 642 if (err) 643 goto free_ddc; 644 desc = panel->desc; 645 } else { 646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 647 panel_simple_parse_panel_timing_node(dev, panel, &dt); 648 } 649 650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 651 /* Optional data-mapping property for overriding bus format */ 652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 653 if (err) 654 goto free_ddc; 655 } 656 657 connector_type = desc->connector_type; 658 /* Catch common mistakes for panels. */ 659 switch (connector_type) { 660 case 0: 661 dev_warn(dev, "Specify missing connector_type\n"); 662 connector_type = DRM_MODE_CONNECTOR_DPI; 663 break; 664 case DRM_MODE_CONNECTOR_LVDS: 665 WARN_ON(desc->bus_flags & 666 ~(DRM_BUS_FLAG_DE_LOW | 667 DRM_BUS_FLAG_DE_HIGH | 668 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 669 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 674 desc->bpc != 6); 675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 677 desc->bpc != 8); 678 break; 679 case DRM_MODE_CONNECTOR_eDP: 680 dev_warn(dev, "eDP panels moved to panel-edp\n"); 681 err = -EINVAL; 682 goto free_ddc; 683 case DRM_MODE_CONNECTOR_DSI: 684 if (desc->bpc != 6 && desc->bpc != 8) 685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 686 break; 687 case DRM_MODE_CONNECTOR_DPI: 688 bus_flags = DRM_BUS_FLAG_DE_LOW | 689 DRM_BUS_FLAG_DE_HIGH | 690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 692 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 693 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 696 if (desc->bus_flags & ~bus_flags) 697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 698 if (!(desc->bus_flags & bus_flags)) 699 dev_warn(dev, "Specify missing bus_flags\n"); 700 if (desc->bus_format == 0) 701 dev_warn(dev, "Specify missing bus_format\n"); 702 if (desc->bpc != 6 && desc->bpc != 8) 703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 704 break; 705 default: 706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 707 connector_type = DRM_MODE_CONNECTOR_DPI; 708 break; 709 } 710 711 dev_set_drvdata(dev, panel); 712 713 /* 714 * We use runtime PM for prepare / unprepare since those power the panel 715 * on and off and those can be very slow operations. This is important 716 * to optimize powering the panel on briefly to read the EDID before 717 * fully enabling the panel. 718 */ 719 pm_runtime_enable(dev); 720 pm_runtime_set_autosuspend_delay(dev, 1000); 721 pm_runtime_use_autosuspend(dev); 722 723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 724 725 err = drm_panel_of_backlight(&panel->base); 726 if (err) { 727 dev_err_probe(dev, err, "Could not find backlight\n"); 728 goto disable_pm_runtime; 729 } 730 731 drm_panel_add(&panel->base); 732 733 return 0; 734 735 disable_pm_runtime: 736 pm_runtime_dont_use_autosuspend(dev); 737 pm_runtime_disable(dev); 738 free_ddc: 739 if (panel->ddc) 740 put_device(&panel->ddc->dev); 741 742 return err; 743 } 744 745 static void panel_simple_remove(struct device *dev) 746 { 747 struct panel_simple *panel = dev_get_drvdata(dev); 748 749 drm_panel_remove(&panel->base); 750 drm_panel_disable(&panel->base); 751 drm_panel_unprepare(&panel->base); 752 753 pm_runtime_dont_use_autosuspend(dev); 754 pm_runtime_disable(dev); 755 if (panel->ddc) 756 put_device(&panel->ddc->dev); 757 } 758 759 static void panel_simple_shutdown(struct device *dev) 760 { 761 struct panel_simple *panel = dev_get_drvdata(dev); 762 763 drm_panel_disable(&panel->base); 764 drm_panel_unprepare(&panel->base); 765 } 766 767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 768 .clock = 71100, 769 .hdisplay = 1280, 770 .hsync_start = 1280 + 40, 771 .hsync_end = 1280 + 40 + 80, 772 .htotal = 1280 + 40 + 80 + 40, 773 .vdisplay = 800, 774 .vsync_start = 800 + 3, 775 .vsync_end = 800 + 3 + 10, 776 .vtotal = 800 + 3 + 10 + 10, 777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 778 }; 779 780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 781 .modes = &ire_am_1280800n3tzqw_t00h_mode, 782 .num_modes = 1, 783 .bpc = 8, 784 .size = { 785 .width = 217, 786 .height = 136, 787 }, 788 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 790 .connector_type = DRM_MODE_CONNECTOR_LVDS, 791 }; 792 793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 794 .clock = 9000, 795 .hdisplay = 480, 796 .hsync_start = 480 + 2, 797 .hsync_end = 480 + 2 + 41, 798 .htotal = 480 + 2 + 41 + 2, 799 .vdisplay = 272, 800 .vsync_start = 272 + 2, 801 .vsync_end = 272 + 2 + 10, 802 .vtotal = 272 + 2 + 10 + 2, 803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 804 }; 805 806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 807 .modes = &ire_am_480272h3tmqw_t01h_mode, 808 .num_modes = 1, 809 .bpc = 8, 810 .size = { 811 .width = 99, 812 .height = 58, 813 }, 814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 815 }; 816 817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 818 .clock = 33333, 819 .hdisplay = 800, 820 .hsync_start = 800 + 0, 821 .hsync_end = 800 + 0 + 255, 822 .htotal = 800 + 0 + 255 + 0, 823 .vdisplay = 480, 824 .vsync_start = 480 + 2, 825 .vsync_end = 480 + 2 + 45, 826 .vtotal = 480 + 2 + 45 + 0, 827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 828 }; 829 830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 831 .pixelclock = { 29930000, 33260000, 36590000 }, 832 .hactive = { 800, 800, 800 }, 833 .hfront_porch = { 1, 40, 168 }, 834 .hback_porch = { 88, 88, 88 }, 835 .hsync_len = { 1, 128, 128 }, 836 .vactive = { 480, 480, 480 }, 837 .vfront_porch = { 1, 35, 37 }, 838 .vback_porch = { 8, 8, 8 }, 839 .vsync_len = { 1, 2, 2 }, 840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 842 DISPLAY_FLAGS_SYNC_POSEDGE, 843 }; 844 845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 846 .timings = &ire_am_800480l1tmqw_t00h_timing, 847 .num_timings = 1, 848 .bpc = 8, 849 .size = { 850 .width = 111, 851 .height = 67, 852 }, 853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 854 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 857 .connector_type = DRM_MODE_CONNECTOR_DPI, 858 }; 859 860 static const struct panel_desc ampire_am800480r3tmqwa1h = { 861 .modes = &ire_am800480r3tmqwa1h_mode, 862 .num_modes = 1, 863 .bpc = 6, 864 .size = { 865 .width = 152, 866 .height = 91, 867 }, 868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 869 }; 870 871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 872 .pixelclock = { 34500000, 39600000, 50400000 }, 873 .hactive = { 800, 800, 800 }, 874 .hfront_porch = { 12, 112, 312 }, 875 .hback_porch = { 87, 87, 48 }, 876 .hsync_len = { 1, 1, 40 }, 877 .vactive = { 600, 600, 600 }, 878 .vfront_porch = { 1, 21, 61 }, 879 .vback_porch = { 38, 38, 19 }, 880 .vsync_len = { 1, 1, 20 }, 881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 883 DISPLAY_FLAGS_SYNC_POSEDGE, 884 }; 885 886 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 887 .timings = &ire_am800600p5tmqw_tb8h_timing, 888 .num_timings = 1, 889 .bpc = 6, 890 .size = { 891 .width = 162, 892 .height = 122, 893 }, 894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 895 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 898 .connector_type = DRM_MODE_CONNECTOR_DPI, 899 }; 900 901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 902 .pixelclock = { 26400000, 33300000, 46800000 }, 903 .hactive = { 800, 800, 800 }, 904 .hfront_porch = { 16, 210, 354 }, 905 .hback_porch = { 45, 36, 6 }, 906 .hsync_len = { 1, 10, 40 }, 907 .vactive = { 480, 480, 480 }, 908 .vfront_porch = { 7, 22, 147 }, 909 .vback_porch = { 22, 13, 3 }, 910 .vsync_len = { 1, 10, 20 }, 911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 913 }; 914 915 static const struct panel_desc armadeus_st0700_adapt = { 916 .timings = &santek_st0700i5y_rbslw_f_timing, 917 .num_timings = 1, 918 .bpc = 6, 919 .size = { 920 .width = 154, 921 .height = 86, 922 }, 923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 925 }; 926 927 static const struct drm_display_mode auo_b101aw03_mode = { 928 .clock = 51450, 929 .hdisplay = 1024, 930 .hsync_start = 1024 + 156, 931 .hsync_end = 1024 + 156 + 8, 932 .htotal = 1024 + 156 + 8 + 156, 933 .vdisplay = 600, 934 .vsync_start = 600 + 16, 935 .vsync_end = 600 + 16 + 6, 936 .vtotal = 600 + 16 + 6 + 16, 937 }; 938 939 static const struct panel_desc auo_b101aw03 = { 940 .modes = &auo_b101aw03_mode, 941 .num_modes = 1, 942 .bpc = 6, 943 .size = { 944 .width = 223, 945 .height = 125, 946 }, 947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 948 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 949 .connector_type = DRM_MODE_CONNECTOR_LVDS, 950 }; 951 952 static const struct drm_display_mode auo_b101xtn01_mode = { 953 .clock = 72000, 954 .hdisplay = 1366, 955 .hsync_start = 1366 + 20, 956 .hsync_end = 1366 + 20 + 70, 957 .htotal = 1366 + 20 + 70, 958 .vdisplay = 768, 959 .vsync_start = 768 + 14, 960 .vsync_end = 768 + 14 + 42, 961 .vtotal = 768 + 14 + 42, 962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 963 }; 964 965 static const struct panel_desc auo_b101xtn01 = { 966 .modes = &auo_b101xtn01_mode, 967 .num_modes = 1, 968 .bpc = 6, 969 .size = { 970 .width = 223, 971 .height = 125, 972 }, 973 }; 974 975 static const struct drm_display_mode auo_b116xw03_mode = { 976 .clock = 70589, 977 .hdisplay = 1366, 978 .hsync_start = 1366 + 40, 979 .hsync_end = 1366 + 40 + 40, 980 .htotal = 1366 + 40 + 40 + 32, 981 .vdisplay = 768, 982 .vsync_start = 768 + 10, 983 .vsync_end = 768 + 10 + 12, 984 .vtotal = 768 + 10 + 12 + 6, 985 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 986 }; 987 988 static const struct panel_desc auo_b116xw03 = { 989 .modes = &auo_b116xw03_mode, 990 .num_modes = 1, 991 .bpc = 6, 992 .size = { 993 .width = 256, 994 .height = 144, 995 }, 996 .delay = { 997 .prepare = 1, 998 .enable = 200, 999 .disable = 200, 1000 .unprepare = 500, 1001 }, 1002 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1003 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1004 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1005 }; 1006 1007 static const struct display_timing auo_g070vvn01_timings = { 1008 .pixelclock = { 33300000, 34209000, 45000000 }, 1009 .hactive = { 800, 800, 800 }, 1010 .hfront_porch = { 20, 40, 200 }, 1011 .hback_porch = { 87, 40, 1 }, 1012 .hsync_len = { 1, 48, 87 }, 1013 .vactive = { 480, 480, 480 }, 1014 .vfront_porch = { 5, 13, 200 }, 1015 .vback_porch = { 31, 31, 29 }, 1016 .vsync_len = { 1, 1, 3 }, 1017 }; 1018 1019 static const struct panel_desc auo_g070vvn01 = { 1020 .timings = &auo_g070vvn01_timings, 1021 .num_timings = 1, 1022 .bpc = 8, 1023 .size = { 1024 .width = 152, 1025 .height = 91, 1026 }, 1027 .delay = { 1028 .prepare = 200, 1029 .enable = 50, 1030 .disable = 50, 1031 .unprepare = 1000, 1032 }, 1033 }; 1034 1035 static const struct drm_display_mode auo_g101evn010_mode = { 1036 .clock = 68930, 1037 .hdisplay = 1280, 1038 .hsync_start = 1280 + 82, 1039 .hsync_end = 1280 + 82 + 2, 1040 .htotal = 1280 + 82 + 2 + 84, 1041 .vdisplay = 800, 1042 .vsync_start = 800 + 8, 1043 .vsync_end = 800 + 8 + 2, 1044 .vtotal = 800 + 8 + 2 + 6, 1045 }; 1046 1047 static const struct panel_desc auo_g101evn010 = { 1048 .modes = &auo_g101evn010_mode, 1049 .num_modes = 1, 1050 .bpc = 6, 1051 .size = { 1052 .width = 216, 1053 .height = 135, 1054 }, 1055 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1057 }; 1058 1059 static const struct drm_display_mode auo_g104sn02_mode = { 1060 .clock = 40000, 1061 .hdisplay = 800, 1062 .hsync_start = 800 + 40, 1063 .hsync_end = 800 + 40 + 216, 1064 .htotal = 800 + 40 + 216 + 128, 1065 .vdisplay = 600, 1066 .vsync_start = 600 + 10, 1067 .vsync_end = 600 + 10 + 35, 1068 .vtotal = 600 + 10 + 35 + 2, 1069 }; 1070 1071 static const struct panel_desc auo_g104sn02 = { 1072 .modes = &auo_g104sn02_mode, 1073 .num_modes = 1, 1074 .bpc = 8, 1075 .size = { 1076 .width = 211, 1077 .height = 158, 1078 }, 1079 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1080 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1081 }; 1082 1083 static const struct display_timing auo_g121ean01_timing = { 1084 .pixelclock = { 60000000, 74400000, 90000000 }, 1085 .hactive = { 1280, 1280, 1280 }, 1086 .hfront_porch = { 20, 50, 100 }, 1087 .hback_porch = { 20, 50, 100 }, 1088 .hsync_len = { 30, 100, 200 }, 1089 .vactive = { 800, 800, 800 }, 1090 .vfront_porch = { 2, 10, 25 }, 1091 .vback_porch = { 2, 10, 25 }, 1092 .vsync_len = { 4, 18, 50 }, 1093 }; 1094 1095 static const struct panel_desc auo_g121ean01 = { 1096 .timings = &auo_g121ean01_timing, 1097 .num_timings = 1, 1098 .bpc = 8, 1099 .size = { 1100 .width = 261, 1101 .height = 163, 1102 }, 1103 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1104 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1105 }; 1106 1107 static const struct display_timing auo_g133han01_timings = { 1108 .pixelclock = { 134000000, 141200000, 149000000 }, 1109 .hactive = { 1920, 1920, 1920 }, 1110 .hfront_porch = { 39, 58, 77 }, 1111 .hback_porch = { 59, 88, 117 }, 1112 .hsync_len = { 28, 42, 56 }, 1113 .vactive = { 1080, 1080, 1080 }, 1114 .vfront_porch = { 3, 8, 11 }, 1115 .vback_porch = { 5, 14, 19 }, 1116 .vsync_len = { 4, 14, 19 }, 1117 }; 1118 1119 static const struct panel_desc auo_g133han01 = { 1120 .timings = &auo_g133han01_timings, 1121 .num_timings = 1, 1122 .bpc = 8, 1123 .size = { 1124 .width = 293, 1125 .height = 165, 1126 }, 1127 .delay = { 1128 .prepare = 200, 1129 .enable = 50, 1130 .disable = 50, 1131 .unprepare = 1000, 1132 }, 1133 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1134 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1135 }; 1136 1137 static const struct display_timing auo_g156han04_timings = { 1138 .pixelclock = { 137000000, 141000000, 146000000 }, 1139 .hactive = { 1920, 1920, 1920 }, 1140 .hfront_porch = { 60, 60, 60 }, 1141 .hback_porch = { 90, 92, 111 }, 1142 .hsync_len = { 32, 32, 32 }, 1143 .vactive = { 1080, 1080, 1080 }, 1144 .vfront_porch = { 12, 12, 12 }, 1145 .vback_porch = { 24, 36, 56 }, 1146 .vsync_len = { 8, 8, 8 }, 1147 }; 1148 1149 static const struct panel_desc auo_g156han04 = { 1150 .timings = &auo_g156han04_timings, 1151 .num_timings = 1, 1152 .bpc = 8, 1153 .size = { 1154 .width = 344, 1155 .height = 194, 1156 }, 1157 .delay = { 1158 .prepare = 50, /* T2 */ 1159 .enable = 200, /* T3 */ 1160 .disable = 110, /* T10 */ 1161 .unprepare = 1000, /* T13 */ 1162 }, 1163 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1164 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1165 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1166 }; 1167 1168 static const struct drm_display_mode auo_g156xtn01_mode = { 1169 .clock = 76000, 1170 .hdisplay = 1366, 1171 .hsync_start = 1366 + 33, 1172 .hsync_end = 1366 + 33 + 67, 1173 .htotal = 1560, 1174 .vdisplay = 768, 1175 .vsync_start = 768 + 4, 1176 .vsync_end = 768 + 4 + 4, 1177 .vtotal = 806, 1178 }; 1179 1180 static const struct panel_desc auo_g156xtn01 = { 1181 .modes = &auo_g156xtn01_mode, 1182 .num_modes = 1, 1183 .bpc = 8, 1184 .size = { 1185 .width = 344, 1186 .height = 194, 1187 }, 1188 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1189 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1190 }; 1191 1192 static const struct display_timing auo_g185han01_timings = { 1193 .pixelclock = { 120000000, 144000000, 175000000 }, 1194 .hactive = { 1920, 1920, 1920 }, 1195 .hfront_porch = { 36, 120, 148 }, 1196 .hback_porch = { 24, 88, 108 }, 1197 .hsync_len = { 20, 48, 64 }, 1198 .vactive = { 1080, 1080, 1080 }, 1199 .vfront_porch = { 6, 10, 40 }, 1200 .vback_porch = { 2, 5, 20 }, 1201 .vsync_len = { 2, 5, 20 }, 1202 }; 1203 1204 static const struct panel_desc auo_g185han01 = { 1205 .timings = &auo_g185han01_timings, 1206 .num_timings = 1, 1207 .bpc = 8, 1208 .size = { 1209 .width = 409, 1210 .height = 230, 1211 }, 1212 .delay = { 1213 .prepare = 50, 1214 .enable = 200, 1215 .disable = 110, 1216 .unprepare = 1000, 1217 }, 1218 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1219 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1220 }; 1221 1222 static const struct display_timing auo_g190ean01_timings = { 1223 .pixelclock = { 90000000, 108000000, 135000000 }, 1224 .hactive = { 1280, 1280, 1280 }, 1225 .hfront_porch = { 126, 184, 1266 }, 1226 .hback_porch = { 84, 122, 844 }, 1227 .hsync_len = { 70, 102, 704 }, 1228 .vactive = { 1024, 1024, 1024 }, 1229 .vfront_porch = { 4, 26, 76 }, 1230 .vback_porch = { 2, 8, 25 }, 1231 .vsync_len = { 2, 8, 25 }, 1232 }; 1233 1234 static const struct panel_desc auo_g190ean01 = { 1235 .timings = &auo_g190ean01_timings, 1236 .num_timings = 1, 1237 .bpc = 8, 1238 .size = { 1239 .width = 376, 1240 .height = 301, 1241 }, 1242 .delay = { 1243 .prepare = 50, 1244 .enable = 200, 1245 .disable = 110, 1246 .unprepare = 1000, 1247 }, 1248 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1249 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1250 }; 1251 1252 static const struct display_timing auo_p320hvn03_timings = { 1253 .pixelclock = { 106000000, 148500000, 164000000 }, 1254 .hactive = { 1920, 1920, 1920 }, 1255 .hfront_porch = { 25, 50, 130 }, 1256 .hback_porch = { 25, 50, 130 }, 1257 .hsync_len = { 20, 40, 105 }, 1258 .vactive = { 1080, 1080, 1080 }, 1259 .vfront_porch = { 8, 17, 150 }, 1260 .vback_porch = { 8, 17, 150 }, 1261 .vsync_len = { 4, 11, 100 }, 1262 }; 1263 1264 static const struct panel_desc auo_p320hvn03 = { 1265 .timings = &auo_p320hvn03_timings, 1266 .num_timings = 1, 1267 .bpc = 8, 1268 .size = { 1269 .width = 698, 1270 .height = 393, 1271 }, 1272 .delay = { 1273 .prepare = 1, 1274 .enable = 450, 1275 .unprepare = 500, 1276 }, 1277 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1278 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1279 }; 1280 1281 static const struct drm_display_mode auo_t215hvn01_mode = { 1282 .clock = 148800, 1283 .hdisplay = 1920, 1284 .hsync_start = 1920 + 88, 1285 .hsync_end = 1920 + 88 + 44, 1286 .htotal = 1920 + 88 + 44 + 148, 1287 .vdisplay = 1080, 1288 .vsync_start = 1080 + 4, 1289 .vsync_end = 1080 + 4 + 5, 1290 .vtotal = 1080 + 4 + 5 + 36, 1291 }; 1292 1293 static const struct panel_desc auo_t215hvn01 = { 1294 .modes = &auo_t215hvn01_mode, 1295 .num_modes = 1, 1296 .bpc = 8, 1297 .size = { 1298 .width = 430, 1299 .height = 270, 1300 }, 1301 .delay = { 1302 .disable = 5, 1303 .unprepare = 1000, 1304 }, 1305 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1306 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1307 }; 1308 1309 static const struct drm_display_mode avic_tm070ddh03_mode = { 1310 .clock = 51200, 1311 .hdisplay = 1024, 1312 .hsync_start = 1024 + 160, 1313 .hsync_end = 1024 + 160 + 4, 1314 .htotal = 1024 + 160 + 4 + 156, 1315 .vdisplay = 600, 1316 .vsync_start = 600 + 17, 1317 .vsync_end = 600 + 17 + 1, 1318 .vtotal = 600 + 17 + 1 + 17, 1319 }; 1320 1321 static const struct panel_desc avic_tm070ddh03 = { 1322 .modes = &avic_tm070ddh03_mode, 1323 .num_modes = 1, 1324 .bpc = 8, 1325 .size = { 1326 .width = 154, 1327 .height = 90, 1328 }, 1329 .delay = { 1330 .prepare = 20, 1331 .enable = 200, 1332 .disable = 200, 1333 }, 1334 }; 1335 1336 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1337 .clock = 30000, 1338 .hdisplay = 800, 1339 .hsync_start = 800 + 40, 1340 .hsync_end = 800 + 40 + 48, 1341 .htotal = 800 + 40 + 48 + 40, 1342 .vdisplay = 480, 1343 .vsync_start = 480 + 13, 1344 .vsync_end = 480 + 13 + 3, 1345 .vtotal = 480 + 13 + 3 + 29, 1346 }; 1347 1348 static const struct panel_desc bananapi_s070wv20_ct16 = { 1349 .modes = &bananapi_s070wv20_ct16_mode, 1350 .num_modes = 1, 1351 .bpc = 6, 1352 .size = { 1353 .width = 154, 1354 .height = 86, 1355 }, 1356 }; 1357 1358 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1359 .clock = 78945, 1360 .hdisplay = 1280, 1361 .hsync_start = 1280 + 0, 1362 .hsync_end = 1280 + 0 + 2, 1363 .htotal = 1280 + 62 + 0 + 2, 1364 .vdisplay = 800, 1365 .vsync_start = 800 + 8, 1366 .vsync_end = 800 + 8 + 2, 1367 .vtotal = 800 + 6 + 8 + 2, 1368 }; 1369 1370 static const struct panel_desc boe_bp101wx1_100 = { 1371 .modes = &boe_bp101wx1_100_mode, 1372 .num_modes = 1, 1373 .bpc = 8, 1374 .size = { 1375 .width = 217, 1376 .height = 136, 1377 }, 1378 .delay = { 1379 .enable = 50, 1380 .disable = 50, 1381 }, 1382 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1383 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1384 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1385 }; 1386 1387 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1388 .pixelclock = { 69922000, 71000000, 72293000 }, 1389 .hactive = { 1280, 1280, 1280 }, 1390 .hfront_porch = { 48, 48, 48 }, 1391 .hback_porch = { 80, 80, 80 }, 1392 .hsync_len = { 32, 32, 32 }, 1393 .vactive = { 800, 800, 800 }, 1394 .vfront_porch = { 3, 3, 3 }, 1395 .vback_porch = { 14, 14, 14 }, 1396 .vsync_len = { 6, 6, 6 }, 1397 }; 1398 1399 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1400 .timings = &boe_ev121wxm_n10_1850_timing, 1401 .num_timings = 1, 1402 .bpc = 8, 1403 .size = { 1404 .width = 261, 1405 .height = 163, 1406 }, 1407 .delay = { 1408 .prepare = 9, 1409 .enable = 300, 1410 .unprepare = 300, 1411 .disable = 560, 1412 }, 1413 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1414 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1415 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1416 }; 1417 1418 static const struct drm_display_mode boe_hv070wsa_mode = { 1419 .clock = 42105, 1420 .hdisplay = 1024, 1421 .hsync_start = 1024 + 30, 1422 .hsync_end = 1024 + 30 + 30, 1423 .htotal = 1024 + 30 + 30 + 30, 1424 .vdisplay = 600, 1425 .vsync_start = 600 + 10, 1426 .vsync_end = 600 + 10 + 10, 1427 .vtotal = 600 + 10 + 10 + 10, 1428 }; 1429 1430 static const struct panel_desc boe_hv070wsa = { 1431 .modes = &boe_hv070wsa_mode, 1432 .num_modes = 1, 1433 .bpc = 8, 1434 .size = { 1435 .width = 154, 1436 .height = 90, 1437 }, 1438 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1439 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1440 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1441 }; 1442 1443 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1444 .clock = 9000, 1445 .hdisplay = 480, 1446 .hsync_start = 480 + 5, 1447 .hsync_end = 480 + 5 + 5, 1448 .htotal = 480 + 5 + 5 + 40, 1449 .vdisplay = 272, 1450 .vsync_start = 272 + 8, 1451 .vsync_end = 272 + 8 + 8, 1452 .vtotal = 272 + 8 + 8 + 8, 1453 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1454 }; 1455 1456 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1457 .modes = &cdtech_s043wq26h_ct7_mode, 1458 .num_modes = 1, 1459 .bpc = 8, 1460 .size = { 1461 .width = 95, 1462 .height = 54, 1463 }, 1464 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1465 }; 1466 1467 /* S070PWS19HP-FC21 2017/04/22 */ 1468 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1469 .clock = 51200, 1470 .hdisplay = 1024, 1471 .hsync_start = 1024 + 160, 1472 .hsync_end = 1024 + 160 + 20, 1473 .htotal = 1024 + 160 + 20 + 140, 1474 .vdisplay = 600, 1475 .vsync_start = 600 + 12, 1476 .vsync_end = 600 + 12 + 3, 1477 .vtotal = 600 + 12 + 3 + 20, 1478 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1479 }; 1480 1481 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1482 .modes = &cdtech_s070pws19hp_fc21_mode, 1483 .num_modes = 1, 1484 .bpc = 6, 1485 .size = { 1486 .width = 154, 1487 .height = 86, 1488 }, 1489 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1490 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1491 .connector_type = DRM_MODE_CONNECTOR_DPI, 1492 }; 1493 1494 /* S070SWV29HG-DC44 2017/09/21 */ 1495 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1496 .clock = 33300, 1497 .hdisplay = 800, 1498 .hsync_start = 800 + 210, 1499 .hsync_end = 800 + 210 + 2, 1500 .htotal = 800 + 210 + 2 + 44, 1501 .vdisplay = 480, 1502 .vsync_start = 480 + 22, 1503 .vsync_end = 480 + 22 + 2, 1504 .vtotal = 480 + 22 + 2 + 21, 1505 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1506 }; 1507 1508 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1509 .modes = &cdtech_s070swv29hg_dc44_mode, 1510 .num_modes = 1, 1511 .bpc = 6, 1512 .size = { 1513 .width = 154, 1514 .height = 86, 1515 }, 1516 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1517 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1518 .connector_type = DRM_MODE_CONNECTOR_DPI, 1519 }; 1520 1521 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1522 .clock = 35000, 1523 .hdisplay = 800, 1524 .hsync_start = 800 + 40, 1525 .hsync_end = 800 + 40 + 40, 1526 .htotal = 800 + 40 + 40 + 48, 1527 .vdisplay = 480, 1528 .vsync_start = 480 + 29, 1529 .vsync_end = 480 + 29 + 13, 1530 .vtotal = 480 + 29 + 13 + 3, 1531 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1532 }; 1533 1534 static const struct panel_desc cdtech_s070wv95_ct16 = { 1535 .modes = &cdtech_s070wv95_ct16_mode, 1536 .num_modes = 1, 1537 .bpc = 8, 1538 .size = { 1539 .width = 154, 1540 .height = 85, 1541 }, 1542 }; 1543 1544 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1545 .pixelclock = { 68900000, 71100000, 73400000 }, 1546 .hactive = { 1280, 1280, 1280 }, 1547 .hfront_porch = { 65, 80, 95 }, 1548 .hback_porch = { 64, 79, 94 }, 1549 .hsync_len = { 1, 1, 1 }, 1550 .vactive = { 800, 800, 800 }, 1551 .vfront_porch = { 7, 11, 14 }, 1552 .vback_porch = { 7, 11, 14 }, 1553 .vsync_len = { 1, 1, 1 }, 1554 .flags = DISPLAY_FLAGS_DE_HIGH, 1555 }; 1556 1557 static const struct panel_desc chefree_ch101olhlwh_002 = { 1558 .timings = &chefree_ch101olhlwh_002_timing, 1559 .num_timings = 1, 1560 .bpc = 8, 1561 .size = { 1562 .width = 217, 1563 .height = 135, 1564 }, 1565 .delay = { 1566 .enable = 200, 1567 .disable = 200, 1568 }, 1569 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1570 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1571 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1572 }; 1573 1574 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1575 .clock = 66770, 1576 .hdisplay = 800, 1577 .hsync_start = 800 + 49, 1578 .hsync_end = 800 + 49 + 33, 1579 .htotal = 800 + 49 + 33 + 17, 1580 .vdisplay = 1280, 1581 .vsync_start = 1280 + 1, 1582 .vsync_end = 1280 + 1 + 7, 1583 .vtotal = 1280 + 1 + 7 + 15, 1584 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1585 }; 1586 1587 static const struct panel_desc chunghwa_claa070wp03xg = { 1588 .modes = &chunghwa_claa070wp03xg_mode, 1589 .num_modes = 1, 1590 .bpc = 6, 1591 .size = { 1592 .width = 94, 1593 .height = 150, 1594 }, 1595 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1596 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1597 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1598 }; 1599 1600 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1601 .clock = 72070, 1602 .hdisplay = 1366, 1603 .hsync_start = 1366 + 58, 1604 .hsync_end = 1366 + 58 + 58, 1605 .htotal = 1366 + 58 + 58 + 58, 1606 .vdisplay = 768, 1607 .vsync_start = 768 + 4, 1608 .vsync_end = 768 + 4 + 4, 1609 .vtotal = 768 + 4 + 4 + 4, 1610 }; 1611 1612 static const struct panel_desc chunghwa_claa101wa01a = { 1613 .modes = &chunghwa_claa101wa01a_mode, 1614 .num_modes = 1, 1615 .bpc = 6, 1616 .size = { 1617 .width = 220, 1618 .height = 120, 1619 }, 1620 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1621 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1622 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1623 }; 1624 1625 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1626 .clock = 69300, 1627 .hdisplay = 1366, 1628 .hsync_start = 1366 + 48, 1629 .hsync_end = 1366 + 48 + 32, 1630 .htotal = 1366 + 48 + 32 + 20, 1631 .vdisplay = 768, 1632 .vsync_start = 768 + 16, 1633 .vsync_end = 768 + 16 + 8, 1634 .vtotal = 768 + 16 + 8 + 16, 1635 }; 1636 1637 static const struct panel_desc chunghwa_claa101wb01 = { 1638 .modes = &chunghwa_claa101wb01_mode, 1639 .num_modes = 1, 1640 .bpc = 6, 1641 .size = { 1642 .width = 223, 1643 .height = 125, 1644 }, 1645 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1646 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1647 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1648 }; 1649 1650 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1651 .pixelclock = { 5000000, 9000000, 12000000 }, 1652 .hactive = { 480, 480, 480 }, 1653 .hfront_porch = { 12, 12, 12 }, 1654 .hback_porch = { 12, 12, 12 }, 1655 .hsync_len = { 21, 21, 21 }, 1656 .vactive = { 272, 272, 272 }, 1657 .vfront_porch = { 4, 4, 4 }, 1658 .vback_porch = { 4, 4, 4 }, 1659 .vsync_len = { 8, 8, 8 }, 1660 }; 1661 1662 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1663 .timings = &dataimage_fg040346dsswbg04_timing, 1664 .num_timings = 1, 1665 .bpc = 8, 1666 .size = { 1667 .width = 95, 1668 .height = 54, 1669 }, 1670 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1671 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1672 .connector_type = DRM_MODE_CONNECTOR_DPI, 1673 }; 1674 1675 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1676 .pixelclock = { 68900000, 71110000, 73400000 }, 1677 .hactive = { 1280, 1280, 1280 }, 1678 .vactive = { 800, 800, 800 }, 1679 .hback_porch = { 100, 100, 100 }, 1680 .hfront_porch = { 100, 100, 100 }, 1681 .vback_porch = { 5, 5, 5 }, 1682 .vfront_porch = { 5, 5, 5 }, 1683 .hsync_len = { 24, 24, 24 }, 1684 .vsync_len = { 3, 3, 3 }, 1685 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1686 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1687 }; 1688 1689 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1690 .timings = &dataimage_fg1001l0dsswmg01_timing, 1691 .num_timings = 1, 1692 .bpc = 8, 1693 .size = { 1694 .width = 217, 1695 .height = 136, 1696 }, 1697 }; 1698 1699 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1700 .clock = 33260, 1701 .hdisplay = 800, 1702 .hsync_start = 800 + 40, 1703 .hsync_end = 800 + 40 + 128, 1704 .htotal = 800 + 40 + 128 + 88, 1705 .vdisplay = 480, 1706 .vsync_start = 480 + 10, 1707 .vsync_end = 480 + 10 + 2, 1708 .vtotal = 480 + 10 + 2 + 33, 1709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1710 }; 1711 1712 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1713 .modes = &dataimage_scf0700c48ggu18_mode, 1714 .num_modes = 1, 1715 .bpc = 8, 1716 .size = { 1717 .width = 152, 1718 .height = 91, 1719 }, 1720 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1721 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1722 }; 1723 1724 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1725 .pixelclock = { 45000000, 51200000, 57000000 }, 1726 .hactive = { 1024, 1024, 1024 }, 1727 .hfront_porch = { 100, 106, 113 }, 1728 .hback_porch = { 100, 106, 113 }, 1729 .hsync_len = { 100, 108, 114 }, 1730 .vactive = { 600, 600, 600 }, 1731 .vfront_porch = { 8, 11, 15 }, 1732 .vback_porch = { 8, 11, 15 }, 1733 .vsync_len = { 9, 13, 15 }, 1734 .flags = DISPLAY_FLAGS_DE_HIGH, 1735 }; 1736 1737 static const struct panel_desc dlc_dlc0700yzg_1 = { 1738 .timings = &dlc_dlc0700yzg_1_timing, 1739 .num_timings = 1, 1740 .bpc = 6, 1741 .size = { 1742 .width = 154, 1743 .height = 86, 1744 }, 1745 .delay = { 1746 .prepare = 30, 1747 .enable = 200, 1748 .disable = 200, 1749 }, 1750 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1751 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1752 }; 1753 1754 static const struct display_timing dlc_dlc1010gig_timing = { 1755 .pixelclock = { 68900000, 71100000, 73400000 }, 1756 .hactive = { 1280, 1280, 1280 }, 1757 .hfront_porch = { 43, 53, 63 }, 1758 .hback_porch = { 43, 53, 63 }, 1759 .hsync_len = { 44, 54, 64 }, 1760 .vactive = { 800, 800, 800 }, 1761 .vfront_porch = { 5, 8, 11 }, 1762 .vback_porch = { 5, 8, 11 }, 1763 .vsync_len = { 5, 7, 11 }, 1764 .flags = DISPLAY_FLAGS_DE_HIGH, 1765 }; 1766 1767 static const struct panel_desc dlc_dlc1010gig = { 1768 .timings = &dlc_dlc1010gig_timing, 1769 .num_timings = 1, 1770 .bpc = 8, 1771 .size = { 1772 .width = 216, 1773 .height = 135, 1774 }, 1775 .delay = { 1776 .prepare = 60, 1777 .enable = 150, 1778 .disable = 100, 1779 .unprepare = 60, 1780 }, 1781 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1782 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1783 }; 1784 1785 static const struct drm_display_mode edt_et035012dm6_mode = { 1786 .clock = 6500, 1787 .hdisplay = 320, 1788 .hsync_start = 320 + 20, 1789 .hsync_end = 320 + 20 + 30, 1790 .htotal = 320 + 20 + 68, 1791 .vdisplay = 240, 1792 .vsync_start = 240 + 4, 1793 .vsync_end = 240 + 4 + 4, 1794 .vtotal = 240 + 4 + 4 + 14, 1795 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1796 }; 1797 1798 static const struct panel_desc edt_et035012dm6 = { 1799 .modes = &edt_et035012dm6_mode, 1800 .num_modes = 1, 1801 .bpc = 8, 1802 .size = { 1803 .width = 70, 1804 .height = 52, 1805 }, 1806 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1807 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1808 }; 1809 1810 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1811 .clock = 6520, 1812 .hdisplay = 320, 1813 .hsync_start = 320 + 20, 1814 .hsync_end = 320 + 20 + 68, 1815 .htotal = 320 + 20 + 68, 1816 .vdisplay = 240, 1817 .vsync_start = 240 + 4, 1818 .vsync_end = 240 + 4 + 18, 1819 .vtotal = 240 + 4 + 18, 1820 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1821 }; 1822 1823 static const struct panel_desc edt_etm0350g0dh6 = { 1824 .modes = &edt_etm0350g0dh6_mode, 1825 .num_modes = 1, 1826 .bpc = 6, 1827 .size = { 1828 .width = 70, 1829 .height = 53, 1830 }, 1831 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1833 .connector_type = DRM_MODE_CONNECTOR_DPI, 1834 }; 1835 1836 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1837 .clock = 10870, 1838 .hdisplay = 480, 1839 .hsync_start = 480 + 8, 1840 .hsync_end = 480 + 8 + 4, 1841 .htotal = 480 + 8 + 4 + 41, 1842 1843 /* 1844 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1845 * fb_align 1846 */ 1847 1848 .vdisplay = 288, 1849 .vsync_start = 288 + 2, 1850 .vsync_end = 288 + 2 + 4, 1851 .vtotal = 288 + 2 + 4 + 10, 1852 }; 1853 1854 static const struct panel_desc edt_etm043080dh6gp = { 1855 .modes = &edt_etm043080dh6gp_mode, 1856 .num_modes = 1, 1857 .bpc = 8, 1858 .size = { 1859 .width = 100, 1860 .height = 65, 1861 }, 1862 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1863 .connector_type = DRM_MODE_CONNECTOR_DPI, 1864 }; 1865 1866 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1867 .clock = 9000, 1868 .hdisplay = 480, 1869 .hsync_start = 480 + 2, 1870 .hsync_end = 480 + 2 + 41, 1871 .htotal = 480 + 2 + 41 + 2, 1872 .vdisplay = 272, 1873 .vsync_start = 272 + 2, 1874 .vsync_end = 272 + 2 + 10, 1875 .vtotal = 272 + 2 + 10 + 2, 1876 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1877 }; 1878 1879 static const struct panel_desc edt_etm0430g0dh6 = { 1880 .modes = &edt_etm0430g0dh6_mode, 1881 .num_modes = 1, 1882 .bpc = 6, 1883 .size = { 1884 .width = 95, 1885 .height = 54, 1886 }, 1887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1888 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1889 .connector_type = DRM_MODE_CONNECTOR_DPI, 1890 }; 1891 1892 static const struct drm_display_mode edt_et057090dhu_mode = { 1893 .clock = 25175, 1894 .hdisplay = 640, 1895 .hsync_start = 640 + 16, 1896 .hsync_end = 640 + 16 + 30, 1897 .htotal = 640 + 16 + 30 + 114, 1898 .vdisplay = 480, 1899 .vsync_start = 480 + 10, 1900 .vsync_end = 480 + 10 + 3, 1901 .vtotal = 480 + 10 + 3 + 32, 1902 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1903 }; 1904 1905 static const struct panel_desc edt_et057090dhu = { 1906 .modes = &edt_et057090dhu_mode, 1907 .num_modes = 1, 1908 .bpc = 6, 1909 .size = { 1910 .width = 115, 1911 .height = 86, 1912 }, 1913 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1914 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1915 .connector_type = DRM_MODE_CONNECTOR_DPI, 1916 }; 1917 1918 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 1919 .clock = 33260, 1920 .hdisplay = 800, 1921 .hsync_start = 800 + 40, 1922 .hsync_end = 800 + 40 + 128, 1923 .htotal = 800 + 40 + 128 + 88, 1924 .vdisplay = 480, 1925 .vsync_start = 480 + 10, 1926 .vsync_end = 480 + 10 + 2, 1927 .vtotal = 480 + 10 + 2 + 33, 1928 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1929 }; 1930 1931 static const struct panel_desc edt_etm0700g0dh6 = { 1932 .modes = &edt_etm0700g0dh6_mode, 1933 .num_modes = 1, 1934 .bpc = 6, 1935 .size = { 1936 .width = 152, 1937 .height = 91, 1938 }, 1939 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1940 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1941 .connector_type = DRM_MODE_CONNECTOR_DPI, 1942 }; 1943 1944 static const struct panel_desc edt_etm0700g0bdh6 = { 1945 .modes = &edt_etm0700g0dh6_mode, 1946 .num_modes = 1, 1947 .bpc = 6, 1948 .size = { 1949 .width = 152, 1950 .height = 91, 1951 }, 1952 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1953 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1954 .connector_type = DRM_MODE_CONNECTOR_DPI, 1955 }; 1956 1957 static const struct display_timing edt_etml0700y5dha_timing = { 1958 .pixelclock = { 40800000, 51200000, 67200000 }, 1959 .hactive = { 1024, 1024, 1024 }, 1960 .hfront_porch = { 30, 106, 125 }, 1961 .hback_porch = { 30, 106, 125 }, 1962 .hsync_len = { 30, 108, 126 }, 1963 .vactive = { 600, 600, 600 }, 1964 .vfront_porch = { 3, 12, 67}, 1965 .vback_porch = { 3, 12, 67 }, 1966 .vsync_len = { 4, 11, 66 }, 1967 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 1968 DISPLAY_FLAGS_DE_HIGH, 1969 }; 1970 1971 static const struct panel_desc edt_etml0700y5dha = { 1972 .timings = &edt_etml0700y5dha_timing, 1973 .num_timings = 1, 1974 .bpc = 8, 1975 .size = { 1976 .width = 155, 1977 .height = 86, 1978 }, 1979 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1980 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1981 }; 1982 1983 static const struct display_timing edt_etml1010g3dra_timing = { 1984 .pixelclock = { 66300000, 72400000, 78900000 }, 1985 .hactive = { 1280, 1280, 1280 }, 1986 .hfront_porch = { 12, 72, 132 }, 1987 .hback_porch = { 86, 86, 86 }, 1988 .hsync_len = { 2, 2, 2 }, 1989 .vactive = { 800, 800, 800 }, 1990 .vfront_porch = { 1, 15, 49 }, 1991 .vback_porch = { 21, 21, 21 }, 1992 .vsync_len = { 2, 2, 2 }, 1993 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 1994 DISPLAY_FLAGS_DE_HIGH, 1995 }; 1996 1997 static const struct panel_desc edt_etml1010g3dra = { 1998 .timings = &edt_etml1010g3dra_timing, 1999 .num_timings = 1, 2000 .bpc = 8, 2001 .size = { 2002 .width = 216, 2003 .height = 135, 2004 }, 2005 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2006 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2007 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2008 }; 2009 2010 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2011 .clock = 25175, 2012 .hdisplay = 640, 2013 .hsync_start = 640, 2014 .hsync_end = 640 + 16, 2015 .htotal = 640 + 16 + 30 + 114, 2016 .vdisplay = 480, 2017 .vsync_start = 480 + 10, 2018 .vsync_end = 480 + 10 + 3, 2019 .vtotal = 480 + 10 + 3 + 35, 2020 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2021 }; 2022 2023 static const struct panel_desc edt_etmv570g2dhu = { 2024 .modes = &edt_etmv570g2dhu_mode, 2025 .num_modes = 1, 2026 .bpc = 6, 2027 .size = { 2028 .width = 115, 2029 .height = 86, 2030 }, 2031 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2032 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2033 .connector_type = DRM_MODE_CONNECTOR_DPI, 2034 }; 2035 2036 static const struct display_timing eink_vb3300_kca_timing = { 2037 .pixelclock = { 40000000, 40000000, 40000000 }, 2038 .hactive = { 334, 334, 334 }, 2039 .hfront_porch = { 1, 1, 1 }, 2040 .hback_porch = { 1, 1, 1 }, 2041 .hsync_len = { 1, 1, 1 }, 2042 .vactive = { 1405, 1405, 1405 }, 2043 .vfront_porch = { 1, 1, 1 }, 2044 .vback_porch = { 1, 1, 1 }, 2045 .vsync_len = { 1, 1, 1 }, 2046 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2047 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2048 }; 2049 2050 static const struct panel_desc eink_vb3300_kca = { 2051 .timings = &eink_vb3300_kca_timing, 2052 .num_timings = 1, 2053 .bpc = 6, 2054 .size = { 2055 .width = 157, 2056 .height = 209, 2057 }, 2058 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2059 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2060 .connector_type = DRM_MODE_CONNECTOR_DPI, 2061 }; 2062 2063 static const struct display_timing evervision_vgg644804_timing = { 2064 .pixelclock = { 25175000, 25175000, 25175000 }, 2065 .hactive = { 640, 640, 640 }, 2066 .hfront_porch = { 16, 16, 16 }, 2067 .hback_porch = { 82, 114, 170 }, 2068 .hsync_len = { 5, 30, 30 }, 2069 .vactive = { 480, 480, 480 }, 2070 .vfront_porch = { 10, 10, 10 }, 2071 .vback_porch = { 30, 32, 34 }, 2072 .vsync_len = { 1, 3, 5 }, 2073 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2074 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2075 DISPLAY_FLAGS_SYNC_POSEDGE, 2076 }; 2077 2078 static const struct panel_desc evervision_vgg644804 = { 2079 .timings = &evervision_vgg644804_timing, 2080 .num_timings = 1, 2081 .bpc = 8, 2082 .size = { 2083 .width = 115, 2084 .height = 86, 2085 }, 2086 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2087 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2088 }; 2089 2090 static const struct display_timing evervision_vgg804821_timing = { 2091 .pixelclock = { 27600000, 33300000, 50000000 }, 2092 .hactive = { 800, 800, 800 }, 2093 .hfront_porch = { 40, 66, 70 }, 2094 .hback_porch = { 40, 67, 70 }, 2095 .hsync_len = { 40, 67, 70 }, 2096 .vactive = { 480, 480, 480 }, 2097 .vfront_porch = { 6, 10, 10 }, 2098 .vback_porch = { 7, 11, 11 }, 2099 .vsync_len = { 7, 11, 11 }, 2100 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2101 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2102 DISPLAY_FLAGS_SYNC_NEGEDGE, 2103 }; 2104 2105 static const struct panel_desc evervision_vgg804821 = { 2106 .timings = &evervision_vgg804821_timing, 2107 .num_timings = 1, 2108 .bpc = 8, 2109 .size = { 2110 .width = 108, 2111 .height = 64, 2112 }, 2113 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2114 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2115 }; 2116 2117 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2118 .clock = 32260, 2119 .hdisplay = 800, 2120 .hsync_start = 800 + 168, 2121 .hsync_end = 800 + 168 + 64, 2122 .htotal = 800 + 168 + 64 + 88, 2123 .vdisplay = 480, 2124 .vsync_start = 480 + 37, 2125 .vsync_end = 480 + 37 + 2, 2126 .vtotal = 480 + 37 + 2 + 8, 2127 }; 2128 2129 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2130 .modes = &foxlink_fl500wvr00_a0t_mode, 2131 .num_modes = 1, 2132 .bpc = 8, 2133 .size = { 2134 .width = 108, 2135 .height = 65, 2136 }, 2137 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2138 }; 2139 2140 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2141 { /* 60 Hz */ 2142 .clock = 6000, 2143 .hdisplay = 320, 2144 .hsync_start = 320 + 44, 2145 .hsync_end = 320 + 44 + 16, 2146 .htotal = 320 + 44 + 16 + 20, 2147 .vdisplay = 240, 2148 .vsync_start = 240 + 2, 2149 .vsync_end = 240 + 2 + 6, 2150 .vtotal = 240 + 2 + 6 + 2, 2151 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2152 }, 2153 { /* 50 Hz */ 2154 .clock = 5400, 2155 .hdisplay = 320, 2156 .hsync_start = 320 + 56, 2157 .hsync_end = 320 + 56 + 16, 2158 .htotal = 320 + 56 + 16 + 40, 2159 .vdisplay = 240, 2160 .vsync_start = 240 + 2, 2161 .vsync_end = 240 + 2 + 6, 2162 .vtotal = 240 + 2 + 6 + 2, 2163 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2164 }, 2165 }; 2166 2167 static const struct panel_desc frida_frd350h54004 = { 2168 .modes = frida_frd350h54004_modes, 2169 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2170 .bpc = 8, 2171 .size = { 2172 .width = 77, 2173 .height = 64, 2174 }, 2175 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2176 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2177 .connector_type = DRM_MODE_CONNECTOR_DPI, 2178 }; 2179 2180 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2181 .clock = 67185, 2182 .hdisplay = 800, 2183 .hsync_start = 800 + 20, 2184 .hsync_end = 800 + 20 + 24, 2185 .htotal = 800 + 20 + 24 + 20, 2186 .vdisplay = 1280, 2187 .vsync_start = 1280 + 4, 2188 .vsync_end = 1280 + 4 + 8, 2189 .vtotal = 1280 + 4 + 8 + 4, 2190 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2191 }; 2192 2193 static const struct panel_desc friendlyarm_hd702e = { 2194 .modes = &friendlyarm_hd702e_mode, 2195 .num_modes = 1, 2196 .size = { 2197 .width = 94, 2198 .height = 151, 2199 }, 2200 }; 2201 2202 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2203 .clock = 9000, 2204 .hdisplay = 480, 2205 .hsync_start = 480 + 5, 2206 .hsync_end = 480 + 5 + 1, 2207 .htotal = 480 + 5 + 1 + 40, 2208 .vdisplay = 272, 2209 .vsync_start = 272 + 8, 2210 .vsync_end = 272 + 8 + 1, 2211 .vtotal = 272 + 8 + 1 + 8, 2212 }; 2213 2214 static const struct panel_desc giantplus_gpg482739qs5 = { 2215 .modes = &giantplus_gpg482739qs5_mode, 2216 .num_modes = 1, 2217 .bpc = 8, 2218 .size = { 2219 .width = 95, 2220 .height = 54, 2221 }, 2222 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2223 }; 2224 2225 static const struct display_timing giantplus_gpm940b0_timing = { 2226 .pixelclock = { 13500000, 27000000, 27500000 }, 2227 .hactive = { 320, 320, 320 }, 2228 .hfront_porch = { 14, 686, 718 }, 2229 .hback_porch = { 50, 70, 255 }, 2230 .hsync_len = { 1, 1, 1 }, 2231 .vactive = { 240, 240, 240 }, 2232 .vfront_porch = { 1, 1, 179 }, 2233 .vback_porch = { 1, 21, 31 }, 2234 .vsync_len = { 1, 1, 6 }, 2235 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2236 }; 2237 2238 static const struct panel_desc giantplus_gpm940b0 = { 2239 .timings = &giantplus_gpm940b0_timing, 2240 .num_timings = 1, 2241 .bpc = 8, 2242 .size = { 2243 .width = 60, 2244 .height = 45, 2245 }, 2246 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2247 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2248 }; 2249 2250 static const struct display_timing hannstar_hsd070pww1_timing = { 2251 .pixelclock = { 64300000, 71100000, 82000000 }, 2252 .hactive = { 1280, 1280, 1280 }, 2253 .hfront_porch = { 1, 1, 10 }, 2254 .hback_porch = { 1, 1, 10 }, 2255 /* 2256 * According to the data sheet, the minimum horizontal blanking interval 2257 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2258 * minimum working horizontal blanking interval to be 60 clocks. 2259 */ 2260 .hsync_len = { 58, 158, 661 }, 2261 .vactive = { 800, 800, 800 }, 2262 .vfront_porch = { 1, 1, 10 }, 2263 .vback_porch = { 1, 1, 10 }, 2264 .vsync_len = { 1, 21, 203 }, 2265 .flags = DISPLAY_FLAGS_DE_HIGH, 2266 }; 2267 2268 static const struct panel_desc hannstar_hsd070pww1 = { 2269 .timings = &hannstar_hsd070pww1_timing, 2270 .num_timings = 1, 2271 .bpc = 6, 2272 .size = { 2273 .width = 151, 2274 .height = 94, 2275 }, 2276 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2277 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2278 }; 2279 2280 static const struct display_timing hannstar_hsd100pxn1_timing = { 2281 .pixelclock = { 55000000, 65000000, 75000000 }, 2282 .hactive = { 1024, 1024, 1024 }, 2283 .hfront_porch = { 40, 40, 40 }, 2284 .hback_porch = { 220, 220, 220 }, 2285 .hsync_len = { 20, 60, 100 }, 2286 .vactive = { 768, 768, 768 }, 2287 .vfront_porch = { 7, 7, 7 }, 2288 .vback_porch = { 21, 21, 21 }, 2289 .vsync_len = { 10, 10, 10 }, 2290 .flags = DISPLAY_FLAGS_DE_HIGH, 2291 }; 2292 2293 static const struct panel_desc hannstar_hsd100pxn1 = { 2294 .timings = &hannstar_hsd100pxn1_timing, 2295 .num_timings = 1, 2296 .bpc = 6, 2297 .size = { 2298 .width = 203, 2299 .height = 152, 2300 }, 2301 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2302 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2303 }; 2304 2305 static const struct display_timing hannstar_hsd101pww2_timing = { 2306 .pixelclock = { 64300000, 71100000, 82000000 }, 2307 .hactive = { 1280, 1280, 1280 }, 2308 .hfront_porch = { 1, 1, 10 }, 2309 .hback_porch = { 1, 1, 10 }, 2310 .hsync_len = { 58, 158, 661 }, 2311 .vactive = { 800, 800, 800 }, 2312 .vfront_porch = { 1, 1, 10 }, 2313 .vback_porch = { 1, 1, 10 }, 2314 .vsync_len = { 1, 21, 203 }, 2315 .flags = DISPLAY_FLAGS_DE_HIGH, 2316 }; 2317 2318 static const struct panel_desc hannstar_hsd101pww2 = { 2319 .timings = &hannstar_hsd101pww2_timing, 2320 .num_timings = 1, 2321 .bpc = 8, 2322 .size = { 2323 .width = 217, 2324 .height = 136, 2325 }, 2326 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2327 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2328 }; 2329 2330 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2331 .clock = 33333, 2332 .hdisplay = 800, 2333 .hsync_start = 800 + 85, 2334 .hsync_end = 800 + 85 + 86, 2335 .htotal = 800 + 85 + 86 + 85, 2336 .vdisplay = 480, 2337 .vsync_start = 480 + 16, 2338 .vsync_end = 480 + 16 + 13, 2339 .vtotal = 480 + 16 + 13 + 16, 2340 }; 2341 2342 static const struct panel_desc hitachi_tx23d38vm0caa = { 2343 .modes = &hitachi_tx23d38vm0caa_mode, 2344 .num_modes = 1, 2345 .bpc = 6, 2346 .size = { 2347 .width = 195, 2348 .height = 117, 2349 }, 2350 .delay = { 2351 .enable = 160, 2352 .disable = 160, 2353 }, 2354 }; 2355 2356 static const struct drm_display_mode innolux_at043tn24_mode = { 2357 .clock = 9000, 2358 .hdisplay = 480, 2359 .hsync_start = 480 + 2, 2360 .hsync_end = 480 + 2 + 41, 2361 .htotal = 480 + 2 + 41 + 2, 2362 .vdisplay = 272, 2363 .vsync_start = 272 + 2, 2364 .vsync_end = 272 + 2 + 10, 2365 .vtotal = 272 + 2 + 10 + 2, 2366 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2367 }; 2368 2369 static const struct panel_desc innolux_at043tn24 = { 2370 .modes = &innolux_at043tn24_mode, 2371 .num_modes = 1, 2372 .bpc = 8, 2373 .size = { 2374 .width = 95, 2375 .height = 54, 2376 }, 2377 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2378 .connector_type = DRM_MODE_CONNECTOR_DPI, 2379 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2380 }; 2381 2382 static const struct drm_display_mode innolux_at070tn92_mode = { 2383 .clock = 33333, 2384 .hdisplay = 800, 2385 .hsync_start = 800 + 210, 2386 .hsync_end = 800 + 210 + 20, 2387 .htotal = 800 + 210 + 20 + 46, 2388 .vdisplay = 480, 2389 .vsync_start = 480 + 22, 2390 .vsync_end = 480 + 22 + 10, 2391 .vtotal = 480 + 22 + 23 + 10, 2392 }; 2393 2394 static const struct panel_desc innolux_at070tn92 = { 2395 .modes = &innolux_at070tn92_mode, 2396 .num_modes = 1, 2397 .size = { 2398 .width = 154, 2399 .height = 86, 2400 }, 2401 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2402 }; 2403 2404 static const struct display_timing innolux_g070ace_l01_timing = { 2405 .pixelclock = { 25200000, 35000000, 35700000 }, 2406 .hactive = { 800, 800, 800 }, 2407 .hfront_porch = { 30, 32, 87 }, 2408 .hback_porch = { 30, 32, 87 }, 2409 .hsync_len = { 1, 1, 1 }, 2410 .vactive = { 480, 480, 480 }, 2411 .vfront_porch = { 3, 3, 3 }, 2412 .vback_porch = { 13, 13, 13 }, 2413 .vsync_len = { 1, 1, 4 }, 2414 .flags = DISPLAY_FLAGS_DE_HIGH, 2415 }; 2416 2417 static const struct panel_desc innolux_g070ace_l01 = { 2418 .timings = &innolux_g070ace_l01_timing, 2419 .num_timings = 1, 2420 .bpc = 8, 2421 .size = { 2422 .width = 152, 2423 .height = 91, 2424 }, 2425 .delay = { 2426 .prepare = 10, 2427 .enable = 50, 2428 .disable = 50, 2429 .unprepare = 500, 2430 }, 2431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2432 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2433 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2434 }; 2435 2436 static const struct display_timing innolux_g070y2_l01_timing = { 2437 .pixelclock = { 28000000, 29500000, 32000000 }, 2438 .hactive = { 800, 800, 800 }, 2439 .hfront_porch = { 61, 91, 141 }, 2440 .hback_porch = { 60, 90, 140 }, 2441 .hsync_len = { 12, 12, 12 }, 2442 .vactive = { 480, 480, 480 }, 2443 .vfront_porch = { 4, 9, 30 }, 2444 .vback_porch = { 4, 8, 28 }, 2445 .vsync_len = { 2, 2, 2 }, 2446 .flags = DISPLAY_FLAGS_DE_HIGH, 2447 }; 2448 2449 static const struct panel_desc innolux_g070y2_l01 = { 2450 .timings = &innolux_g070y2_l01_timing, 2451 .num_timings = 1, 2452 .bpc = 8, 2453 .size = { 2454 .width = 152, 2455 .height = 91, 2456 }, 2457 .delay = { 2458 .prepare = 10, 2459 .enable = 100, 2460 .disable = 100, 2461 .unprepare = 800, 2462 }, 2463 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2464 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2465 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2466 }; 2467 2468 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2469 .clock = 33333, 2470 .hdisplay = 800, 2471 .hsync_start = 800 + 210, 2472 .hsync_end = 800 + 210 + 20, 2473 .htotal = 800 + 210 + 20 + 46, 2474 .vdisplay = 480, 2475 .vsync_start = 480 + 22, 2476 .vsync_end = 480 + 22 + 10, 2477 .vtotal = 480 + 22 + 23 + 10, 2478 }; 2479 2480 static const struct panel_desc innolux_g070y2_t02 = { 2481 .modes = &innolux_g070y2_t02_mode, 2482 .num_modes = 1, 2483 .bpc = 8, 2484 .size = { 2485 .width = 152, 2486 .height = 92, 2487 }, 2488 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2489 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2490 .connector_type = DRM_MODE_CONNECTOR_DPI, 2491 }; 2492 2493 static const struct display_timing innolux_g101ice_l01_timing = { 2494 .pixelclock = { 60400000, 71100000, 74700000 }, 2495 .hactive = { 1280, 1280, 1280 }, 2496 .hfront_porch = { 30, 60, 70 }, 2497 .hback_porch = { 30, 60, 70 }, 2498 .hsync_len = { 22, 40, 60 }, 2499 .vactive = { 800, 800, 800 }, 2500 .vfront_porch = { 3, 8, 14 }, 2501 .vback_porch = { 3, 8, 14 }, 2502 .vsync_len = { 4, 7, 12 }, 2503 .flags = DISPLAY_FLAGS_DE_HIGH, 2504 }; 2505 2506 static const struct panel_desc innolux_g101ice_l01 = { 2507 .timings = &innolux_g101ice_l01_timing, 2508 .num_timings = 1, 2509 .bpc = 8, 2510 .size = { 2511 .width = 217, 2512 .height = 135, 2513 }, 2514 .delay = { 2515 .enable = 200, 2516 .disable = 200, 2517 }, 2518 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2519 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2520 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2521 }; 2522 2523 static const struct display_timing innolux_g121i1_l01_timing = { 2524 .pixelclock = { 67450000, 71000000, 74550000 }, 2525 .hactive = { 1280, 1280, 1280 }, 2526 .hfront_porch = { 40, 80, 160 }, 2527 .hback_porch = { 39, 79, 159 }, 2528 .hsync_len = { 1, 1, 1 }, 2529 .vactive = { 800, 800, 800 }, 2530 .vfront_porch = { 5, 11, 100 }, 2531 .vback_porch = { 4, 11, 99 }, 2532 .vsync_len = { 1, 1, 1 }, 2533 }; 2534 2535 static const struct panel_desc innolux_g121i1_l01 = { 2536 .timings = &innolux_g121i1_l01_timing, 2537 .num_timings = 1, 2538 .bpc = 6, 2539 .size = { 2540 .width = 261, 2541 .height = 163, 2542 }, 2543 .delay = { 2544 .enable = 200, 2545 .disable = 20, 2546 }, 2547 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2548 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2549 }; 2550 2551 static const struct drm_display_mode innolux_g121x1_l03_mode = { 2552 .clock = 65000, 2553 .hdisplay = 1024, 2554 .hsync_start = 1024 + 0, 2555 .hsync_end = 1024 + 1, 2556 .htotal = 1024 + 0 + 1 + 320, 2557 .vdisplay = 768, 2558 .vsync_start = 768 + 38, 2559 .vsync_end = 768 + 38 + 1, 2560 .vtotal = 768 + 38 + 1 + 0, 2561 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2562 }; 2563 2564 static const struct panel_desc innolux_g121x1_l03 = { 2565 .modes = &innolux_g121x1_l03_mode, 2566 .num_modes = 1, 2567 .bpc = 6, 2568 .size = { 2569 .width = 246, 2570 .height = 185, 2571 }, 2572 .delay = { 2573 .enable = 200, 2574 .unprepare = 200, 2575 .disable = 400, 2576 }, 2577 }; 2578 2579 static const struct display_timing innolux_g156hce_l01_timings = { 2580 .pixelclock = { 120000000, 141860000, 150000000 }, 2581 .hactive = { 1920, 1920, 1920 }, 2582 .hfront_porch = { 80, 90, 100 }, 2583 .hback_porch = { 80, 90, 100 }, 2584 .hsync_len = { 20, 30, 30 }, 2585 .vactive = { 1080, 1080, 1080 }, 2586 .vfront_porch = { 3, 10, 20 }, 2587 .vback_porch = { 3, 10, 20 }, 2588 .vsync_len = { 4, 10, 10 }, 2589 }; 2590 2591 static const struct panel_desc innolux_g156hce_l01 = { 2592 .timings = &innolux_g156hce_l01_timings, 2593 .num_timings = 1, 2594 .bpc = 8, 2595 .size = { 2596 .width = 344, 2597 .height = 194, 2598 }, 2599 .delay = { 2600 .prepare = 1, /* T1+T2 */ 2601 .enable = 450, /* T5 */ 2602 .disable = 200, /* T6 */ 2603 .unprepare = 10, /* T3+T7 */ 2604 }, 2605 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2606 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2607 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2608 }; 2609 2610 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2611 .clock = 69300, 2612 .hdisplay = 1366, 2613 .hsync_start = 1366 + 16, 2614 .hsync_end = 1366 + 16 + 34, 2615 .htotal = 1366 + 16 + 34 + 50, 2616 .vdisplay = 768, 2617 .vsync_start = 768 + 2, 2618 .vsync_end = 768 + 2 + 6, 2619 .vtotal = 768 + 2 + 6 + 12, 2620 }; 2621 2622 static const struct panel_desc innolux_n156bge_l21 = { 2623 .modes = &innolux_n156bge_l21_mode, 2624 .num_modes = 1, 2625 .bpc = 6, 2626 .size = { 2627 .width = 344, 2628 .height = 193, 2629 }, 2630 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2631 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2632 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2633 }; 2634 2635 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2636 .clock = 51501, 2637 .hdisplay = 1024, 2638 .hsync_start = 1024 + 128, 2639 .hsync_end = 1024 + 128 + 64, 2640 .htotal = 1024 + 128 + 64 + 128, 2641 .vdisplay = 600, 2642 .vsync_start = 600 + 16, 2643 .vsync_end = 600 + 16 + 4, 2644 .vtotal = 600 + 16 + 4 + 16, 2645 }; 2646 2647 static const struct panel_desc innolux_zj070na_01p = { 2648 .modes = &innolux_zj070na_01p_mode, 2649 .num_modes = 1, 2650 .bpc = 6, 2651 .size = { 2652 .width = 154, 2653 .height = 90, 2654 }, 2655 }; 2656 2657 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2658 .pixelclock = { 5580000, 5850000, 6200000 }, 2659 .hactive = { 320, 320, 320 }, 2660 .hfront_porch = { 30, 30, 30 }, 2661 .hback_porch = { 30, 30, 30 }, 2662 .hsync_len = { 1, 5, 17 }, 2663 .vactive = { 240, 240, 240 }, 2664 .vfront_porch = { 6, 6, 6 }, 2665 .vback_porch = { 5, 5, 5 }, 2666 .vsync_len = { 1, 2, 11 }, 2667 .flags = DISPLAY_FLAGS_DE_HIGH, 2668 }; 2669 2670 static const struct panel_desc koe_tx14d24vm1bpa = { 2671 .timings = &koe_tx14d24vm1bpa_timing, 2672 .num_timings = 1, 2673 .bpc = 6, 2674 .size = { 2675 .width = 115, 2676 .height = 86, 2677 }, 2678 }; 2679 2680 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2681 .pixelclock = { 151820000, 156720000, 159780000 }, 2682 .hactive = { 1920, 1920, 1920 }, 2683 .hfront_porch = { 105, 130, 142 }, 2684 .hback_porch = { 45, 70, 82 }, 2685 .hsync_len = { 30, 30, 30 }, 2686 .vactive = { 1200, 1200, 1200}, 2687 .vfront_porch = { 3, 5, 10 }, 2688 .vback_porch = { 2, 5, 10 }, 2689 .vsync_len = { 5, 5, 5 }, 2690 }; 2691 2692 static const struct panel_desc koe_tx26d202vm0bwa = { 2693 .timings = &koe_tx26d202vm0bwa_timing, 2694 .num_timings = 1, 2695 .bpc = 8, 2696 .size = { 2697 .width = 217, 2698 .height = 136, 2699 }, 2700 .delay = { 2701 .prepare = 1000, 2702 .enable = 1000, 2703 .unprepare = 1000, 2704 .disable = 1000, 2705 }, 2706 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2707 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2708 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2709 }; 2710 2711 static const struct display_timing koe_tx31d200vm0baa_timing = { 2712 .pixelclock = { 39600000, 43200000, 48000000 }, 2713 .hactive = { 1280, 1280, 1280 }, 2714 .hfront_porch = { 16, 36, 56 }, 2715 .hback_porch = { 16, 36, 56 }, 2716 .hsync_len = { 8, 8, 8 }, 2717 .vactive = { 480, 480, 480 }, 2718 .vfront_porch = { 6, 21, 33 }, 2719 .vback_porch = { 6, 21, 33 }, 2720 .vsync_len = { 8, 8, 8 }, 2721 .flags = DISPLAY_FLAGS_DE_HIGH, 2722 }; 2723 2724 static const struct panel_desc koe_tx31d200vm0baa = { 2725 .timings = &koe_tx31d200vm0baa_timing, 2726 .num_timings = 1, 2727 .bpc = 6, 2728 .size = { 2729 .width = 292, 2730 .height = 109, 2731 }, 2732 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2733 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2734 }; 2735 2736 static const struct display_timing kyo_tcg121xglp_timing = { 2737 .pixelclock = { 52000000, 65000000, 71000000 }, 2738 .hactive = { 1024, 1024, 1024 }, 2739 .hfront_porch = { 2, 2, 2 }, 2740 .hback_porch = { 2, 2, 2 }, 2741 .hsync_len = { 86, 124, 244 }, 2742 .vactive = { 768, 768, 768 }, 2743 .vfront_porch = { 2, 2, 2 }, 2744 .vback_porch = { 2, 2, 2 }, 2745 .vsync_len = { 6, 34, 73 }, 2746 .flags = DISPLAY_FLAGS_DE_HIGH, 2747 }; 2748 2749 static const struct panel_desc kyo_tcg121xglp = { 2750 .timings = &kyo_tcg121xglp_timing, 2751 .num_timings = 1, 2752 .bpc = 8, 2753 .size = { 2754 .width = 246, 2755 .height = 184, 2756 }, 2757 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2758 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2759 }; 2760 2761 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2762 .clock = 7000, 2763 .hdisplay = 320, 2764 .hsync_start = 320 + 20, 2765 .hsync_end = 320 + 20 + 30, 2766 .htotal = 320 + 20 + 30 + 38, 2767 .vdisplay = 240, 2768 .vsync_start = 240 + 4, 2769 .vsync_end = 240 + 4 + 3, 2770 .vtotal = 240 + 4 + 3 + 15, 2771 }; 2772 2773 static const struct panel_desc lemaker_bl035_rgb_002 = { 2774 .modes = &lemaker_bl035_rgb_002_mode, 2775 .num_modes = 1, 2776 .size = { 2777 .width = 70, 2778 .height = 52, 2779 }, 2780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2781 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2782 }; 2783 2784 static const struct display_timing lg_lb070wv8_timing = { 2785 .pixelclock = { 31950000, 33260000, 34600000 }, 2786 .hactive = { 800, 800, 800 }, 2787 .hfront_porch = { 88, 88, 88 }, 2788 .hback_porch = { 88, 88, 88 }, 2789 .hsync_len = { 80, 80, 80 }, 2790 .vactive = { 480, 480, 480 }, 2791 .vfront_porch = { 10, 10, 10 }, 2792 .vback_porch = { 10, 10, 10 }, 2793 .vsync_len = { 25, 25, 25 }, 2794 }; 2795 2796 static const struct panel_desc lg_lb070wv8 = { 2797 .timings = &lg_lb070wv8_timing, 2798 .num_timings = 1, 2799 .bpc = 8, 2800 .size = { 2801 .width = 151, 2802 .height = 91, 2803 }, 2804 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2806 }; 2807 2808 static const struct display_timing logictechno_lt161010_2nh_timing = { 2809 .pixelclock = { 26400000, 33300000, 46800000 }, 2810 .hactive = { 800, 800, 800 }, 2811 .hfront_porch = { 16, 210, 354 }, 2812 .hback_porch = { 46, 46, 46 }, 2813 .hsync_len = { 1, 20, 40 }, 2814 .vactive = { 480, 480, 480 }, 2815 .vfront_porch = { 7, 22, 147 }, 2816 .vback_porch = { 23, 23, 23 }, 2817 .vsync_len = { 1, 10, 20 }, 2818 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2819 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2820 DISPLAY_FLAGS_SYNC_POSEDGE, 2821 }; 2822 2823 static const struct panel_desc logictechno_lt161010_2nh = { 2824 .timings = &logictechno_lt161010_2nh_timing, 2825 .num_timings = 1, 2826 .bpc = 6, 2827 .size = { 2828 .width = 154, 2829 .height = 86, 2830 }, 2831 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2832 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 2833 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 2834 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 2835 .connector_type = DRM_MODE_CONNECTOR_DPI, 2836 }; 2837 2838 static const struct display_timing logictechno_lt170410_2whc_timing = { 2839 .pixelclock = { 68900000, 71100000, 73400000 }, 2840 .hactive = { 1280, 1280, 1280 }, 2841 .hfront_porch = { 23, 60, 71 }, 2842 .hback_porch = { 23, 60, 71 }, 2843 .hsync_len = { 15, 40, 47 }, 2844 .vactive = { 800, 800, 800 }, 2845 .vfront_porch = { 5, 7, 10 }, 2846 .vback_porch = { 5, 7, 10 }, 2847 .vsync_len = { 6, 9, 12 }, 2848 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2849 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2850 DISPLAY_FLAGS_SYNC_POSEDGE, 2851 }; 2852 2853 static const struct panel_desc logictechno_lt170410_2whc = { 2854 .timings = &logictechno_lt170410_2whc_timing, 2855 .num_timings = 1, 2856 .bpc = 8, 2857 .size = { 2858 .width = 217, 2859 .height = 136, 2860 }, 2861 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2862 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2863 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2864 }; 2865 2866 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 2867 .clock = 33000, 2868 .hdisplay = 800, 2869 .hsync_start = 800 + 112, 2870 .hsync_end = 800 + 112 + 3, 2871 .htotal = 800 + 112 + 3 + 85, 2872 .vdisplay = 480, 2873 .vsync_start = 480 + 38, 2874 .vsync_end = 480 + 38 + 3, 2875 .vtotal = 480 + 38 + 3 + 29, 2876 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2877 }; 2878 2879 static const struct panel_desc logictechno_lttd800480070_l2rt = { 2880 .modes = &logictechno_lttd800480070_l2rt_mode, 2881 .num_modes = 1, 2882 .bpc = 8, 2883 .size = { 2884 .width = 154, 2885 .height = 86, 2886 }, 2887 .delay = { 2888 .prepare = 45, 2889 .enable = 100, 2890 .disable = 100, 2891 .unprepare = 45 2892 }, 2893 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2894 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2895 .connector_type = DRM_MODE_CONNECTOR_DPI, 2896 }; 2897 2898 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 2899 .clock = 33000, 2900 .hdisplay = 800, 2901 .hsync_start = 800 + 154, 2902 .hsync_end = 800 + 154 + 3, 2903 .htotal = 800 + 154 + 3 + 43, 2904 .vdisplay = 480, 2905 .vsync_start = 480 + 47, 2906 .vsync_end = 480 + 47 + 3, 2907 .vtotal = 480 + 47 + 3 + 20, 2908 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2909 }; 2910 2911 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 2912 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 2913 .num_modes = 1, 2914 .bpc = 8, 2915 .size = { 2916 .width = 154, 2917 .height = 86, 2918 }, 2919 .delay = { 2920 .prepare = 45, 2921 .enable = 100, 2922 .disable = 100, 2923 .unprepare = 45 2924 }, 2925 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2926 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2927 .connector_type = DRM_MODE_CONNECTOR_DPI, 2928 }; 2929 2930 static const struct drm_display_mode logicpd_type_28_mode = { 2931 .clock = 9107, 2932 .hdisplay = 480, 2933 .hsync_start = 480 + 3, 2934 .hsync_end = 480 + 3 + 42, 2935 .htotal = 480 + 3 + 42 + 2, 2936 2937 .vdisplay = 272, 2938 .vsync_start = 272 + 2, 2939 .vsync_end = 272 + 2 + 11, 2940 .vtotal = 272 + 2 + 11 + 3, 2941 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 2942 }; 2943 2944 static const struct panel_desc logicpd_type_28 = { 2945 .modes = &logicpd_type_28_mode, 2946 .num_modes = 1, 2947 .bpc = 8, 2948 .size = { 2949 .width = 105, 2950 .height = 67, 2951 }, 2952 .delay = { 2953 .prepare = 200, 2954 .enable = 200, 2955 .unprepare = 200, 2956 .disable = 200, 2957 }, 2958 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2959 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 2960 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 2961 .connector_type = DRM_MODE_CONNECTOR_DPI, 2962 }; 2963 2964 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 2965 .clock = 30400, 2966 .hdisplay = 800, 2967 .hsync_start = 800 + 0, 2968 .hsync_end = 800 + 1, 2969 .htotal = 800 + 0 + 1 + 160, 2970 .vdisplay = 480, 2971 .vsync_start = 480 + 0, 2972 .vsync_end = 480 + 48 + 1, 2973 .vtotal = 480 + 48 + 1 + 0, 2974 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2975 }; 2976 2977 static const struct panel_desc mitsubishi_aa070mc01 = { 2978 .modes = &mitsubishi_aa070mc01_mode, 2979 .num_modes = 1, 2980 .bpc = 8, 2981 .size = { 2982 .width = 152, 2983 .height = 91, 2984 }, 2985 2986 .delay = { 2987 .enable = 200, 2988 .unprepare = 200, 2989 .disable = 400, 2990 }, 2991 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2992 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2993 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2994 }; 2995 2996 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 2997 .clock = 56234, 2998 .hdisplay = 1024, 2999 .hsync_start = 1024 + 24, 3000 .hsync_end = 1024 + 24 + 63, 3001 .htotal = 1024 + 24 + 63 + 1, 3002 .vdisplay = 768, 3003 .vsync_start = 768 + 3, 3004 .vsync_end = 768 + 3 + 6, 3005 .vtotal = 768 + 3 + 6 + 1, 3006 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3007 }; 3008 3009 static const struct panel_desc mitsubishi_aa084xe01 = { 3010 .modes = &mitsubishi_aa084xe01_mode, 3011 .num_modes = 1, 3012 .bpc = 8, 3013 .size = { 3014 .width = 1024, 3015 .height = 768, 3016 }, 3017 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3018 .connector_type = DRM_MODE_CONNECTOR_DPI, 3019 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3020 }; 3021 3022 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3023 .pixelclock = { 29000000, 33000000, 38000000 }, 3024 .hactive = { 800, 800, 800 }, 3025 .hfront_porch = { 180, 210, 240 }, 3026 .hback_porch = { 16, 16, 16 }, 3027 .hsync_len = { 30, 30, 30 }, 3028 .vactive = { 480, 480, 480 }, 3029 .vfront_porch = { 12, 22, 32 }, 3030 .vback_porch = { 10, 10, 10 }, 3031 .vsync_len = { 13, 13, 13 }, 3032 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3033 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3034 DISPLAY_FLAGS_SYNC_POSEDGE, 3035 }; 3036 3037 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3038 .timings = &multi_inno_mi0700s4t_6_timing, 3039 .num_timings = 1, 3040 .bpc = 8, 3041 .size = { 3042 .width = 154, 3043 .height = 86, 3044 }, 3045 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3046 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3047 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3048 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3049 .connector_type = DRM_MODE_CONNECTOR_DPI, 3050 }; 3051 3052 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3053 .pixelclock = { 32000000, 40000000, 50000000 }, 3054 .hactive = { 800, 800, 800 }, 3055 .hfront_porch = { 16, 210, 354 }, 3056 .hback_porch = { 6, 26, 45 }, 3057 .hsync_len = { 1, 20, 40 }, 3058 .vactive = { 600, 600, 600 }, 3059 .vfront_porch = { 1, 12, 77 }, 3060 .vback_porch = { 3, 13, 22 }, 3061 .vsync_len = { 1, 10, 20 }, 3062 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3063 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3064 DISPLAY_FLAGS_SYNC_POSEDGE, 3065 }; 3066 3067 static const struct panel_desc multi_inno_mi0800ft_9 = { 3068 .timings = &multi_inno_mi0800ft_9_timing, 3069 .num_timings = 1, 3070 .bpc = 8, 3071 .size = { 3072 .width = 162, 3073 .height = 122, 3074 }, 3075 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3076 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3077 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3078 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3079 .connector_type = DRM_MODE_CONNECTOR_DPI, 3080 }; 3081 3082 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3083 .pixelclock = { 68900000, 70000000, 73400000 }, 3084 .hactive = { 1280, 1280, 1280 }, 3085 .hfront_porch = { 30, 60, 71 }, 3086 .hback_porch = { 30, 60, 71 }, 3087 .hsync_len = { 10, 10, 48 }, 3088 .vactive = { 800, 800, 800 }, 3089 .vfront_porch = { 5, 10, 10 }, 3090 .vback_porch = { 5, 10, 10 }, 3091 .vsync_len = { 5, 6, 13 }, 3092 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3093 DISPLAY_FLAGS_DE_HIGH, 3094 }; 3095 3096 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3097 .timings = &multi_inno_mi1010ait_1cp_timing, 3098 .num_timings = 1, 3099 .bpc = 8, 3100 .size = { 3101 .width = 217, 3102 .height = 136, 3103 }, 3104 .delay = { 3105 .enable = 50, 3106 .disable = 50, 3107 }, 3108 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3109 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3110 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3111 }; 3112 3113 static const struct display_timing nec_nl12880bc20_05_timing = { 3114 .pixelclock = { 67000000, 71000000, 75000000 }, 3115 .hactive = { 1280, 1280, 1280 }, 3116 .hfront_porch = { 2, 30, 30 }, 3117 .hback_porch = { 6, 100, 100 }, 3118 .hsync_len = { 2, 30, 30 }, 3119 .vactive = { 800, 800, 800 }, 3120 .vfront_porch = { 5, 5, 5 }, 3121 .vback_porch = { 11, 11, 11 }, 3122 .vsync_len = { 7, 7, 7 }, 3123 }; 3124 3125 static const struct panel_desc nec_nl12880bc20_05 = { 3126 .timings = &nec_nl12880bc20_05_timing, 3127 .num_timings = 1, 3128 .bpc = 8, 3129 .size = { 3130 .width = 261, 3131 .height = 163, 3132 }, 3133 .delay = { 3134 .enable = 50, 3135 .disable = 50, 3136 }, 3137 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3138 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3139 }; 3140 3141 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3142 .clock = 10870, 3143 .hdisplay = 480, 3144 .hsync_start = 480 + 2, 3145 .hsync_end = 480 + 2 + 41, 3146 .htotal = 480 + 2 + 41 + 2, 3147 .vdisplay = 272, 3148 .vsync_start = 272 + 2, 3149 .vsync_end = 272 + 2 + 4, 3150 .vtotal = 272 + 2 + 4 + 2, 3151 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3152 }; 3153 3154 static const struct panel_desc nec_nl4827hc19_05b = { 3155 .modes = &nec_nl4827hc19_05b_mode, 3156 .num_modes = 1, 3157 .bpc = 8, 3158 .size = { 3159 .width = 95, 3160 .height = 54, 3161 }, 3162 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3163 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3164 }; 3165 3166 static const struct drm_display_mode netron_dy_e231732_mode = { 3167 .clock = 66000, 3168 .hdisplay = 1024, 3169 .hsync_start = 1024 + 160, 3170 .hsync_end = 1024 + 160 + 70, 3171 .htotal = 1024 + 160 + 70 + 90, 3172 .vdisplay = 600, 3173 .vsync_start = 600 + 127, 3174 .vsync_end = 600 + 127 + 20, 3175 .vtotal = 600 + 127 + 20 + 3, 3176 }; 3177 3178 static const struct panel_desc netron_dy_e231732 = { 3179 .modes = &netron_dy_e231732_mode, 3180 .num_modes = 1, 3181 .size = { 3182 .width = 154, 3183 .height = 87, 3184 }, 3185 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3186 }; 3187 3188 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3189 .clock = 9000, 3190 .hdisplay = 480, 3191 .hsync_start = 480 + 2, 3192 .hsync_end = 480 + 2 + 41, 3193 .htotal = 480 + 2 + 41 + 2, 3194 .vdisplay = 272, 3195 .vsync_start = 272 + 2, 3196 .vsync_end = 272 + 2 + 10, 3197 .vtotal = 272 + 2 + 10 + 2, 3198 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3199 }; 3200 3201 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3202 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3203 .num_modes = 1, 3204 .bpc = 8, 3205 .size = { 3206 .width = 95, 3207 .height = 54, 3208 }, 3209 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3210 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3211 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3212 .connector_type = DRM_MODE_CONNECTOR_DPI, 3213 }; 3214 3215 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3216 .pixelclock = { 130000000, 148350000, 163000000 }, 3217 .hactive = { 1920, 1920, 1920 }, 3218 .hfront_porch = { 80, 100, 100 }, 3219 .hback_porch = { 100, 120, 120 }, 3220 .hsync_len = { 50, 60, 60 }, 3221 .vactive = { 1080, 1080, 1080 }, 3222 .vfront_porch = { 12, 30, 30 }, 3223 .vback_porch = { 4, 10, 10 }, 3224 .vsync_len = { 4, 5, 5 }, 3225 }; 3226 3227 static const struct panel_desc nlt_nl192108ac18_02d = { 3228 .timings = &nlt_nl192108ac18_02d_timing, 3229 .num_timings = 1, 3230 .bpc = 8, 3231 .size = { 3232 .width = 344, 3233 .height = 194, 3234 }, 3235 .delay = { 3236 .unprepare = 500, 3237 }, 3238 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3239 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3240 }; 3241 3242 static const struct drm_display_mode nvd_9128_mode = { 3243 .clock = 29500, 3244 .hdisplay = 800, 3245 .hsync_start = 800 + 130, 3246 .hsync_end = 800 + 130 + 98, 3247 .htotal = 800 + 0 + 130 + 98, 3248 .vdisplay = 480, 3249 .vsync_start = 480 + 10, 3250 .vsync_end = 480 + 10 + 50, 3251 .vtotal = 480 + 0 + 10 + 50, 3252 }; 3253 3254 static const struct panel_desc nvd_9128 = { 3255 .modes = &nvd_9128_mode, 3256 .num_modes = 1, 3257 .bpc = 8, 3258 .size = { 3259 .width = 156, 3260 .height = 88, 3261 }, 3262 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3263 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3264 }; 3265 3266 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3267 .pixelclock = { 30000000, 30000000, 40000000 }, 3268 .hactive = { 800, 800, 800 }, 3269 .hfront_porch = { 40, 40, 40 }, 3270 .hback_porch = { 40, 40, 40 }, 3271 .hsync_len = { 1, 48, 48 }, 3272 .vactive = { 480, 480, 480 }, 3273 .vfront_porch = { 13, 13, 13 }, 3274 .vback_porch = { 29, 29, 29 }, 3275 .vsync_len = { 3, 3, 3 }, 3276 .flags = DISPLAY_FLAGS_DE_HIGH, 3277 }; 3278 3279 static const struct panel_desc okaya_rs800480t_7x0gp = { 3280 .timings = &okaya_rs800480t_7x0gp_timing, 3281 .num_timings = 1, 3282 .bpc = 6, 3283 .size = { 3284 .width = 154, 3285 .height = 87, 3286 }, 3287 .delay = { 3288 .prepare = 41, 3289 .enable = 50, 3290 .unprepare = 41, 3291 .disable = 50, 3292 }, 3293 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3294 }; 3295 3296 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3297 .clock = 9000, 3298 .hdisplay = 480, 3299 .hsync_start = 480 + 5, 3300 .hsync_end = 480 + 5 + 30, 3301 .htotal = 480 + 5 + 30 + 10, 3302 .vdisplay = 272, 3303 .vsync_start = 272 + 8, 3304 .vsync_end = 272 + 8 + 5, 3305 .vtotal = 272 + 8 + 5 + 3, 3306 }; 3307 3308 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3309 .modes = &olimex_lcd_olinuxino_43ts_mode, 3310 .num_modes = 1, 3311 .size = { 3312 .width = 95, 3313 .height = 54, 3314 }, 3315 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3316 }; 3317 3318 /* 3319 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3320 * pixel clocks, but this is the timing that was being used in the Adafruit 3321 * installation instructions. 3322 */ 3323 static const struct drm_display_mode ontat_yx700wv03_mode = { 3324 .clock = 29500, 3325 .hdisplay = 800, 3326 .hsync_start = 824, 3327 .hsync_end = 896, 3328 .htotal = 992, 3329 .vdisplay = 480, 3330 .vsync_start = 483, 3331 .vsync_end = 493, 3332 .vtotal = 500, 3333 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3334 }; 3335 3336 /* 3337 * Specification at: 3338 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3339 */ 3340 static const struct panel_desc ontat_yx700wv03 = { 3341 .modes = &ontat_yx700wv03_mode, 3342 .num_modes = 1, 3343 .bpc = 8, 3344 .size = { 3345 .width = 154, 3346 .height = 83, 3347 }, 3348 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3349 }; 3350 3351 static const struct drm_display_mode ortustech_com37h3m_mode = { 3352 .clock = 22230, 3353 .hdisplay = 480, 3354 .hsync_start = 480 + 40, 3355 .hsync_end = 480 + 40 + 10, 3356 .htotal = 480 + 40 + 10 + 40, 3357 .vdisplay = 640, 3358 .vsync_start = 640 + 4, 3359 .vsync_end = 640 + 4 + 2, 3360 .vtotal = 640 + 4 + 2 + 4, 3361 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3362 }; 3363 3364 static const struct panel_desc ortustech_com37h3m = { 3365 .modes = &ortustech_com37h3m_mode, 3366 .num_modes = 1, 3367 .bpc = 8, 3368 .size = { 3369 .width = 56, /* 56.16mm */ 3370 .height = 75, /* 74.88mm */ 3371 }, 3372 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3373 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3374 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3375 }; 3376 3377 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3378 .clock = 25000, 3379 .hdisplay = 480, 3380 .hsync_start = 480 + 10, 3381 .hsync_end = 480 + 10 + 10, 3382 .htotal = 480 + 10 + 10 + 15, 3383 .vdisplay = 800, 3384 .vsync_start = 800 + 3, 3385 .vsync_end = 800 + 3 + 3, 3386 .vtotal = 800 + 3 + 3 + 3, 3387 }; 3388 3389 static const struct panel_desc ortustech_com43h4m85ulc = { 3390 .modes = &ortustech_com43h4m85ulc_mode, 3391 .num_modes = 1, 3392 .bpc = 6, 3393 .size = { 3394 .width = 56, 3395 .height = 93, 3396 }, 3397 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3398 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3399 .connector_type = DRM_MODE_CONNECTOR_DPI, 3400 }; 3401 3402 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3403 .clock = 33000, 3404 .hdisplay = 800, 3405 .hsync_start = 800 + 210, 3406 .hsync_end = 800 + 210 + 30, 3407 .htotal = 800 + 210 + 30 + 16, 3408 .vdisplay = 480, 3409 .vsync_start = 480 + 22, 3410 .vsync_end = 480 + 22 + 13, 3411 .vtotal = 480 + 22 + 13 + 10, 3412 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3413 }; 3414 3415 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3416 .modes = &osddisplays_osd070t1718_19ts_mode, 3417 .num_modes = 1, 3418 .bpc = 8, 3419 .size = { 3420 .width = 152, 3421 .height = 91, 3422 }, 3423 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3424 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3425 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3426 .connector_type = DRM_MODE_CONNECTOR_DPI, 3427 }; 3428 3429 static const struct drm_display_mode pda_91_00156_a0_mode = { 3430 .clock = 33300, 3431 .hdisplay = 800, 3432 .hsync_start = 800 + 1, 3433 .hsync_end = 800 + 1 + 64, 3434 .htotal = 800 + 1 + 64 + 64, 3435 .vdisplay = 480, 3436 .vsync_start = 480 + 1, 3437 .vsync_end = 480 + 1 + 23, 3438 .vtotal = 480 + 1 + 23 + 22, 3439 }; 3440 3441 static const struct panel_desc pda_91_00156_a0 = { 3442 .modes = &pda_91_00156_a0_mode, 3443 .num_modes = 1, 3444 .size = { 3445 .width = 152, 3446 .height = 91, 3447 }, 3448 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3449 }; 3450 3451 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3452 .clock = 24750, 3453 .hdisplay = 800, 3454 .hsync_start = 800 + 54, 3455 .hsync_end = 800 + 54 + 2, 3456 .htotal = 800 + 54 + 2 + 44, 3457 .vdisplay = 480, 3458 .vsync_start = 480 + 49, 3459 .vsync_end = 480 + 49 + 2, 3460 .vtotal = 480 + 49 + 2 + 22, 3461 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3462 }; 3463 3464 static const struct panel_desc powertip_ph800480t013_idf02 = { 3465 .modes = &powertip_ph800480t013_idf02_mode, 3466 .num_modes = 1, 3467 .bpc = 8, 3468 .size = { 3469 .width = 152, 3470 .height = 91, 3471 }, 3472 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3473 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3474 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3475 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3476 .connector_type = DRM_MODE_CONNECTOR_DPI, 3477 }; 3478 3479 static const struct drm_display_mode qd43003c0_40_mode = { 3480 .clock = 9000, 3481 .hdisplay = 480, 3482 .hsync_start = 480 + 8, 3483 .hsync_end = 480 + 8 + 4, 3484 .htotal = 480 + 8 + 4 + 39, 3485 .vdisplay = 272, 3486 .vsync_start = 272 + 4, 3487 .vsync_end = 272 + 4 + 10, 3488 .vtotal = 272 + 4 + 10 + 2, 3489 }; 3490 3491 static const struct panel_desc qd43003c0_40 = { 3492 .modes = &qd43003c0_40_mode, 3493 .num_modes = 1, 3494 .bpc = 8, 3495 .size = { 3496 .width = 95, 3497 .height = 53, 3498 }, 3499 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3500 }; 3501 3502 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3503 { /* 60 Hz */ 3504 .clock = 10800, 3505 .hdisplay = 480, 3506 .hsync_start = 480 + 77, 3507 .hsync_end = 480 + 77 + 41, 3508 .htotal = 480 + 77 + 41 + 2, 3509 .vdisplay = 272, 3510 .vsync_start = 272 + 16, 3511 .vsync_end = 272 + 16 + 10, 3512 .vtotal = 272 + 16 + 10 + 2, 3513 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3514 }, 3515 { /* 50 Hz */ 3516 .clock = 10800, 3517 .hdisplay = 480, 3518 .hsync_start = 480 + 17, 3519 .hsync_end = 480 + 17 + 41, 3520 .htotal = 480 + 17 + 41 + 2, 3521 .vdisplay = 272, 3522 .vsync_start = 272 + 116, 3523 .vsync_end = 272 + 116 + 10, 3524 .vtotal = 272 + 116 + 10 + 2, 3525 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3526 }, 3527 }; 3528 3529 static const struct panel_desc qishenglong_gopher2b_lcd = { 3530 .modes = qishenglong_gopher2b_lcd_modes, 3531 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3532 .bpc = 8, 3533 .size = { 3534 .width = 95, 3535 .height = 54, 3536 }, 3537 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3538 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3539 .connector_type = DRM_MODE_CONNECTOR_DPI, 3540 }; 3541 3542 static const struct display_timing rocktech_rk043fn48h_timing = { 3543 .pixelclock = { 6000000, 9000000, 12000000 }, 3544 .hactive = { 480, 480, 480 }, 3545 .hback_porch = { 8, 43, 43 }, 3546 .hfront_porch = { 2, 8, 10 }, 3547 .hsync_len = { 1, 1, 1 }, 3548 .vactive = { 272, 272, 272 }, 3549 .vback_porch = { 2, 12, 26 }, 3550 .vfront_porch = { 1, 4, 4 }, 3551 .vsync_len = { 1, 10, 10 }, 3552 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3553 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3554 DISPLAY_FLAGS_SYNC_POSEDGE, 3555 }; 3556 3557 static const struct panel_desc rocktech_rk043fn48h = { 3558 .timings = &rocktech_rk043fn48h_timing, 3559 .num_timings = 1, 3560 .bpc = 8, 3561 .size = { 3562 .width = 95, 3563 .height = 54, 3564 }, 3565 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3566 .connector_type = DRM_MODE_CONNECTOR_DPI, 3567 }; 3568 3569 static const struct display_timing rocktech_rk070er9427_timing = { 3570 .pixelclock = { 26400000, 33300000, 46800000 }, 3571 .hactive = { 800, 800, 800 }, 3572 .hfront_porch = { 16, 210, 354 }, 3573 .hback_porch = { 46, 46, 46 }, 3574 .hsync_len = { 1, 1, 1 }, 3575 .vactive = { 480, 480, 480 }, 3576 .vfront_porch = { 7, 22, 147 }, 3577 .vback_porch = { 23, 23, 23 }, 3578 .vsync_len = { 1, 1, 1 }, 3579 .flags = DISPLAY_FLAGS_DE_HIGH, 3580 }; 3581 3582 static const struct panel_desc rocktech_rk070er9427 = { 3583 .timings = &rocktech_rk070er9427_timing, 3584 .num_timings = 1, 3585 .bpc = 6, 3586 .size = { 3587 .width = 154, 3588 .height = 86, 3589 }, 3590 .delay = { 3591 .prepare = 41, 3592 .enable = 50, 3593 .unprepare = 41, 3594 .disable = 50, 3595 }, 3596 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3597 }; 3598 3599 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 3600 .clock = 71100, 3601 .hdisplay = 1280, 3602 .hsync_start = 1280 + 48, 3603 .hsync_end = 1280 + 48 + 32, 3604 .htotal = 1280 + 48 + 32 + 80, 3605 .vdisplay = 800, 3606 .vsync_start = 800 + 2, 3607 .vsync_end = 800 + 2 + 5, 3608 .vtotal = 800 + 2 + 5 + 16, 3609 }; 3610 3611 static const struct panel_desc rocktech_rk101ii01d_ct = { 3612 .modes = &rocktech_rk101ii01d_ct_mode, 3613 .bpc = 8, 3614 .num_modes = 1, 3615 .size = { 3616 .width = 217, 3617 .height = 136, 3618 }, 3619 .delay = { 3620 .prepare = 50, 3621 .disable = 50, 3622 }, 3623 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3624 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3625 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3626 }; 3627 3628 static const struct display_timing samsung_ltl101al01_timing = { 3629 .pixelclock = { 66663000, 66663000, 66663000 }, 3630 .hactive = { 1280, 1280, 1280 }, 3631 .hfront_porch = { 18, 18, 18 }, 3632 .hback_porch = { 36, 36, 36 }, 3633 .hsync_len = { 16, 16, 16 }, 3634 .vactive = { 800, 800, 800 }, 3635 .vfront_porch = { 4, 4, 4 }, 3636 .vback_porch = { 16, 16, 16 }, 3637 .vsync_len = { 3, 3, 3 }, 3638 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 3639 }; 3640 3641 static const struct panel_desc samsung_ltl101al01 = { 3642 .timings = &samsung_ltl101al01_timing, 3643 .num_timings = 1, 3644 .bpc = 8, 3645 .size = { 3646 .width = 217, 3647 .height = 135, 3648 }, 3649 .delay = { 3650 .prepare = 40, 3651 .enable = 300, 3652 .disable = 200, 3653 .unprepare = 600, 3654 }, 3655 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3656 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3657 }; 3658 3659 static const struct drm_display_mode samsung_ltn101nt05_mode = { 3660 .clock = 54030, 3661 .hdisplay = 1024, 3662 .hsync_start = 1024 + 24, 3663 .hsync_end = 1024 + 24 + 136, 3664 .htotal = 1024 + 24 + 136 + 160, 3665 .vdisplay = 600, 3666 .vsync_start = 600 + 3, 3667 .vsync_end = 600 + 3 + 6, 3668 .vtotal = 600 + 3 + 6 + 61, 3669 }; 3670 3671 static const struct panel_desc samsung_ltn101nt05 = { 3672 .modes = &samsung_ltn101nt05_mode, 3673 .num_modes = 1, 3674 .bpc = 6, 3675 .size = { 3676 .width = 223, 3677 .height = 125, 3678 }, 3679 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3680 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3681 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3682 }; 3683 3684 static const struct display_timing satoz_sat050at40h12r2_timing = { 3685 .pixelclock = {33300000, 33300000, 50000000}, 3686 .hactive = {800, 800, 800}, 3687 .hfront_porch = {16, 210, 354}, 3688 .hback_porch = {46, 46, 46}, 3689 .hsync_len = {1, 1, 40}, 3690 .vactive = {480, 480, 480}, 3691 .vfront_porch = {7, 22, 147}, 3692 .vback_porch = {23, 23, 23}, 3693 .vsync_len = {1, 1, 20}, 3694 }; 3695 3696 static const struct panel_desc satoz_sat050at40h12r2 = { 3697 .timings = &satoz_sat050at40h12r2_timing, 3698 .num_timings = 1, 3699 .bpc = 8, 3700 .size = { 3701 .width = 108, 3702 .height = 65, 3703 }, 3704 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3705 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3706 }; 3707 3708 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 3709 .clock = 33260, 3710 .hdisplay = 800, 3711 .hsync_start = 800 + 64, 3712 .hsync_end = 800 + 64 + 128, 3713 .htotal = 800 + 64 + 128 + 64, 3714 .vdisplay = 480, 3715 .vsync_start = 480 + 8, 3716 .vsync_end = 480 + 8 + 2, 3717 .vtotal = 480 + 8 + 2 + 35, 3718 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3719 }; 3720 3721 static const struct panel_desc sharp_lq070y3dg3b = { 3722 .modes = &sharp_lq070y3dg3b_mode, 3723 .num_modes = 1, 3724 .bpc = 8, 3725 .size = { 3726 .width = 152, /* 152.4mm */ 3727 .height = 91, /* 91.4mm */ 3728 }, 3729 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3730 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3731 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3732 }; 3733 3734 static const struct drm_display_mode sharp_lq035q7db03_mode = { 3735 .clock = 5500, 3736 .hdisplay = 240, 3737 .hsync_start = 240 + 16, 3738 .hsync_end = 240 + 16 + 7, 3739 .htotal = 240 + 16 + 7 + 5, 3740 .vdisplay = 320, 3741 .vsync_start = 320 + 9, 3742 .vsync_end = 320 + 9 + 1, 3743 .vtotal = 320 + 9 + 1 + 7, 3744 }; 3745 3746 static const struct panel_desc sharp_lq035q7db03 = { 3747 .modes = &sharp_lq035q7db03_mode, 3748 .num_modes = 1, 3749 .bpc = 6, 3750 .size = { 3751 .width = 54, 3752 .height = 72, 3753 }, 3754 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3755 }; 3756 3757 static const struct display_timing sharp_lq101k1ly04_timing = { 3758 .pixelclock = { 60000000, 65000000, 80000000 }, 3759 .hactive = { 1280, 1280, 1280 }, 3760 .hfront_porch = { 20, 20, 20 }, 3761 .hback_porch = { 20, 20, 20 }, 3762 .hsync_len = { 10, 10, 10 }, 3763 .vactive = { 800, 800, 800 }, 3764 .vfront_porch = { 4, 4, 4 }, 3765 .vback_porch = { 4, 4, 4 }, 3766 .vsync_len = { 4, 4, 4 }, 3767 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 3768 }; 3769 3770 static const struct panel_desc sharp_lq101k1ly04 = { 3771 .timings = &sharp_lq101k1ly04_timing, 3772 .num_timings = 1, 3773 .bpc = 8, 3774 .size = { 3775 .width = 217, 3776 .height = 136, 3777 }, 3778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 3779 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3780 }; 3781 3782 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 3783 { /* 50 Hz */ 3784 .clock = 3000, 3785 .hdisplay = 240, 3786 .hsync_start = 240 + 58, 3787 .hsync_end = 240 + 58 + 1, 3788 .htotal = 240 + 58 + 1 + 1, 3789 .vdisplay = 160, 3790 .vsync_start = 160 + 24, 3791 .vsync_end = 160 + 24 + 10, 3792 .vtotal = 160 + 24 + 10 + 6, 3793 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3794 }, 3795 { /* 60 Hz */ 3796 .clock = 3000, 3797 .hdisplay = 240, 3798 .hsync_start = 240 + 8, 3799 .hsync_end = 240 + 8 + 1, 3800 .htotal = 240 + 8 + 1 + 1, 3801 .vdisplay = 160, 3802 .vsync_start = 160 + 24, 3803 .vsync_end = 160 + 24 + 10, 3804 .vtotal = 160 + 24 + 10 + 6, 3805 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 3806 }, 3807 }; 3808 3809 static const struct panel_desc sharp_ls020b1dd01d = { 3810 .modes = sharp_ls020b1dd01d_modes, 3811 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 3812 .bpc = 6, 3813 .size = { 3814 .width = 42, 3815 .height = 28, 3816 }, 3817 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3818 .bus_flags = DRM_BUS_FLAG_DE_HIGH 3819 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 3820 | DRM_BUS_FLAG_SHARP_SIGNALS, 3821 }; 3822 3823 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 3824 .clock = 33300, 3825 .hdisplay = 800, 3826 .hsync_start = 800 + 1, 3827 .hsync_end = 800 + 1 + 64, 3828 .htotal = 800 + 1 + 64 + 64, 3829 .vdisplay = 480, 3830 .vsync_start = 480 + 1, 3831 .vsync_end = 480 + 1 + 23, 3832 .vtotal = 480 + 1 + 23 + 22, 3833 }; 3834 3835 static const struct panel_desc shelly_sca07010_bfn_lnn = { 3836 .modes = &shelly_sca07010_bfn_lnn_mode, 3837 .num_modes = 1, 3838 .size = { 3839 .width = 152, 3840 .height = 91, 3841 }, 3842 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3843 }; 3844 3845 static const struct drm_display_mode starry_kr070pe2t_mode = { 3846 .clock = 33000, 3847 .hdisplay = 800, 3848 .hsync_start = 800 + 209, 3849 .hsync_end = 800 + 209 + 1, 3850 .htotal = 800 + 209 + 1 + 45, 3851 .vdisplay = 480, 3852 .vsync_start = 480 + 22, 3853 .vsync_end = 480 + 22 + 1, 3854 .vtotal = 480 + 22 + 1 + 22, 3855 }; 3856 3857 static const struct panel_desc starry_kr070pe2t = { 3858 .modes = &starry_kr070pe2t_mode, 3859 .num_modes = 1, 3860 .bpc = 8, 3861 .size = { 3862 .width = 152, 3863 .height = 86, 3864 }, 3865 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3866 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 3867 .connector_type = DRM_MODE_CONNECTOR_DPI, 3868 }; 3869 3870 static const struct display_timing startek_kd070wvfpa_mode = { 3871 .pixelclock = { 25200000, 27200000, 30500000 }, 3872 .hactive = { 800, 800, 800 }, 3873 .hfront_porch = { 19, 44, 115 }, 3874 .hback_porch = { 5, 16, 101 }, 3875 .hsync_len = { 1, 2, 100 }, 3876 .vactive = { 480, 480, 480 }, 3877 .vfront_porch = { 5, 43, 67 }, 3878 .vback_porch = { 5, 5, 67 }, 3879 .vsync_len = { 1, 2, 66 }, 3880 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3881 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3882 DISPLAY_FLAGS_SYNC_POSEDGE, 3883 }; 3884 3885 static const struct panel_desc startek_kd070wvfpa = { 3886 .timings = &startek_kd070wvfpa_mode, 3887 .num_timings = 1, 3888 .bpc = 8, 3889 .size = { 3890 .width = 152, 3891 .height = 91, 3892 }, 3893 .delay = { 3894 .prepare = 20, 3895 .enable = 200, 3896 .disable = 200, 3897 }, 3898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3899 .connector_type = DRM_MODE_CONNECTOR_DPI, 3900 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3901 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3902 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3903 }; 3904 3905 static const struct display_timing tsd_tst043015cmhx_timing = { 3906 .pixelclock = { 5000000, 9000000, 12000000 }, 3907 .hactive = { 480, 480, 480 }, 3908 .hfront_porch = { 4, 5, 65 }, 3909 .hback_porch = { 36, 40, 255 }, 3910 .hsync_len = { 1, 1, 1 }, 3911 .vactive = { 272, 272, 272 }, 3912 .vfront_porch = { 2, 8, 97 }, 3913 .vback_porch = { 3, 8, 31 }, 3914 .vsync_len = { 1, 1, 1 }, 3915 3916 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3917 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3918 }; 3919 3920 static const struct panel_desc tsd_tst043015cmhx = { 3921 .timings = &tsd_tst043015cmhx_timing, 3922 .num_timings = 1, 3923 .bpc = 8, 3924 .size = { 3925 .width = 105, 3926 .height = 67, 3927 }, 3928 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3929 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3930 }; 3931 3932 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 3933 .clock = 30000, 3934 .hdisplay = 800, 3935 .hsync_start = 800 + 39, 3936 .hsync_end = 800 + 39 + 47, 3937 .htotal = 800 + 39 + 47 + 39, 3938 .vdisplay = 480, 3939 .vsync_start = 480 + 13, 3940 .vsync_end = 480 + 13 + 2, 3941 .vtotal = 480 + 13 + 2 + 29, 3942 }; 3943 3944 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 3945 .modes = &tfc_s9700rtwv43tr_01b_mode, 3946 .num_modes = 1, 3947 .bpc = 8, 3948 .size = { 3949 .width = 155, 3950 .height = 90, 3951 }, 3952 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3953 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3954 }; 3955 3956 static const struct display_timing tianma_tm070jdhg30_timing = { 3957 .pixelclock = { 62600000, 68200000, 78100000 }, 3958 .hactive = { 1280, 1280, 1280 }, 3959 .hfront_porch = { 15, 64, 159 }, 3960 .hback_porch = { 5, 5, 5 }, 3961 .hsync_len = { 1, 1, 256 }, 3962 .vactive = { 800, 800, 800 }, 3963 .vfront_porch = { 3, 40, 99 }, 3964 .vback_porch = { 2, 2, 2 }, 3965 .vsync_len = { 1, 1, 128 }, 3966 .flags = DISPLAY_FLAGS_DE_HIGH, 3967 }; 3968 3969 static const struct panel_desc tianma_tm070jdhg30 = { 3970 .timings = &tianma_tm070jdhg30_timing, 3971 .num_timings = 1, 3972 .bpc = 8, 3973 .size = { 3974 .width = 151, 3975 .height = 95, 3976 }, 3977 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3978 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3979 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3980 }; 3981 3982 static const struct panel_desc tianma_tm070jvhg33 = { 3983 .timings = &tianma_tm070jdhg30_timing, 3984 .num_timings = 1, 3985 .bpc = 8, 3986 .size = { 3987 .width = 150, 3988 .height = 94, 3989 }, 3990 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3991 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3992 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3993 }; 3994 3995 static const struct display_timing tianma_tm070rvhg71_timing = { 3996 .pixelclock = { 27700000, 29200000, 39600000 }, 3997 .hactive = { 800, 800, 800 }, 3998 .hfront_porch = { 12, 40, 212 }, 3999 .hback_porch = { 88, 88, 88 }, 4000 .hsync_len = { 1, 1, 40 }, 4001 .vactive = { 480, 480, 480 }, 4002 .vfront_porch = { 1, 13, 88 }, 4003 .vback_porch = { 32, 32, 32 }, 4004 .vsync_len = { 1, 1, 3 }, 4005 .flags = DISPLAY_FLAGS_DE_HIGH, 4006 }; 4007 4008 static const struct panel_desc tianma_tm070rvhg71 = { 4009 .timings = &tianma_tm070rvhg71_timing, 4010 .num_timings = 1, 4011 .bpc = 8, 4012 .size = { 4013 .width = 154, 4014 .height = 86, 4015 }, 4016 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4017 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4018 }; 4019 4020 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4021 { 4022 .clock = 10000, 4023 .hdisplay = 320, 4024 .hsync_start = 320 + 50, 4025 .hsync_end = 320 + 50 + 6, 4026 .htotal = 320 + 50 + 6 + 38, 4027 .vdisplay = 240, 4028 .vsync_start = 240 + 3, 4029 .vsync_end = 240 + 3 + 1, 4030 .vtotal = 240 + 3 + 1 + 17, 4031 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4032 }, 4033 }; 4034 4035 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4036 .modes = ti_nspire_cx_lcd_mode, 4037 .num_modes = 1, 4038 .bpc = 8, 4039 .size = { 4040 .width = 65, 4041 .height = 49, 4042 }, 4043 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4044 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4045 }; 4046 4047 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4048 { 4049 .clock = 10000, 4050 .hdisplay = 320, 4051 .hsync_start = 320 + 6, 4052 .hsync_end = 320 + 6 + 6, 4053 .htotal = 320 + 6 + 6 + 6, 4054 .vdisplay = 240, 4055 .vsync_start = 240 + 0, 4056 .vsync_end = 240 + 0 + 1, 4057 .vtotal = 240 + 0 + 1 + 0, 4058 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4059 }, 4060 }; 4061 4062 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4063 .modes = ti_nspire_classic_lcd_mode, 4064 .num_modes = 1, 4065 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4066 .bpc = 8, 4067 .size = { 4068 .width = 71, 4069 .height = 53, 4070 }, 4071 /* This is the grayscale bus format */ 4072 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4073 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4074 }; 4075 4076 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4077 .clock = 79500, 4078 .hdisplay = 1280, 4079 .hsync_start = 1280 + 192, 4080 .hsync_end = 1280 + 192 + 128, 4081 .htotal = 1280 + 192 + 128 + 64, 4082 .vdisplay = 768, 4083 .vsync_start = 768 + 20, 4084 .vsync_end = 768 + 20 + 7, 4085 .vtotal = 768 + 20 + 7 + 3, 4086 }; 4087 4088 static const struct panel_desc toshiba_lt089ac29000 = { 4089 .modes = &toshiba_lt089ac29000_mode, 4090 .num_modes = 1, 4091 .size = { 4092 .width = 194, 4093 .height = 116, 4094 }, 4095 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4096 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4097 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4098 }; 4099 4100 static const struct drm_display_mode tpk_f07a_0102_mode = { 4101 .clock = 33260, 4102 .hdisplay = 800, 4103 .hsync_start = 800 + 40, 4104 .hsync_end = 800 + 40 + 128, 4105 .htotal = 800 + 40 + 128 + 88, 4106 .vdisplay = 480, 4107 .vsync_start = 480 + 10, 4108 .vsync_end = 480 + 10 + 2, 4109 .vtotal = 480 + 10 + 2 + 33, 4110 }; 4111 4112 static const struct panel_desc tpk_f07a_0102 = { 4113 .modes = &tpk_f07a_0102_mode, 4114 .num_modes = 1, 4115 .size = { 4116 .width = 152, 4117 .height = 91, 4118 }, 4119 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4120 }; 4121 4122 static const struct drm_display_mode tpk_f10a_0102_mode = { 4123 .clock = 45000, 4124 .hdisplay = 1024, 4125 .hsync_start = 1024 + 176, 4126 .hsync_end = 1024 + 176 + 5, 4127 .htotal = 1024 + 176 + 5 + 88, 4128 .vdisplay = 600, 4129 .vsync_start = 600 + 20, 4130 .vsync_end = 600 + 20 + 5, 4131 .vtotal = 600 + 20 + 5 + 25, 4132 }; 4133 4134 static const struct panel_desc tpk_f10a_0102 = { 4135 .modes = &tpk_f10a_0102_mode, 4136 .num_modes = 1, 4137 .size = { 4138 .width = 223, 4139 .height = 125, 4140 }, 4141 }; 4142 4143 static const struct display_timing urt_umsh_8596md_timing = { 4144 .pixelclock = { 33260000, 33260000, 33260000 }, 4145 .hactive = { 800, 800, 800 }, 4146 .hfront_porch = { 41, 41, 41 }, 4147 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4148 .hsync_len = { 71, 128, 128 }, 4149 .vactive = { 480, 480, 480 }, 4150 .vfront_porch = { 10, 10, 10 }, 4151 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4152 .vsync_len = { 2, 2, 2 }, 4153 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4154 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4155 }; 4156 4157 static const struct panel_desc urt_umsh_8596md_lvds = { 4158 .timings = &urt_umsh_8596md_timing, 4159 .num_timings = 1, 4160 .bpc = 6, 4161 .size = { 4162 .width = 152, 4163 .height = 91, 4164 }, 4165 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4166 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4167 }; 4168 4169 static const struct panel_desc urt_umsh_8596md_parallel = { 4170 .timings = &urt_umsh_8596md_timing, 4171 .num_timings = 1, 4172 .bpc = 6, 4173 .size = { 4174 .width = 152, 4175 .height = 91, 4176 }, 4177 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4178 }; 4179 4180 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4181 .clock = 60000, 4182 .hdisplay = 1024, 4183 .hsync_start = 1024 + 160, 4184 .hsync_end = 1024 + 160 + 100, 4185 .htotal = 1024 + 160 + 100 + 60, 4186 .vdisplay = 600, 4187 .vsync_start = 600 + 12, 4188 .vsync_end = 600 + 12 + 10, 4189 .vtotal = 600 + 12 + 10 + 13, 4190 }; 4191 4192 static const struct panel_desc vivax_tpc9150_panel = { 4193 .modes = &vivax_tpc9150_panel_mode, 4194 .num_modes = 1, 4195 .bpc = 6, 4196 .size = { 4197 .width = 200, 4198 .height = 115, 4199 }, 4200 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4201 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4202 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4203 }; 4204 4205 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4206 .clock = 33333, 4207 .hdisplay = 800, 4208 .hsync_start = 800 + 210, 4209 .hsync_end = 800 + 210 + 20, 4210 .htotal = 800 + 210 + 20 + 46, 4211 .vdisplay = 480, 4212 .vsync_start = 480 + 22, 4213 .vsync_end = 480 + 22 + 10, 4214 .vtotal = 480 + 22 + 10 + 23, 4215 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4216 }; 4217 4218 static const struct panel_desc vl050_8048nt_c01 = { 4219 .modes = &vl050_8048nt_c01_mode, 4220 .num_modes = 1, 4221 .bpc = 8, 4222 .size = { 4223 .width = 120, 4224 .height = 76, 4225 }, 4226 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4227 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4228 }; 4229 4230 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4231 .clock = 6410, 4232 .hdisplay = 320, 4233 .hsync_start = 320 + 20, 4234 .hsync_end = 320 + 20 + 30, 4235 .htotal = 320 + 20 + 30 + 38, 4236 .vdisplay = 240, 4237 .vsync_start = 240 + 4, 4238 .vsync_end = 240 + 4 + 3, 4239 .vtotal = 240 + 4 + 3 + 15, 4240 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4241 }; 4242 4243 static const struct panel_desc winstar_wf35ltiacd = { 4244 .modes = &winstar_wf35ltiacd_mode, 4245 .num_modes = 1, 4246 .bpc = 8, 4247 .size = { 4248 .width = 70, 4249 .height = 53, 4250 }, 4251 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4252 }; 4253 4254 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4255 .clock = 51200, 4256 .hdisplay = 1024, 4257 .hsync_start = 1024 + 100, 4258 .hsync_end = 1024 + 100 + 100, 4259 .htotal = 1024 + 100 + 100 + 120, 4260 .vdisplay = 600, 4261 .vsync_start = 600 + 10, 4262 .vsync_end = 600 + 10 + 10, 4263 .vtotal = 600 + 10 + 10 + 15, 4264 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4265 }; 4266 4267 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4268 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4269 .num_modes = 1, 4270 .bpc = 8, 4271 .size = { 4272 .width = 154, 4273 .height = 90, 4274 }, 4275 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4276 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4277 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4278 }; 4279 4280 static const struct drm_display_mode arm_rtsm_mode[] = { 4281 { 4282 .clock = 65000, 4283 .hdisplay = 1024, 4284 .hsync_start = 1024 + 24, 4285 .hsync_end = 1024 + 24 + 136, 4286 .htotal = 1024 + 24 + 136 + 160, 4287 .vdisplay = 768, 4288 .vsync_start = 768 + 3, 4289 .vsync_end = 768 + 3 + 6, 4290 .vtotal = 768 + 3 + 6 + 29, 4291 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4292 }, 4293 }; 4294 4295 static const struct panel_desc arm_rtsm = { 4296 .modes = arm_rtsm_mode, 4297 .num_modes = 1, 4298 .bpc = 8, 4299 .size = { 4300 .width = 400, 4301 .height = 300, 4302 }, 4303 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4304 }; 4305 4306 static const struct of_device_id platform_of_match[] = { 4307 { 4308 .compatible = "ampire,am-1280800n3tzqw-t00h", 4309 .data = &ire_am_1280800n3tzqw_t00h, 4310 }, { 4311 .compatible = "ampire,am-480272h3tmqw-t01h", 4312 .data = &ire_am_480272h3tmqw_t01h, 4313 }, { 4314 .compatible = "ampire,am-800480l1tmqw-t00h", 4315 .data = &ire_am_800480l1tmqw_t00h, 4316 }, { 4317 .compatible = "ampire,am800480r3tmqwa1h", 4318 .data = &ire_am800480r3tmqwa1h, 4319 }, { 4320 .compatible = "ampire,am800600p5tmqw-tb8h", 4321 .data = &ire_am800600p5tmqwtb8h, 4322 }, { 4323 .compatible = "arm,rtsm-display", 4324 .data = &arm_rtsm, 4325 }, { 4326 .compatible = "armadeus,st0700-adapt", 4327 .data = &armadeus_st0700_adapt, 4328 }, { 4329 .compatible = "auo,b101aw03", 4330 .data = &auo_b101aw03, 4331 }, { 4332 .compatible = "auo,b101xtn01", 4333 .data = &auo_b101xtn01, 4334 }, { 4335 .compatible = "auo,b116xw03", 4336 .data = &auo_b116xw03, 4337 }, { 4338 .compatible = "auo,g070vvn01", 4339 .data = &auo_g070vvn01, 4340 }, { 4341 .compatible = "auo,g101evn010", 4342 .data = &auo_g101evn010, 4343 }, { 4344 .compatible = "auo,g104sn02", 4345 .data = &auo_g104sn02, 4346 }, { 4347 .compatible = "auo,g121ean01", 4348 .data = &auo_g121ean01, 4349 }, { 4350 .compatible = "auo,g133han01", 4351 .data = &auo_g133han01, 4352 }, { 4353 .compatible = "auo,g156han04", 4354 .data = &auo_g156han04, 4355 }, { 4356 .compatible = "auo,g156xtn01", 4357 .data = &auo_g156xtn01, 4358 }, { 4359 .compatible = "auo,g185han01", 4360 .data = &auo_g185han01, 4361 }, { 4362 .compatible = "auo,g190ean01", 4363 .data = &auo_g190ean01, 4364 }, { 4365 .compatible = "auo,p320hvn03", 4366 .data = &auo_p320hvn03, 4367 }, { 4368 .compatible = "auo,t215hvn01", 4369 .data = &auo_t215hvn01, 4370 }, { 4371 .compatible = "avic,tm070ddh03", 4372 .data = &avic_tm070ddh03, 4373 }, { 4374 .compatible = "bananapi,s070wv20-ct16", 4375 .data = &bananapi_s070wv20_ct16, 4376 }, { 4377 .compatible = "boe,bp101wx1-100", 4378 .data = &boe_bp101wx1_100, 4379 }, { 4380 .compatible = "boe,ev121wxm-n10-1850", 4381 .data = &boe_ev121wxm_n10_1850, 4382 }, { 4383 .compatible = "boe,hv070wsa-100", 4384 .data = &boe_hv070wsa 4385 }, { 4386 .compatible = "cdtech,s043wq26h-ct7", 4387 .data = &cdtech_s043wq26h_ct7, 4388 }, { 4389 .compatible = "cdtech,s070pws19hp-fc21", 4390 .data = &cdtech_s070pws19hp_fc21, 4391 }, { 4392 .compatible = "cdtech,s070swv29hg-dc44", 4393 .data = &cdtech_s070swv29hg_dc44, 4394 }, { 4395 .compatible = "cdtech,s070wv95-ct16", 4396 .data = &cdtech_s070wv95_ct16, 4397 }, { 4398 .compatible = "chefree,ch101olhlwh-002", 4399 .data = &chefree_ch101olhlwh_002, 4400 }, { 4401 .compatible = "chunghwa,claa070wp03xg", 4402 .data = &chunghwa_claa070wp03xg, 4403 }, { 4404 .compatible = "chunghwa,claa101wa01a", 4405 .data = &chunghwa_claa101wa01a 4406 }, { 4407 .compatible = "chunghwa,claa101wb01", 4408 .data = &chunghwa_claa101wb01 4409 }, { 4410 .compatible = "dataimage,fg040346dsswbg04", 4411 .data = &dataimage_fg040346dsswbg04, 4412 }, { 4413 .compatible = "dataimage,fg1001l0dsswmg01", 4414 .data = &dataimage_fg1001l0dsswmg01, 4415 }, { 4416 .compatible = "dataimage,scf0700c48ggu18", 4417 .data = &dataimage_scf0700c48ggu18, 4418 }, { 4419 .compatible = "dlc,dlc0700yzg-1", 4420 .data = &dlc_dlc0700yzg_1, 4421 }, { 4422 .compatible = "dlc,dlc1010gig", 4423 .data = &dlc_dlc1010gig, 4424 }, { 4425 .compatible = "edt,et035012dm6", 4426 .data = &edt_et035012dm6, 4427 }, { 4428 .compatible = "edt,etm0350g0dh6", 4429 .data = &edt_etm0350g0dh6, 4430 }, { 4431 .compatible = "edt,etm043080dh6gp", 4432 .data = &edt_etm043080dh6gp, 4433 }, { 4434 .compatible = "edt,etm0430g0dh6", 4435 .data = &edt_etm0430g0dh6, 4436 }, { 4437 .compatible = "edt,et057090dhu", 4438 .data = &edt_et057090dhu, 4439 }, { 4440 .compatible = "edt,et070080dh6", 4441 .data = &edt_etm0700g0dh6, 4442 }, { 4443 .compatible = "edt,etm0700g0dh6", 4444 .data = &edt_etm0700g0dh6, 4445 }, { 4446 .compatible = "edt,etm0700g0bdh6", 4447 .data = &edt_etm0700g0bdh6, 4448 }, { 4449 .compatible = "edt,etm0700g0edh6", 4450 .data = &edt_etm0700g0bdh6, 4451 }, { 4452 .compatible = "edt,etml0700y5dha", 4453 .data = &edt_etml0700y5dha, 4454 }, { 4455 .compatible = "edt,etml1010g3dra", 4456 .data = &edt_etml1010g3dra, 4457 }, { 4458 .compatible = "edt,etmv570g2dhu", 4459 .data = &edt_etmv570g2dhu, 4460 }, { 4461 .compatible = "eink,vb3300-kca", 4462 .data = &eink_vb3300_kca, 4463 }, { 4464 .compatible = "evervision,vgg644804", 4465 .data = &evervision_vgg644804, 4466 }, { 4467 .compatible = "evervision,vgg804821", 4468 .data = &evervision_vgg804821, 4469 }, { 4470 .compatible = "foxlink,fl500wvr00-a0t", 4471 .data = &foxlink_fl500wvr00_a0t, 4472 }, { 4473 .compatible = "frida,frd350h54004", 4474 .data = &frida_frd350h54004, 4475 }, { 4476 .compatible = "friendlyarm,hd702e", 4477 .data = &friendlyarm_hd702e, 4478 }, { 4479 .compatible = "giantplus,gpg482739qs5", 4480 .data = &giantplus_gpg482739qs5 4481 }, { 4482 .compatible = "giantplus,gpm940b0", 4483 .data = &giantplus_gpm940b0, 4484 }, { 4485 .compatible = "hannstar,hsd070pww1", 4486 .data = &hannstar_hsd070pww1, 4487 }, { 4488 .compatible = "hannstar,hsd100pxn1", 4489 .data = &hannstar_hsd100pxn1, 4490 }, { 4491 .compatible = "hannstar,hsd101pww2", 4492 .data = &hannstar_hsd101pww2, 4493 }, { 4494 .compatible = "hit,tx23d38vm0caa", 4495 .data = &hitachi_tx23d38vm0caa 4496 }, { 4497 .compatible = "innolux,at043tn24", 4498 .data = &innolux_at043tn24, 4499 }, { 4500 .compatible = "innolux,at070tn92", 4501 .data = &innolux_at070tn92, 4502 }, { 4503 .compatible = "innolux,g070ace-l01", 4504 .data = &innolux_g070ace_l01, 4505 }, { 4506 .compatible = "innolux,g070y2-l01", 4507 .data = &innolux_g070y2_l01, 4508 }, { 4509 .compatible = "innolux,g070y2-t02", 4510 .data = &innolux_g070y2_t02, 4511 }, { 4512 .compatible = "innolux,g101ice-l01", 4513 .data = &innolux_g101ice_l01 4514 }, { 4515 .compatible = "innolux,g121i1-l01", 4516 .data = &innolux_g121i1_l01 4517 }, { 4518 .compatible = "innolux,g121x1-l03", 4519 .data = &innolux_g121x1_l03, 4520 }, { 4521 .compatible = "innolux,g156hce-l01", 4522 .data = &innolux_g156hce_l01, 4523 }, { 4524 .compatible = "innolux,n156bge-l21", 4525 .data = &innolux_n156bge_l21, 4526 }, { 4527 .compatible = "innolux,zj070na-01p", 4528 .data = &innolux_zj070na_01p, 4529 }, { 4530 .compatible = "koe,tx14d24vm1bpa", 4531 .data = &koe_tx14d24vm1bpa, 4532 }, { 4533 .compatible = "koe,tx26d202vm0bwa", 4534 .data = &koe_tx26d202vm0bwa, 4535 }, { 4536 .compatible = "koe,tx31d200vm0baa", 4537 .data = &koe_tx31d200vm0baa, 4538 }, { 4539 .compatible = "kyo,tcg121xglp", 4540 .data = &kyo_tcg121xglp, 4541 }, { 4542 .compatible = "lemaker,bl035-rgb-002", 4543 .data = &lemaker_bl035_rgb_002, 4544 }, { 4545 .compatible = "lg,lb070wv8", 4546 .data = &lg_lb070wv8, 4547 }, { 4548 .compatible = "logicpd,type28", 4549 .data = &logicpd_type_28, 4550 }, { 4551 .compatible = "logictechno,lt161010-2nhc", 4552 .data = &logictechno_lt161010_2nh, 4553 }, { 4554 .compatible = "logictechno,lt161010-2nhr", 4555 .data = &logictechno_lt161010_2nh, 4556 }, { 4557 .compatible = "logictechno,lt170410-2whc", 4558 .data = &logictechno_lt170410_2whc, 4559 }, { 4560 .compatible = "logictechno,lttd800480070-l2rt", 4561 .data = &logictechno_lttd800480070_l2rt, 4562 }, { 4563 .compatible = "logictechno,lttd800480070-l6wh-rt", 4564 .data = &logictechno_lttd800480070_l6wh_rt, 4565 }, { 4566 .compatible = "mitsubishi,aa070mc01-ca1", 4567 .data = &mitsubishi_aa070mc01, 4568 }, { 4569 .compatible = "mitsubishi,aa084xe01", 4570 .data = &mitsubishi_aa084xe01, 4571 }, { 4572 .compatible = "multi-inno,mi0700s4t-6", 4573 .data = &multi_inno_mi0700s4t_6, 4574 }, { 4575 .compatible = "multi-inno,mi0800ft-9", 4576 .data = &multi_inno_mi0800ft_9, 4577 }, { 4578 .compatible = "multi-inno,mi1010ait-1cp", 4579 .data = &multi_inno_mi1010ait_1cp, 4580 }, { 4581 .compatible = "nec,nl12880bc20-05", 4582 .data = &nec_nl12880bc20_05, 4583 }, { 4584 .compatible = "nec,nl4827hc19-05b", 4585 .data = &nec_nl4827hc19_05b, 4586 }, { 4587 .compatible = "netron-dy,e231732", 4588 .data = &netron_dy_e231732, 4589 }, { 4590 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 4591 .data = &newhaven_nhd_43_480272ef_atxl, 4592 }, { 4593 .compatible = "nlt,nl192108ac18-02d", 4594 .data = &nlt_nl192108ac18_02d, 4595 }, { 4596 .compatible = "nvd,9128", 4597 .data = &nvd_9128, 4598 }, { 4599 .compatible = "okaya,rs800480t-7x0gp", 4600 .data = &okaya_rs800480t_7x0gp, 4601 }, { 4602 .compatible = "olimex,lcd-olinuxino-43-ts", 4603 .data = &olimex_lcd_olinuxino_43ts, 4604 }, { 4605 .compatible = "ontat,yx700wv03", 4606 .data = &ontat_yx700wv03, 4607 }, { 4608 .compatible = "ortustech,com37h3m05dtc", 4609 .data = &ortustech_com37h3m, 4610 }, { 4611 .compatible = "ortustech,com37h3m99dtc", 4612 .data = &ortustech_com37h3m, 4613 }, { 4614 .compatible = "ortustech,com43h4m85ulc", 4615 .data = &ortustech_com43h4m85ulc, 4616 }, { 4617 .compatible = "osddisplays,osd070t1718-19ts", 4618 .data = &osddisplays_osd070t1718_19ts, 4619 }, { 4620 .compatible = "pda,91-00156-a0", 4621 .data = &pda_91_00156_a0, 4622 }, { 4623 .compatible = "powertip,ph800480t013-idf02", 4624 .data = &powertip_ph800480t013_idf02, 4625 }, { 4626 .compatible = "qiaodian,qd43003c0-40", 4627 .data = &qd43003c0_40, 4628 }, { 4629 .compatible = "qishenglong,gopher2b-lcd", 4630 .data = &qishenglong_gopher2b_lcd, 4631 }, { 4632 .compatible = "rocktech,rk043fn48h", 4633 .data = &rocktech_rk043fn48h, 4634 }, { 4635 .compatible = "rocktech,rk070er9427", 4636 .data = &rocktech_rk070er9427, 4637 }, { 4638 .compatible = "rocktech,rk101ii01d-ct", 4639 .data = &rocktech_rk101ii01d_ct, 4640 }, { 4641 .compatible = "samsung,ltl101al01", 4642 .data = &samsung_ltl101al01, 4643 }, { 4644 .compatible = "samsung,ltn101nt05", 4645 .data = &samsung_ltn101nt05, 4646 }, { 4647 .compatible = "satoz,sat050at40h12r2", 4648 .data = &satoz_sat050at40h12r2, 4649 }, { 4650 .compatible = "sharp,lq035q7db03", 4651 .data = &sharp_lq035q7db03, 4652 }, { 4653 .compatible = "sharp,lq070y3dg3b", 4654 .data = &sharp_lq070y3dg3b, 4655 }, { 4656 .compatible = "sharp,lq101k1ly04", 4657 .data = &sharp_lq101k1ly04, 4658 }, { 4659 .compatible = "sharp,ls020b1dd01d", 4660 .data = &sharp_ls020b1dd01d, 4661 }, { 4662 .compatible = "shelly,sca07010-bfn-lnn", 4663 .data = &shelly_sca07010_bfn_lnn, 4664 }, { 4665 .compatible = "starry,kr070pe2t", 4666 .data = &starry_kr070pe2t, 4667 }, { 4668 .compatible = "startek,kd070wvfpa", 4669 .data = &startek_kd070wvfpa, 4670 }, { 4671 .compatible = "team-source-display,tst043015cmhx", 4672 .data = &tsd_tst043015cmhx, 4673 }, { 4674 .compatible = "tfc,s9700rtwv43tr-01b", 4675 .data = &tfc_s9700rtwv43tr_01b, 4676 }, { 4677 .compatible = "tianma,tm070jdhg30", 4678 .data = &tianma_tm070jdhg30, 4679 }, { 4680 .compatible = "tianma,tm070jvhg33", 4681 .data = &tianma_tm070jvhg33, 4682 }, { 4683 .compatible = "tianma,tm070rvhg71", 4684 .data = &tianma_tm070rvhg71, 4685 }, { 4686 .compatible = "ti,nspire-cx-lcd-panel", 4687 .data = &ti_nspire_cx_lcd_panel, 4688 }, { 4689 .compatible = "ti,nspire-classic-lcd-panel", 4690 .data = &ti_nspire_classic_lcd_panel, 4691 }, { 4692 .compatible = "toshiba,lt089ac29000", 4693 .data = &toshiba_lt089ac29000, 4694 }, { 4695 .compatible = "tpk,f07a-0102", 4696 .data = &tpk_f07a_0102, 4697 }, { 4698 .compatible = "tpk,f10a-0102", 4699 .data = &tpk_f10a_0102, 4700 }, { 4701 .compatible = "urt,umsh-8596md-t", 4702 .data = &urt_umsh_8596md_parallel, 4703 }, { 4704 .compatible = "urt,umsh-8596md-1t", 4705 .data = &urt_umsh_8596md_parallel, 4706 }, { 4707 .compatible = "urt,umsh-8596md-7t", 4708 .data = &urt_umsh_8596md_parallel, 4709 }, { 4710 .compatible = "urt,umsh-8596md-11t", 4711 .data = &urt_umsh_8596md_lvds, 4712 }, { 4713 .compatible = "urt,umsh-8596md-19t", 4714 .data = &urt_umsh_8596md_lvds, 4715 }, { 4716 .compatible = "urt,umsh-8596md-20t", 4717 .data = &urt_umsh_8596md_parallel, 4718 }, { 4719 .compatible = "vivax,tpc9150-panel", 4720 .data = &vivax_tpc9150_panel, 4721 }, { 4722 .compatible = "vxt,vl050-8048nt-c01", 4723 .data = &vl050_8048nt_c01, 4724 }, { 4725 .compatible = "winstar,wf35ltiacd", 4726 .data = &winstar_wf35ltiacd, 4727 }, { 4728 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 4729 .data = &yes_optoelectronics_ytc700tlag_05_201c, 4730 }, { 4731 /* Must be the last entry */ 4732 .compatible = "panel-dpi", 4733 .data = &panel_dpi, 4734 }, { 4735 /* sentinel */ 4736 } 4737 }; 4738 MODULE_DEVICE_TABLE(of, platform_of_match); 4739 4740 static int panel_simple_platform_probe(struct platform_device *pdev) 4741 { 4742 const struct panel_desc *desc; 4743 4744 desc = of_device_get_match_data(&pdev->dev); 4745 if (!desc) 4746 return -ENODEV; 4747 4748 return panel_simple_probe(&pdev->dev, desc); 4749 } 4750 4751 static void panel_simple_platform_remove(struct platform_device *pdev) 4752 { 4753 panel_simple_remove(&pdev->dev); 4754 } 4755 4756 static void panel_simple_platform_shutdown(struct platform_device *pdev) 4757 { 4758 panel_simple_shutdown(&pdev->dev); 4759 } 4760 4761 static const struct dev_pm_ops panel_simple_pm_ops = { 4762 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 4763 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 4764 pm_runtime_force_resume) 4765 }; 4766 4767 static struct platform_driver panel_simple_platform_driver = { 4768 .driver = { 4769 .name = "panel-simple", 4770 .of_match_table = platform_of_match, 4771 .pm = &panel_simple_pm_ops, 4772 }, 4773 .probe = panel_simple_platform_probe, 4774 .remove_new = panel_simple_platform_remove, 4775 .shutdown = panel_simple_platform_shutdown, 4776 }; 4777 4778 struct panel_desc_dsi { 4779 struct panel_desc desc; 4780 4781 unsigned long flags; 4782 enum mipi_dsi_pixel_format format; 4783 unsigned int lanes; 4784 }; 4785 4786 static const struct drm_display_mode auo_b080uan01_mode = { 4787 .clock = 154500, 4788 .hdisplay = 1200, 4789 .hsync_start = 1200 + 62, 4790 .hsync_end = 1200 + 62 + 4, 4791 .htotal = 1200 + 62 + 4 + 62, 4792 .vdisplay = 1920, 4793 .vsync_start = 1920 + 9, 4794 .vsync_end = 1920 + 9 + 2, 4795 .vtotal = 1920 + 9 + 2 + 8, 4796 }; 4797 4798 static const struct panel_desc_dsi auo_b080uan01 = { 4799 .desc = { 4800 .modes = &auo_b080uan01_mode, 4801 .num_modes = 1, 4802 .bpc = 8, 4803 .size = { 4804 .width = 108, 4805 .height = 272, 4806 }, 4807 .connector_type = DRM_MODE_CONNECTOR_DSI, 4808 }, 4809 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4810 .format = MIPI_DSI_FMT_RGB888, 4811 .lanes = 4, 4812 }; 4813 4814 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 4815 .clock = 160000, 4816 .hdisplay = 1200, 4817 .hsync_start = 1200 + 120, 4818 .hsync_end = 1200 + 120 + 20, 4819 .htotal = 1200 + 120 + 20 + 21, 4820 .vdisplay = 1920, 4821 .vsync_start = 1920 + 21, 4822 .vsync_end = 1920 + 21 + 3, 4823 .vtotal = 1920 + 21 + 3 + 18, 4824 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4825 }; 4826 4827 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 4828 .desc = { 4829 .modes = &boe_tv080wum_nl0_mode, 4830 .num_modes = 1, 4831 .size = { 4832 .width = 107, 4833 .height = 172, 4834 }, 4835 .connector_type = DRM_MODE_CONNECTOR_DSI, 4836 }, 4837 .flags = MIPI_DSI_MODE_VIDEO | 4838 MIPI_DSI_MODE_VIDEO_BURST | 4839 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 4840 .format = MIPI_DSI_FMT_RGB888, 4841 .lanes = 4, 4842 }; 4843 4844 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 4845 .clock = 71000, 4846 .hdisplay = 800, 4847 .hsync_start = 800 + 32, 4848 .hsync_end = 800 + 32 + 1, 4849 .htotal = 800 + 32 + 1 + 57, 4850 .vdisplay = 1280, 4851 .vsync_start = 1280 + 28, 4852 .vsync_end = 1280 + 28 + 1, 4853 .vtotal = 1280 + 28 + 1 + 14, 4854 }; 4855 4856 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 4857 .desc = { 4858 .modes = &lg_ld070wx3_sl01_mode, 4859 .num_modes = 1, 4860 .bpc = 8, 4861 .size = { 4862 .width = 94, 4863 .height = 151, 4864 }, 4865 .connector_type = DRM_MODE_CONNECTOR_DSI, 4866 }, 4867 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 4868 .format = MIPI_DSI_FMT_RGB888, 4869 .lanes = 4, 4870 }; 4871 4872 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 4873 .clock = 67000, 4874 .hdisplay = 720, 4875 .hsync_start = 720 + 12, 4876 .hsync_end = 720 + 12 + 4, 4877 .htotal = 720 + 12 + 4 + 112, 4878 .vdisplay = 1280, 4879 .vsync_start = 1280 + 8, 4880 .vsync_end = 1280 + 8 + 4, 4881 .vtotal = 1280 + 8 + 4 + 12, 4882 }; 4883 4884 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 4885 .desc = { 4886 .modes = &lg_lh500wx1_sd03_mode, 4887 .num_modes = 1, 4888 .bpc = 8, 4889 .size = { 4890 .width = 62, 4891 .height = 110, 4892 }, 4893 .connector_type = DRM_MODE_CONNECTOR_DSI, 4894 }, 4895 .flags = MIPI_DSI_MODE_VIDEO, 4896 .format = MIPI_DSI_FMT_RGB888, 4897 .lanes = 4, 4898 }; 4899 4900 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 4901 .clock = 157200, 4902 .hdisplay = 1920, 4903 .hsync_start = 1920 + 154, 4904 .hsync_end = 1920 + 154 + 16, 4905 .htotal = 1920 + 154 + 16 + 32, 4906 .vdisplay = 1200, 4907 .vsync_start = 1200 + 17, 4908 .vsync_end = 1200 + 17 + 2, 4909 .vtotal = 1200 + 17 + 2 + 16, 4910 }; 4911 4912 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 4913 .desc = { 4914 .modes = &panasonic_vvx10f004b00_mode, 4915 .num_modes = 1, 4916 .bpc = 8, 4917 .size = { 4918 .width = 217, 4919 .height = 136, 4920 }, 4921 .connector_type = DRM_MODE_CONNECTOR_DSI, 4922 }, 4923 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4924 MIPI_DSI_CLOCK_NON_CONTINUOUS, 4925 .format = MIPI_DSI_FMT_RGB888, 4926 .lanes = 4, 4927 }; 4928 4929 static const struct drm_display_mode lg_acx467akm_7_mode = { 4930 .clock = 150000, 4931 .hdisplay = 1080, 4932 .hsync_start = 1080 + 2, 4933 .hsync_end = 1080 + 2 + 2, 4934 .htotal = 1080 + 2 + 2 + 2, 4935 .vdisplay = 1920, 4936 .vsync_start = 1920 + 2, 4937 .vsync_end = 1920 + 2 + 2, 4938 .vtotal = 1920 + 2 + 2 + 2, 4939 }; 4940 4941 static const struct panel_desc_dsi lg_acx467akm_7 = { 4942 .desc = { 4943 .modes = &lg_acx467akm_7_mode, 4944 .num_modes = 1, 4945 .bpc = 8, 4946 .size = { 4947 .width = 62, 4948 .height = 110, 4949 }, 4950 .connector_type = DRM_MODE_CONNECTOR_DSI, 4951 }, 4952 .flags = 0, 4953 .format = MIPI_DSI_FMT_RGB888, 4954 .lanes = 4, 4955 }; 4956 4957 static const struct drm_display_mode osd101t2045_53ts_mode = { 4958 .clock = 154500, 4959 .hdisplay = 1920, 4960 .hsync_start = 1920 + 112, 4961 .hsync_end = 1920 + 112 + 16, 4962 .htotal = 1920 + 112 + 16 + 32, 4963 .vdisplay = 1200, 4964 .vsync_start = 1200 + 16, 4965 .vsync_end = 1200 + 16 + 2, 4966 .vtotal = 1200 + 16 + 2 + 16, 4967 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4968 }; 4969 4970 static const struct panel_desc_dsi osd101t2045_53ts = { 4971 .desc = { 4972 .modes = &osd101t2045_53ts_mode, 4973 .num_modes = 1, 4974 .bpc = 8, 4975 .size = { 4976 .width = 217, 4977 .height = 136, 4978 }, 4979 .connector_type = DRM_MODE_CONNECTOR_DSI, 4980 }, 4981 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4982 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 4983 MIPI_DSI_MODE_NO_EOT_PACKET, 4984 .format = MIPI_DSI_FMT_RGB888, 4985 .lanes = 4, 4986 }; 4987 4988 static const struct of_device_id dsi_of_match[] = { 4989 { 4990 .compatible = "auo,b080uan01", 4991 .data = &auo_b080uan01 4992 }, { 4993 .compatible = "boe,tv080wum-nl0", 4994 .data = &boe_tv080wum_nl0 4995 }, { 4996 .compatible = "lg,ld070wx3-sl01", 4997 .data = &lg_ld070wx3_sl01 4998 }, { 4999 .compatible = "lg,lh500wx1-sd03", 5000 .data = &lg_lh500wx1_sd03 5001 }, { 5002 .compatible = "panasonic,vvx10f004b00", 5003 .data = &panasonic_vvx10f004b00 5004 }, { 5005 .compatible = "lg,acx467akm-7", 5006 .data = &lg_acx467akm_7 5007 }, { 5008 .compatible = "osddisplays,osd101t2045-53ts", 5009 .data = &osd101t2045_53ts 5010 }, { 5011 /* sentinel */ 5012 } 5013 }; 5014 MODULE_DEVICE_TABLE(of, dsi_of_match); 5015 5016 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5017 { 5018 const struct panel_desc_dsi *desc; 5019 int err; 5020 5021 desc = of_device_get_match_data(&dsi->dev); 5022 if (!desc) 5023 return -ENODEV; 5024 5025 err = panel_simple_probe(&dsi->dev, &desc->desc); 5026 if (err < 0) 5027 return err; 5028 5029 dsi->mode_flags = desc->flags; 5030 dsi->format = desc->format; 5031 dsi->lanes = desc->lanes; 5032 5033 err = mipi_dsi_attach(dsi); 5034 if (err) { 5035 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5036 5037 drm_panel_remove(&panel->base); 5038 } 5039 5040 return err; 5041 } 5042 5043 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5044 { 5045 int err; 5046 5047 err = mipi_dsi_detach(dsi); 5048 if (err < 0) 5049 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5050 5051 panel_simple_remove(&dsi->dev); 5052 } 5053 5054 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5055 { 5056 panel_simple_shutdown(&dsi->dev); 5057 } 5058 5059 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5060 .driver = { 5061 .name = "panel-simple-dsi", 5062 .of_match_table = dsi_of_match, 5063 .pm = &panel_simple_pm_ops, 5064 }, 5065 .probe = panel_simple_dsi_probe, 5066 .remove = panel_simple_dsi_remove, 5067 .shutdown = panel_simple_dsi_shutdown, 5068 }; 5069 5070 static int __init panel_simple_init(void) 5071 { 5072 int err; 5073 5074 err = platform_driver_register(&panel_simple_platform_driver); 5075 if (err < 0) 5076 return err; 5077 5078 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5079 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5080 if (err < 0) 5081 goto err_did_platform_register; 5082 } 5083 5084 return 0; 5085 5086 err_did_platform_register: 5087 platform_driver_unregister(&panel_simple_platform_driver); 5088 5089 return err; 5090 } 5091 module_init(panel_simple_init); 5092 5093 static void __exit panel_simple_exit(void) 5094 { 5095 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5096 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5097 5098 platform_driver_unregister(&panel_simple_platform_driver); 5099 } 5100 module_exit(panel_simple_exit); 5101 5102 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5103 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5104 MODULE_LICENSE("GPL and additional rights"); 5105