1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) COPYRIGHT 2012-2013 ARM Limited. All rights reserved. 4 * 5 * Parts of this file were based on sources as follows: 6 * 7 * Copyright (c) 2006-2008 Intel Corporation 8 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 9 * Copyright (C) 2011 Texas Instruments 10 */ 11 12 #include <linux/amba/clcd-regs.h> 13 #include <linux/clk.h> 14 #include <linux/version.h> 15 #include <linux/dma-buf.h> 16 #include <linux/of_graph.h> 17 18 #include <drm/drmP.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_gem_framebuffer_helper.h> 21 #include <drm/drm_fb_cma_helper.h> 22 23 #include "pl111_drm.h" 24 25 irqreturn_t pl111_irq(int irq, void *data) 26 { 27 struct pl111_drm_dev_private *priv = data; 28 u32 irq_stat; 29 irqreturn_t status = IRQ_NONE; 30 31 irq_stat = readl(priv->regs + CLCD_PL111_MIS); 32 33 if (!irq_stat) 34 return IRQ_NONE; 35 36 if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) { 37 drm_crtc_handle_vblank(&priv->pipe.crtc); 38 39 status = IRQ_HANDLED; 40 } 41 42 /* Clear the interrupt once done */ 43 writel(irq_stat, priv->regs + CLCD_PL111_ICR); 44 45 return status; 46 } 47 48 static enum drm_mode_status 49 pl111_mode_valid(struct drm_crtc *crtc, 50 const struct drm_display_mode *mode) 51 { 52 struct drm_device *drm = crtc->dev; 53 struct pl111_drm_dev_private *priv = drm->dev_private; 54 u32 cpp = priv->variant->fb_bpp / 8; 55 u64 bw; 56 57 /* 58 * We use the pixelclock to also account for interlaced modes, the 59 * resulting bandwidth is in bytes per second. 60 */ 61 bw = mode->clock * 1000ULL; /* In Hz */ 62 bw = bw * mode->hdisplay * mode->vdisplay * cpp; 63 bw = div_u64(bw, mode->htotal * mode->vtotal); 64 65 /* 66 * If no bandwidth constraints, anything goes, else 67 * check if we are too fast. 68 */ 69 if (priv->memory_bw && (bw > priv->memory_bw)) { 70 DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu too fast\n", 71 mode->hdisplay, mode->vdisplay, 72 mode->clock * 1000, cpp, bw); 73 74 return MODE_BAD; 75 } 76 DRM_DEBUG_KMS("%d x %d @ %d Hz, %d cpp, bw %llu bytes/s OK\n", 77 mode->hdisplay, mode->vdisplay, 78 mode->clock * 1000, cpp, bw); 79 80 return MODE_OK; 81 } 82 83 static int pl111_display_check(struct drm_simple_display_pipe *pipe, 84 struct drm_plane_state *pstate, 85 struct drm_crtc_state *cstate) 86 { 87 const struct drm_display_mode *mode = &cstate->mode; 88 struct drm_framebuffer *old_fb = pipe->plane.state->fb; 89 struct drm_framebuffer *fb = pstate->fb; 90 91 if (mode->hdisplay % 16) 92 return -EINVAL; 93 94 if (fb) { 95 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0); 96 97 /* FB base address must be dword aligned. */ 98 if (offset & 3) 99 return -EINVAL; 100 101 /* There's no pitch register -- the mode's hdisplay 102 * controls it. 103 */ 104 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) 105 return -EINVAL; 106 107 /* We can't change the FB format in a flicker-free 108 * manner (and only update it during CRTC enable). 109 */ 110 if (old_fb && old_fb->format != fb->format) 111 cstate->mode_changed = true; 112 } 113 114 return 0; 115 } 116 117 static void pl111_display_enable(struct drm_simple_display_pipe *pipe, 118 struct drm_crtc_state *cstate, 119 struct drm_plane_state *plane_state) 120 { 121 struct drm_crtc *crtc = &pipe->crtc; 122 struct drm_plane *plane = &pipe->plane; 123 struct drm_device *drm = crtc->dev; 124 struct pl111_drm_dev_private *priv = drm->dev_private; 125 const struct drm_display_mode *mode = &cstate->mode; 126 struct drm_framebuffer *fb = plane->state->fb; 127 struct drm_connector *connector = priv->connector; 128 struct drm_bridge *bridge = priv->bridge; 129 u32 cntl; 130 u32 ppl, hsw, hfp, hbp; 131 u32 lpp, vsw, vfp, vbp; 132 u32 cpl, tim2; 133 int ret; 134 135 ret = clk_set_rate(priv->clk, mode->clock * 1000); 136 if (ret) { 137 dev_err(drm->dev, 138 "Failed to set pixel clock rate to %d: %d\n", 139 mode->clock * 1000, ret); 140 } 141 142 clk_prepare_enable(priv->clk); 143 144 ppl = (mode->hdisplay / 16) - 1; 145 hsw = mode->hsync_end - mode->hsync_start - 1; 146 hfp = mode->hsync_start - mode->hdisplay - 1; 147 hbp = mode->htotal - mode->hsync_end - 1; 148 149 lpp = mode->vdisplay - 1; 150 vsw = mode->vsync_end - mode->vsync_start - 1; 151 vfp = mode->vsync_start - mode->vdisplay; 152 vbp = mode->vtotal - mode->vsync_end; 153 154 cpl = mode->hdisplay - 1; 155 156 writel((ppl << 2) | 157 (hsw << 8) | 158 (hfp << 16) | 159 (hbp << 24), 160 priv->regs + CLCD_TIM0); 161 writel(lpp | 162 (vsw << 10) | 163 (vfp << 16) | 164 (vbp << 24), 165 priv->regs + CLCD_TIM1); 166 167 spin_lock(&priv->tim2_lock); 168 169 tim2 = readl(priv->regs + CLCD_TIM2); 170 tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); 171 172 if (priv->variant->broken_clockdivider) 173 tim2 |= TIM2_BCD; 174 175 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 176 tim2 |= TIM2_IHS; 177 178 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 179 tim2 |= TIM2_IVS; 180 181 if (connector) { 182 if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW) 183 tim2 |= TIM2_IOE; 184 185 if (connector->display_info.bus_flags & 186 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 187 tim2 |= TIM2_IPC; 188 } 189 190 if (bridge) { 191 const struct drm_bridge_timings *btimings = bridge->timings; 192 193 /* 194 * Here is when things get really fun. Sometimes the bridge 195 * timings are such that the signal out from PL11x is not 196 * stable before the receiving bridge (such as a dumb VGA DAC 197 * or similar) samples it. If that happens, we compensate by 198 * the only method we have: output the data on the opposite 199 * edge of the clock so it is for sure stable when it gets 200 * sampled. 201 * 202 * The PL111 manual does not contain proper timining diagrams 203 * or data for these details, but we know from experiments 204 * that the setup time is more than 3000 picoseconds (3 ns). 205 * If we have a bridge that requires the signal to be stable 206 * earlier than 3000 ps before the clock pulse, we have to 207 * output the data on the opposite edge to avoid flicker. 208 */ 209 if (btimings && btimings->setup_time_ps >= 3000) 210 tim2 ^= TIM2_IPC; 211 } 212 213 tim2 |= cpl << 16; 214 writel(tim2, priv->regs + CLCD_TIM2); 215 spin_unlock(&priv->tim2_lock); 216 217 writel(0, priv->regs + CLCD_TIM3); 218 219 /* Hard-code TFT panel */ 220 cntl = CNTL_LCDEN | CNTL_LCDTFT | CNTL_LCDVCOMP(1); 221 /* On the ST Micro variant, assume all 24 bits are connected */ 222 if (priv->variant->st_bitmux_control) 223 cntl |= CNTL_ST_CDWID_24; 224 225 /* 226 * Note that the the ARM hardware's format reader takes 'r' from 227 * the low bit, while DRM formats list channels from high bit 228 * to low bit as you read left to right. The ST Micro version of 229 * the PL110 (LCDC) however uses the standard DRM format. 230 */ 231 switch (fb->format->format) { 232 case DRM_FORMAT_BGR888: 233 /* Only supported on the ST Micro variant */ 234 if (priv->variant->st_bitmux_control) 235 cntl |= CNTL_ST_LCDBPP24_PACKED | CNTL_BGR; 236 break; 237 case DRM_FORMAT_RGB888: 238 /* Only supported on the ST Micro variant */ 239 if (priv->variant->st_bitmux_control) 240 cntl |= CNTL_ST_LCDBPP24_PACKED; 241 break; 242 case DRM_FORMAT_ABGR8888: 243 case DRM_FORMAT_XBGR8888: 244 if (priv->variant->st_bitmux_control) 245 cntl |= CNTL_LCDBPP24 | CNTL_BGR; 246 else 247 cntl |= CNTL_LCDBPP24; 248 break; 249 case DRM_FORMAT_ARGB8888: 250 case DRM_FORMAT_XRGB8888: 251 if (priv->variant->st_bitmux_control) 252 cntl |= CNTL_LCDBPP24; 253 else 254 cntl |= CNTL_LCDBPP24 | CNTL_BGR; 255 break; 256 case DRM_FORMAT_BGR565: 257 if (priv->variant->is_pl110) 258 cntl |= CNTL_LCDBPP16; 259 else if (priv->variant->st_bitmux_control) 260 cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565 | CNTL_BGR; 261 else 262 cntl |= CNTL_LCDBPP16_565; 263 break; 264 case DRM_FORMAT_RGB565: 265 if (priv->variant->is_pl110) 266 cntl |= CNTL_LCDBPP16 | CNTL_BGR; 267 else if (priv->variant->st_bitmux_control) 268 cntl |= CNTL_LCDBPP16 | CNTL_ST_1XBPP_565; 269 else 270 cntl |= CNTL_LCDBPP16_565 | CNTL_BGR; 271 break; 272 case DRM_FORMAT_ABGR1555: 273 case DRM_FORMAT_XBGR1555: 274 cntl |= CNTL_LCDBPP16; 275 if (priv->variant->st_bitmux_control) 276 cntl |= CNTL_ST_1XBPP_5551 | CNTL_BGR; 277 break; 278 case DRM_FORMAT_ARGB1555: 279 case DRM_FORMAT_XRGB1555: 280 cntl |= CNTL_LCDBPP16; 281 if (priv->variant->st_bitmux_control) 282 cntl |= CNTL_ST_1XBPP_5551; 283 else 284 cntl |= CNTL_BGR; 285 break; 286 case DRM_FORMAT_ABGR4444: 287 case DRM_FORMAT_XBGR4444: 288 cntl |= CNTL_LCDBPP16_444; 289 if (priv->variant->st_bitmux_control) 290 cntl |= CNTL_ST_1XBPP_444 | CNTL_BGR; 291 break; 292 case DRM_FORMAT_ARGB4444: 293 case DRM_FORMAT_XRGB4444: 294 cntl |= CNTL_LCDBPP16_444; 295 if (priv->variant->st_bitmux_control) 296 cntl |= CNTL_ST_1XBPP_444; 297 else 298 cntl |= CNTL_BGR; 299 break; 300 default: 301 WARN_ONCE(true, "Unknown FB format 0x%08x\n", 302 fb->format->format); 303 break; 304 } 305 306 /* The PL110 in Integrator/Versatile does the BGR routing externally */ 307 if (priv->variant->external_bgr) 308 cntl &= ~CNTL_BGR; 309 310 /* Power sequence: first enable and chill */ 311 writel(cntl, priv->regs + priv->ctrl); 312 313 /* 314 * We expect this delay to stabilize the contrast 315 * voltage Vee as stipulated by the manual 316 */ 317 msleep(20); 318 319 if (priv->variant_display_enable) 320 priv->variant_display_enable(drm, fb->format->format); 321 322 /* Power Up */ 323 cntl |= CNTL_LCDPWR; 324 writel(cntl, priv->regs + priv->ctrl); 325 326 if (!priv->variant->broken_vblank) 327 drm_crtc_vblank_on(crtc); 328 } 329 330 void pl111_display_disable(struct drm_simple_display_pipe *pipe) 331 { 332 struct drm_crtc *crtc = &pipe->crtc; 333 struct drm_device *drm = crtc->dev; 334 struct pl111_drm_dev_private *priv = drm->dev_private; 335 u32 cntl; 336 337 if (!priv->variant->broken_vblank) 338 drm_crtc_vblank_off(crtc); 339 340 /* Power Down */ 341 cntl = readl(priv->regs + priv->ctrl); 342 if (cntl & CNTL_LCDPWR) { 343 cntl &= ~CNTL_LCDPWR; 344 writel(cntl, priv->regs + priv->ctrl); 345 } 346 347 /* 348 * We expect this delay to stabilize the contrast voltage Vee as 349 * stipulated by the manual 350 */ 351 msleep(20); 352 353 if (priv->variant_display_disable) 354 priv->variant_display_disable(drm); 355 356 /* Disable */ 357 writel(0, priv->regs + priv->ctrl); 358 359 clk_disable_unprepare(priv->clk); 360 } 361 362 static void pl111_display_update(struct drm_simple_display_pipe *pipe, 363 struct drm_plane_state *old_pstate) 364 { 365 struct drm_crtc *crtc = &pipe->crtc; 366 struct drm_device *drm = crtc->dev; 367 struct pl111_drm_dev_private *priv = drm->dev_private; 368 struct drm_pending_vblank_event *event = crtc->state->event; 369 struct drm_plane *plane = &pipe->plane; 370 struct drm_plane_state *pstate = plane->state; 371 struct drm_framebuffer *fb = pstate->fb; 372 373 if (fb) { 374 u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0); 375 376 writel(addr, priv->regs + CLCD_UBAS); 377 } 378 379 if (event) { 380 crtc->state->event = NULL; 381 382 spin_lock_irq(&crtc->dev->event_lock); 383 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) 384 drm_crtc_arm_vblank_event(crtc, event); 385 else 386 drm_crtc_send_vblank_event(crtc, event); 387 spin_unlock_irq(&crtc->dev->event_lock); 388 } 389 } 390 391 static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pipe) 392 { 393 struct drm_crtc *crtc = &pipe->crtc; 394 struct drm_device *drm = crtc->dev; 395 struct pl111_drm_dev_private *priv = drm->dev_private; 396 397 writel(CLCD_IRQ_NEXTBASE_UPDATE, priv->regs + priv->ienb); 398 399 return 0; 400 } 401 402 static void pl111_display_disable_vblank(struct drm_simple_display_pipe *pipe) 403 { 404 struct drm_crtc *crtc = &pipe->crtc; 405 struct drm_device *drm = crtc->dev; 406 struct pl111_drm_dev_private *priv = drm->dev_private; 407 408 writel(0, priv->regs + priv->ienb); 409 } 410 411 static struct drm_simple_display_pipe_funcs pl111_display_funcs = { 412 .mode_valid = pl111_mode_valid, 413 .check = pl111_display_check, 414 .enable = pl111_display_enable, 415 .disable = pl111_display_disable, 416 .update = pl111_display_update, 417 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, 418 }; 419 420 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, 421 unsigned long *prate, bool set_parent) 422 { 423 int best_div = 1, div; 424 struct clk_hw *parent = clk_hw_get_parent(hw); 425 unsigned long best_prate = 0; 426 unsigned long best_diff = ~0ul; 427 int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1; 428 429 for (div = 1; div < max_div; div++) { 430 unsigned long this_prate, div_rate, diff; 431 432 if (set_parent) 433 this_prate = clk_hw_round_rate(parent, rate * div); 434 else 435 this_prate = *prate; 436 div_rate = DIV_ROUND_UP_ULL(this_prate, div); 437 diff = abs(rate - div_rate); 438 439 if (diff < best_diff) { 440 best_div = div; 441 best_diff = diff; 442 best_prate = this_prate; 443 } 444 } 445 446 *prate = best_prate; 447 return best_div; 448 } 449 450 static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 451 unsigned long *prate) 452 { 453 int div = pl111_clk_div_choose_div(hw, rate, prate, true); 454 455 return DIV_ROUND_UP_ULL(*prate, div); 456 } 457 458 static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw, 459 unsigned long prate) 460 { 461 struct pl111_drm_dev_private *priv = 462 container_of(hw, struct pl111_drm_dev_private, clk_div); 463 u32 tim2 = readl(priv->regs + CLCD_TIM2); 464 int div; 465 466 if (tim2 & TIM2_BCD) 467 return prate; 468 469 div = tim2 & TIM2_PCD_LO_MASK; 470 div |= (tim2 & TIM2_PCD_HI_MASK) >> 471 (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS); 472 div += 2; 473 474 return DIV_ROUND_UP_ULL(prate, div); 475 } 476 477 static int pl111_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 478 unsigned long prate) 479 { 480 struct pl111_drm_dev_private *priv = 481 container_of(hw, struct pl111_drm_dev_private, clk_div); 482 int div = pl111_clk_div_choose_div(hw, rate, &prate, false); 483 u32 tim2; 484 485 spin_lock(&priv->tim2_lock); 486 tim2 = readl(priv->regs + CLCD_TIM2); 487 tim2 &= ~(TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); 488 489 if (div == 1) { 490 tim2 |= TIM2_BCD; 491 } else { 492 div -= 2; 493 tim2 |= div & TIM2_PCD_LO_MASK; 494 tim2 |= (div >> TIM2_PCD_LO_BITS) << TIM2_PCD_HI_SHIFT; 495 } 496 497 writel(tim2, priv->regs + CLCD_TIM2); 498 spin_unlock(&priv->tim2_lock); 499 500 return 0; 501 } 502 503 static const struct clk_ops pl111_clk_div_ops = { 504 .recalc_rate = pl111_clk_div_recalc_rate, 505 .round_rate = pl111_clk_div_round_rate, 506 .set_rate = pl111_clk_div_set_rate, 507 }; 508 509 static int 510 pl111_init_clock_divider(struct drm_device *drm) 511 { 512 struct pl111_drm_dev_private *priv = drm->dev_private; 513 struct clk *parent = devm_clk_get(drm->dev, "clcdclk"); 514 struct clk_hw *div = &priv->clk_div; 515 const char *parent_name; 516 struct clk_init_data init = { 517 .name = "pl111_div", 518 .ops = &pl111_clk_div_ops, 519 .parent_names = &parent_name, 520 .num_parents = 1, 521 .flags = CLK_SET_RATE_PARENT, 522 }; 523 int ret; 524 525 if (IS_ERR(parent)) { 526 dev_err(drm->dev, "CLCD: unable to get clcdclk.\n"); 527 return PTR_ERR(parent); 528 } 529 530 spin_lock_init(&priv->tim2_lock); 531 532 /* If the clock divider is broken, use the parent directly */ 533 if (priv->variant->broken_clockdivider) { 534 priv->clk = parent; 535 return 0; 536 } 537 parent_name = __clk_get_name(parent); 538 div->init = &init; 539 540 ret = devm_clk_hw_register(drm->dev, div); 541 542 priv->clk = div->clk; 543 return ret; 544 } 545 546 int pl111_display_init(struct drm_device *drm) 547 { 548 struct pl111_drm_dev_private *priv = drm->dev_private; 549 struct device *dev = drm->dev; 550 struct device_node *endpoint; 551 u32 tft_r0b0g0[3]; 552 int ret; 553 554 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); 555 if (!endpoint) 556 return -ENODEV; 557 558 if (of_property_read_u32_array(endpoint, 559 "arm,pl11x,tft-r0g0b0-pads", 560 tft_r0b0g0, 561 ARRAY_SIZE(tft_r0b0g0)) != 0) { 562 dev_err(dev, "arm,pl11x,tft-r0g0b0-pads should be 3 ints\n"); 563 of_node_put(endpoint); 564 return -ENOENT; 565 } 566 of_node_put(endpoint); 567 568 ret = pl111_init_clock_divider(drm); 569 if (ret) 570 return ret; 571 572 if (!priv->variant->broken_vblank) { 573 pl111_display_funcs.enable_vblank = pl111_display_enable_vblank; 574 pl111_display_funcs.disable_vblank = pl111_display_disable_vblank; 575 } 576 577 ret = drm_simple_display_pipe_init(drm, &priv->pipe, 578 &pl111_display_funcs, 579 priv->variant->formats, 580 priv->variant->nformats, 581 NULL, 582 priv->connector); 583 if (ret) 584 return ret; 585 586 return 0; 587 } 588