1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_H__ 29 #define __RADEON_H__ 30 31 /* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45 /* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63 #include <linux/atomic.h> 64 #include <linux/wait.h> 65 #include <linux/list.h> 66 #include <linux/kref.h> 67 #include <linux/interval_tree.h> 68 #include <linux/hashtable.h> 69 #include <linux/dma-fence.h> 70 71 #include <drm/ttm/ttm_bo_api.h> 72 #include <drm/ttm/ttm_bo_driver.h> 73 #include <drm/ttm/ttm_placement.h> 74 #include <drm/ttm/ttm_module.h> 75 #include <drm/ttm/ttm_execbuf_util.h> 76 77 #include <drm/drm_gem.h> 78 79 #include "radeon_family.h" 80 #include "radeon_mode.h" 81 #include "radeon_reg.h" 82 83 /* 84 * Modules parameters. 85 */ 86 extern int radeon_no_wb; 87 extern int radeon_modeset; 88 extern int radeon_dynclks; 89 extern int radeon_r4xx_atom; 90 extern int radeon_agpmode; 91 extern int radeon_vram_limit; 92 extern int radeon_gart_size; 93 extern int radeon_benchmarking; 94 extern int radeon_testing; 95 extern int radeon_connector_table; 96 extern int radeon_tv; 97 extern int radeon_audio; 98 extern int radeon_disp_priority; 99 extern int radeon_hw_i2c; 100 extern int radeon_pcie_gen2; 101 extern int radeon_msi; 102 extern int radeon_lockup_timeout; 103 extern int radeon_fastfb; 104 extern int radeon_dpm; 105 extern int radeon_aspm; 106 extern int radeon_runtime_pm; 107 extern int radeon_hard_reset; 108 extern int radeon_vm_size; 109 extern int radeon_vm_block_size; 110 extern int radeon_deep_color; 111 extern int radeon_use_pflipirq; 112 extern int radeon_bapm; 113 extern int radeon_backlight; 114 extern int radeon_auxch; 115 extern int radeon_mst; 116 extern int radeon_uvd; 117 extern int radeon_vce; 118 extern int radeon_si_support; 119 extern int radeon_cik_support; 120 121 /* 122 * Copy from radeon_drv.h so we don't have to include both and have conflicting 123 * symbol; 124 */ 125 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 126 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 127 #define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */ 128 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 129 #define RADEON_IB_POOL_SIZE 16 130 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 131 #define RADEONFB_CONN_LIMIT 4 132 #define RADEON_BIOS_NUM_SCRATCH 8 133 134 /* internal ring indices */ 135 /* r1xx+ has gfx CP ring */ 136 #define RADEON_RING_TYPE_GFX_INDEX 0 137 138 /* cayman has 2 compute CP rings */ 139 #define CAYMAN_RING_TYPE_CP1_INDEX 1 140 #define CAYMAN_RING_TYPE_CP2_INDEX 2 141 142 /* R600+ has an async dma ring */ 143 #define R600_RING_TYPE_DMA_INDEX 3 144 /* cayman add a second async dma ring */ 145 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 146 147 /* R600+ */ 148 #define R600_RING_TYPE_UVD_INDEX 5 149 150 /* TN+ */ 151 #define TN_RING_TYPE_VCE1_INDEX 6 152 #define TN_RING_TYPE_VCE2_INDEX 7 153 154 /* max number of rings */ 155 #define RADEON_NUM_RINGS 8 156 157 /* number of hw syncs before falling back on blocking */ 158 #define RADEON_NUM_SYNCS 4 159 160 /* hardcode those limit for now */ 161 #define RADEON_VA_IB_OFFSET (1 << 20) 162 #define RADEON_VA_RESERVED_SIZE (8 << 20) 163 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 164 165 /* hard reset data */ 166 #define RADEON_ASIC_RESET_DATA 0x39d5e86b 167 168 /* reset flags */ 169 #define RADEON_RESET_GFX (1 << 0) 170 #define RADEON_RESET_COMPUTE (1 << 1) 171 #define RADEON_RESET_DMA (1 << 2) 172 #define RADEON_RESET_CP (1 << 3) 173 #define RADEON_RESET_GRBM (1 << 4) 174 #define RADEON_RESET_DMA1 (1 << 5) 175 #define RADEON_RESET_RLC (1 << 6) 176 #define RADEON_RESET_SEM (1 << 7) 177 #define RADEON_RESET_IH (1 << 8) 178 #define RADEON_RESET_VMC (1 << 9) 179 #define RADEON_RESET_MC (1 << 10) 180 #define RADEON_RESET_DISPLAY (1 << 11) 181 182 /* CG block flags */ 183 #define RADEON_CG_BLOCK_GFX (1 << 0) 184 #define RADEON_CG_BLOCK_MC (1 << 1) 185 #define RADEON_CG_BLOCK_SDMA (1 << 2) 186 #define RADEON_CG_BLOCK_UVD (1 << 3) 187 #define RADEON_CG_BLOCK_VCE (1 << 4) 188 #define RADEON_CG_BLOCK_HDP (1 << 5) 189 #define RADEON_CG_BLOCK_BIF (1 << 6) 190 191 /* CG flags */ 192 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 193 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 194 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 195 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 196 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 197 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 198 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 199 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 200 #define RADEON_CG_SUPPORT_MC_LS (1 << 8) 201 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 202 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 203 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 204 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 205 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 206 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 207 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 208 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 209 210 /* PG flags */ 211 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 212 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 213 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 214 #define RADEON_PG_SUPPORT_UVD (1 << 3) 215 #define RADEON_PG_SUPPORT_VCE (1 << 4) 216 #define RADEON_PG_SUPPORT_CP (1 << 5) 217 #define RADEON_PG_SUPPORT_GDS (1 << 6) 218 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 219 #define RADEON_PG_SUPPORT_SDMA (1 << 8) 220 #define RADEON_PG_SUPPORT_ACP (1 << 9) 221 #define RADEON_PG_SUPPORT_SAMU (1 << 10) 222 223 /* max cursor sizes (in pixels) */ 224 #define CURSOR_WIDTH 64 225 #define CURSOR_HEIGHT 64 226 227 #define CIK_CURSOR_WIDTH 128 228 #define CIK_CURSOR_HEIGHT 128 229 230 /* 231 * Errata workarounds. 232 */ 233 enum radeon_pll_errata { 234 CHIP_ERRATA_R300_CG = 0x00000001, 235 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 236 CHIP_ERRATA_PLL_DELAY = 0x00000004 237 }; 238 239 240 struct radeon_device; 241 242 243 /* 244 * BIOS. 245 */ 246 bool radeon_get_bios(struct radeon_device *rdev); 247 248 /* 249 * Dummy page 250 */ 251 struct radeon_dummy_page { 252 uint64_t entry; 253 struct page *page; 254 dma_addr_t addr; 255 }; 256 int radeon_dummy_page_init(struct radeon_device *rdev); 257 void radeon_dummy_page_fini(struct radeon_device *rdev); 258 259 260 /* 261 * Clocks 262 */ 263 struct radeon_clock { 264 struct radeon_pll p1pll; 265 struct radeon_pll p2pll; 266 struct radeon_pll dcpll; 267 struct radeon_pll spll; 268 struct radeon_pll mpll; 269 /* 10 Khz units */ 270 uint32_t default_mclk; 271 uint32_t default_sclk; 272 uint32_t default_dispclk; 273 uint32_t current_dispclk; 274 uint32_t dp_extclk; 275 uint32_t max_pixel_clock; 276 uint32_t vco_freq; 277 }; 278 279 /* 280 * Power management 281 */ 282 int radeon_pm_init(struct radeon_device *rdev); 283 int radeon_pm_late_init(struct radeon_device *rdev); 284 void radeon_pm_fini(struct radeon_device *rdev); 285 void radeon_pm_compute_clocks(struct radeon_device *rdev); 286 void radeon_pm_suspend(struct radeon_device *rdev); 287 void radeon_pm_resume(struct radeon_device *rdev); 288 void radeon_combios_get_power_modes(struct radeon_device *rdev); 289 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 290 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 291 u8 clock_type, 292 u32 clock, 293 bool strobe_mode, 294 struct atom_clock_dividers *dividers); 295 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 296 u32 clock, 297 bool strobe_mode, 298 struct atom_mpll_param *mpll_param); 299 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 300 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 301 u16 voltage_level, u8 voltage_type, 302 u32 *gpio_value, u32 *gpio_mask); 303 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 304 u32 eng_clock, u32 mem_clock); 305 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 306 u8 voltage_type, u16 *voltage_step); 307 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 308 u16 voltage_id, u16 *voltage); 309 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 310 u16 *voltage, 311 u16 leakage_idx); 312 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 313 u16 *leakage_id); 314 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 315 u16 *vddc, u16 *vddci, 316 u16 virtual_voltage_id, 317 u16 vbios_voltage_id); 318 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 319 u16 virtual_voltage_id, 320 u16 *voltage); 321 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 322 u8 voltage_type, 323 u16 nominal_voltage, 324 u16 *true_voltage); 325 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 326 u8 voltage_type, u16 *min_voltage); 327 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 328 u8 voltage_type, u16 *max_voltage); 329 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 330 u8 voltage_type, u8 voltage_mode, 331 struct atom_voltage_table *voltage_table); 332 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 333 u8 voltage_type, u8 voltage_mode); 334 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 335 u8 voltage_type, 336 u8 *svd_gpio_id, u8 *svc_gpio_id); 337 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 338 u32 mem_clock); 339 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 340 u32 mem_clock); 341 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 342 u8 module_index, 343 struct atom_mc_reg_table *reg_table); 344 int radeon_atom_get_memory_info(struct radeon_device *rdev, 345 u8 module_index, struct atom_memory_info *mem_info); 346 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 347 bool gddr5, u8 module_index, 348 struct atom_memory_clock_range_table *mclk_range_table); 349 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 350 u16 voltage_id, u16 *voltage); 351 void rs690_pm_info(struct radeon_device *rdev); 352 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 353 unsigned *bankh, unsigned *mtaspect, 354 unsigned *tile_split); 355 356 /* 357 * Fences. 358 */ 359 struct radeon_fence_driver { 360 struct radeon_device *rdev; 361 uint32_t scratch_reg; 362 uint64_t gpu_addr; 363 volatile uint32_t *cpu_addr; 364 /* sync_seq is protected by ring emission lock */ 365 uint64_t sync_seq[RADEON_NUM_RINGS]; 366 atomic64_t last_seq; 367 bool initialized, delayed_irq; 368 struct delayed_work lockup_work; 369 }; 370 371 struct radeon_fence { 372 struct dma_fence base; 373 374 struct radeon_device *rdev; 375 uint64_t seq; 376 /* RB, DMA, etc. */ 377 unsigned ring; 378 bool is_vm_update; 379 380 wait_queue_entry_t fence_wake; 381 }; 382 383 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 384 int radeon_fence_driver_init(struct radeon_device *rdev); 385 void radeon_fence_driver_fini(struct radeon_device *rdev); 386 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 387 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 388 void radeon_fence_process(struct radeon_device *rdev, int ring); 389 bool radeon_fence_signaled(struct radeon_fence *fence); 390 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout); 391 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 392 int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 393 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 394 int radeon_fence_wait_any(struct radeon_device *rdev, 395 struct radeon_fence **fences, 396 bool intr); 397 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 398 void radeon_fence_unref(struct radeon_fence **fence); 399 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 400 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 401 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 402 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 403 struct radeon_fence *b) 404 { 405 if (!a) { 406 return b; 407 } 408 409 if (!b) { 410 return a; 411 } 412 413 BUG_ON(a->ring != b->ring); 414 415 if (a->seq > b->seq) { 416 return a; 417 } else { 418 return b; 419 } 420 } 421 422 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 423 struct radeon_fence *b) 424 { 425 if (!a) { 426 return false; 427 } 428 429 if (!b) { 430 return true; 431 } 432 433 BUG_ON(a->ring != b->ring); 434 435 return a->seq < b->seq; 436 } 437 438 /* 439 * Tiling registers 440 */ 441 struct radeon_surface_reg { 442 struct radeon_bo *bo; 443 }; 444 445 #define RADEON_GEM_MAX_SURFACES 8 446 447 /* 448 * TTM. 449 */ 450 struct radeon_mman { 451 struct ttm_bo_device bdev; 452 bool initialized; 453 454 #if defined(CONFIG_DEBUG_FS) 455 struct dentry *vram; 456 struct dentry *gtt; 457 #endif 458 }; 459 460 struct radeon_bo_list { 461 struct radeon_bo *robj; 462 struct ttm_validate_buffer tv; 463 uint64_t gpu_offset; 464 unsigned preferred_domains; 465 unsigned allowed_domains; 466 uint32_t tiling_flags; 467 }; 468 469 /* bo virtual address in a specific vm */ 470 struct radeon_bo_va { 471 /* protected by bo being reserved */ 472 struct list_head bo_list; 473 uint32_t flags; 474 struct radeon_fence *last_pt_update; 475 unsigned ref_count; 476 477 /* protected by vm mutex */ 478 struct interval_tree_node it; 479 struct list_head vm_status; 480 481 /* constant after initialization */ 482 struct radeon_vm *vm; 483 struct radeon_bo *bo; 484 }; 485 486 struct radeon_bo { 487 /* Protected by gem.mutex */ 488 struct list_head list; 489 /* Protected by tbo.reserved */ 490 u32 initial_domain; 491 struct ttm_place placements[4]; 492 struct ttm_placement placement; 493 struct ttm_buffer_object tbo; 494 struct ttm_bo_kmap_obj kmap; 495 u32 flags; 496 unsigned pin_count; 497 void *kptr; 498 u32 tiling_flags; 499 u32 pitch; 500 int surface_reg; 501 unsigned prime_shared_count; 502 /* list of all virtual address to which this bo 503 * is associated to 504 */ 505 struct list_head va; 506 /* Constant after initialization */ 507 struct radeon_device *rdev; 508 509 struct ttm_bo_kmap_obj dma_buf_vmap; 510 pid_t pid; 511 512 struct radeon_mn *mn; 513 struct list_head mn_list; 514 }; 515 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base) 516 517 int radeon_gem_debugfs_init(struct radeon_device *rdev); 518 519 /* sub-allocation manager, it has to be protected by another lock. 520 * By conception this is an helper for other part of the driver 521 * like the indirect buffer or semaphore, which both have their 522 * locking. 523 * 524 * Principe is simple, we keep a list of sub allocation in offset 525 * order (first entry has offset == 0, last entry has the highest 526 * offset). 527 * 528 * When allocating new object we first check if there is room at 529 * the end total_size - (last_object_offset + last_object_size) >= 530 * alloc_size. If so we allocate new object there. 531 * 532 * When there is not enough room at the end, we start waiting for 533 * each sub object until we reach object_offset+object_size >= 534 * alloc_size, this object then become the sub object we return. 535 * 536 * Alignment can't be bigger than page size. 537 * 538 * Hole are not considered for allocation to keep things simple. 539 * Assumption is that there won't be hole (all object on same 540 * alignment). 541 */ 542 struct radeon_sa_manager { 543 wait_queue_head_t wq; 544 struct radeon_bo *bo; 545 struct list_head *hole; 546 struct list_head flist[RADEON_NUM_RINGS]; 547 struct list_head olist; 548 unsigned size; 549 uint64_t gpu_addr; 550 void *cpu_ptr; 551 uint32_t domain; 552 uint32_t align; 553 }; 554 555 struct radeon_sa_bo; 556 557 /* sub-allocation buffer */ 558 struct radeon_sa_bo { 559 struct list_head olist; 560 struct list_head flist; 561 struct radeon_sa_manager *manager; 562 unsigned soffset; 563 unsigned eoffset; 564 struct radeon_fence *fence; 565 }; 566 567 /* 568 * GEM objects. 569 */ 570 struct radeon_gem { 571 struct mutex mutex; 572 struct list_head objects; 573 }; 574 575 int radeon_gem_init(struct radeon_device *rdev); 576 void radeon_gem_fini(struct radeon_device *rdev); 577 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 578 int alignment, int initial_domain, 579 u32 flags, bool kernel, 580 struct drm_gem_object **obj); 581 582 int radeon_mode_dumb_create(struct drm_file *file_priv, 583 struct drm_device *dev, 584 struct drm_mode_create_dumb *args); 585 int radeon_mode_dumb_mmap(struct drm_file *filp, 586 struct drm_device *dev, 587 uint32_t handle, uint64_t *offset_p); 588 589 /* 590 * Semaphores. 591 */ 592 struct radeon_semaphore { 593 struct radeon_sa_bo *sa_bo; 594 signed waiters; 595 uint64_t gpu_addr; 596 }; 597 598 int radeon_semaphore_create(struct radeon_device *rdev, 599 struct radeon_semaphore **semaphore); 600 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 601 struct radeon_semaphore *semaphore); 602 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 603 struct radeon_semaphore *semaphore); 604 void radeon_semaphore_free(struct radeon_device *rdev, 605 struct radeon_semaphore **semaphore, 606 struct radeon_fence *fence); 607 608 /* 609 * Synchronization 610 */ 611 struct radeon_sync { 612 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 613 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 614 struct radeon_fence *last_vm_update; 615 }; 616 617 void radeon_sync_create(struct radeon_sync *sync); 618 void radeon_sync_fence(struct radeon_sync *sync, 619 struct radeon_fence *fence); 620 int radeon_sync_resv(struct radeon_device *rdev, 621 struct radeon_sync *sync, 622 struct dma_resv *resv, 623 bool shared); 624 int radeon_sync_rings(struct radeon_device *rdev, 625 struct radeon_sync *sync, 626 int waiting_ring); 627 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 628 struct radeon_fence *fence); 629 630 /* 631 * GART structures, functions & helpers 632 */ 633 struct radeon_mc; 634 635 #define RADEON_GPU_PAGE_SIZE 4096 636 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 637 #define RADEON_GPU_PAGE_SHIFT 12 638 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 639 640 #define RADEON_GART_PAGE_DUMMY 0 641 #define RADEON_GART_PAGE_VALID (1 << 0) 642 #define RADEON_GART_PAGE_READ (1 << 1) 643 #define RADEON_GART_PAGE_WRITE (1 << 2) 644 #define RADEON_GART_PAGE_SNOOP (1 << 3) 645 646 struct radeon_gart { 647 dma_addr_t table_addr; 648 struct radeon_bo *robj; 649 void *ptr; 650 unsigned num_gpu_pages; 651 unsigned num_cpu_pages; 652 unsigned table_size; 653 struct page **pages; 654 uint64_t *pages_entry; 655 bool ready; 656 }; 657 658 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 659 void radeon_gart_table_ram_free(struct radeon_device *rdev); 660 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 661 void radeon_gart_table_vram_free(struct radeon_device *rdev); 662 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 663 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 664 int radeon_gart_init(struct radeon_device *rdev); 665 void radeon_gart_fini(struct radeon_device *rdev); 666 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 667 int pages); 668 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 669 int pages, struct page **pagelist, 670 dma_addr_t *dma_addr, uint32_t flags); 671 672 673 /* 674 * GPU MC structures, functions & helpers 675 */ 676 struct radeon_mc { 677 resource_size_t aper_size; 678 resource_size_t aper_base; 679 resource_size_t agp_base; 680 /* for some chips with <= 32MB we need to lie 681 * about vram size near mc fb location */ 682 u64 mc_vram_size; 683 u64 visible_vram_size; 684 u64 gtt_size; 685 u64 gtt_start; 686 u64 gtt_end; 687 u64 vram_start; 688 u64 vram_end; 689 unsigned vram_width; 690 u64 real_vram_size; 691 int vram_mtrr; 692 bool vram_is_ddr; 693 bool igp_sideport_enabled; 694 u64 gtt_base_align; 695 u64 mc_mask; 696 }; 697 698 bool radeon_combios_sideport_present(struct radeon_device *rdev); 699 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 700 701 /* 702 * GPU scratch registers structures, functions & helpers 703 */ 704 struct radeon_scratch { 705 unsigned num_reg; 706 uint32_t reg_base; 707 bool free[32]; 708 uint32_t reg[32]; 709 }; 710 711 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 712 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 713 714 /* 715 * GPU doorbell structures, functions & helpers 716 */ 717 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 718 719 struct radeon_doorbell { 720 /* doorbell mmio */ 721 resource_size_t base; 722 resource_size_t size; 723 u32 __iomem *ptr; 724 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 725 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS); 726 }; 727 728 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 729 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 730 731 /* 732 * IRQS. 733 */ 734 735 struct radeon_flip_work { 736 struct work_struct flip_work; 737 struct work_struct unpin_work; 738 struct radeon_device *rdev; 739 int crtc_id; 740 u32 target_vblank; 741 uint64_t base; 742 struct drm_pending_vblank_event *event; 743 struct radeon_bo *old_rbo; 744 struct dma_fence *fence; 745 bool async; 746 }; 747 748 struct r500_irq_stat_regs { 749 u32 disp_int; 750 u32 hdmi0_status; 751 }; 752 753 struct r600_irq_stat_regs { 754 u32 disp_int; 755 u32 disp_int_cont; 756 u32 disp_int_cont2; 757 u32 d1grph_int; 758 u32 d2grph_int; 759 u32 hdmi0_status; 760 u32 hdmi1_status; 761 }; 762 763 struct evergreen_irq_stat_regs { 764 u32 disp_int[6]; 765 u32 grph_int[6]; 766 u32 afmt_status[6]; 767 }; 768 769 struct cik_irq_stat_regs { 770 u32 disp_int; 771 u32 disp_int_cont; 772 u32 disp_int_cont2; 773 u32 disp_int_cont3; 774 u32 disp_int_cont4; 775 u32 disp_int_cont5; 776 u32 disp_int_cont6; 777 u32 d1grph_int; 778 u32 d2grph_int; 779 u32 d3grph_int; 780 u32 d4grph_int; 781 u32 d5grph_int; 782 u32 d6grph_int; 783 }; 784 785 union radeon_irq_stat_regs { 786 struct r500_irq_stat_regs r500; 787 struct r600_irq_stat_regs r600; 788 struct evergreen_irq_stat_regs evergreen; 789 struct cik_irq_stat_regs cik; 790 }; 791 792 struct radeon_irq { 793 bool installed; 794 spinlock_t lock; 795 atomic_t ring_int[RADEON_NUM_RINGS]; 796 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 797 atomic_t pflip[RADEON_MAX_CRTCS]; 798 wait_queue_head_t vblank_queue; 799 bool hpd[RADEON_MAX_HPD_PINS]; 800 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 801 union radeon_irq_stat_regs stat_regs; 802 bool dpm_thermal; 803 }; 804 805 int radeon_irq_kms_init(struct radeon_device *rdev); 806 void radeon_irq_kms_fini(struct radeon_device *rdev); 807 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 808 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 809 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 810 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 811 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 812 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 813 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 814 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 815 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 816 817 /* 818 * CP & rings. 819 */ 820 821 struct radeon_ib { 822 struct radeon_sa_bo *sa_bo; 823 uint32_t length_dw; 824 uint64_t gpu_addr; 825 uint32_t *ptr; 826 int ring; 827 struct radeon_fence *fence; 828 struct radeon_vm *vm; 829 bool is_const_ib; 830 struct radeon_sync sync; 831 }; 832 833 struct radeon_ring { 834 struct radeon_bo *ring_obj; 835 volatile uint32_t *ring; 836 unsigned rptr_offs; 837 unsigned rptr_save_reg; 838 u64 next_rptr_gpu_addr; 839 volatile u32 *next_rptr_cpu_addr; 840 unsigned wptr; 841 unsigned wptr_old; 842 unsigned ring_size; 843 unsigned ring_free_dw; 844 int count_dw; 845 atomic_t last_rptr; 846 atomic64_t last_activity; 847 uint64_t gpu_addr; 848 uint32_t align_mask; 849 uint32_t ptr_mask; 850 bool ready; 851 u32 nop; 852 u32 idx; 853 u64 last_semaphore_signal_addr; 854 u64 last_semaphore_wait_addr; 855 /* for CIK queues */ 856 u32 me; 857 u32 pipe; 858 u32 queue; 859 struct radeon_bo *mqd_obj; 860 u32 doorbell_index; 861 unsigned wptr_offs; 862 }; 863 864 struct radeon_mec { 865 struct radeon_bo *hpd_eop_obj; 866 u64 hpd_eop_gpu_addr; 867 u32 num_pipe; 868 u32 num_mec; 869 u32 num_queue; 870 }; 871 872 /* 873 * VM 874 */ 875 876 /* maximum number of VMIDs */ 877 #define RADEON_NUM_VM 16 878 879 /* number of entries in page table */ 880 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 881 882 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 883 #define RADEON_VM_PTB_ALIGN_SIZE 32768 884 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 885 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 886 887 #define R600_PTE_VALID (1 << 0) 888 #define R600_PTE_SYSTEM (1 << 1) 889 #define R600_PTE_SNOOPED (1 << 2) 890 #define R600_PTE_READABLE (1 << 5) 891 #define R600_PTE_WRITEABLE (1 << 6) 892 893 /* PTE (Page Table Entry) fragment field for different page sizes */ 894 #define R600_PTE_FRAG_4KB (0 << 7) 895 #define R600_PTE_FRAG_64KB (4 << 7) 896 #define R600_PTE_FRAG_256KB (6 << 7) 897 898 /* flags needed to be set so we can copy directly from the GART table */ 899 #define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 900 R600_PTE_SYSTEM | R600_PTE_VALID ) 901 902 struct radeon_vm_pt { 903 struct radeon_bo *bo; 904 uint64_t addr; 905 }; 906 907 struct radeon_vm_id { 908 unsigned id; 909 uint64_t pd_gpu_addr; 910 /* last flushed PD/PT update */ 911 struct radeon_fence *flushed_updates; 912 /* last use of vmid */ 913 struct radeon_fence *last_id_use; 914 }; 915 916 struct radeon_vm { 917 struct mutex mutex; 918 919 struct rb_root_cached va; 920 921 /* protecting invalidated and freed */ 922 spinlock_t status_lock; 923 924 /* BOs moved, but not yet updated in the PT */ 925 struct list_head invalidated; 926 927 /* BOs freed, but not yet updated in the PT */ 928 struct list_head freed; 929 930 /* BOs cleared in the PT */ 931 struct list_head cleared; 932 933 /* contains the page directory */ 934 struct radeon_bo *page_directory; 935 unsigned max_pde_used; 936 937 /* array of page tables, one for each page directory entry */ 938 struct radeon_vm_pt *page_tables; 939 940 struct radeon_bo_va *ib_bo_va; 941 942 /* for id and flush management per ring */ 943 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 944 }; 945 946 struct radeon_vm_manager { 947 struct radeon_fence *active[RADEON_NUM_VM]; 948 uint32_t max_pfn; 949 /* number of VMIDs */ 950 unsigned nvm; 951 /* vram base address for page table entry */ 952 u64 vram_base_offset; 953 /* is vm enabled? */ 954 bool enabled; 955 /* for hw to save the PD addr on suspend/resume */ 956 uint32_t saved_table_addr[RADEON_NUM_VM]; 957 }; 958 959 /* 960 * file private structure 961 */ 962 struct radeon_fpriv { 963 struct radeon_vm vm; 964 }; 965 966 /* 967 * R6xx+ IH ring 968 */ 969 struct r600_ih { 970 struct radeon_bo *ring_obj; 971 volatile uint32_t *ring; 972 unsigned rptr; 973 unsigned ring_size; 974 uint64_t gpu_addr; 975 uint32_t ptr_mask; 976 atomic_t lock; 977 bool enabled; 978 }; 979 980 /* 981 * RLC stuff 982 */ 983 #include "clearstate_defs.h" 984 985 struct radeon_rlc { 986 /* for power gating */ 987 struct radeon_bo *save_restore_obj; 988 uint64_t save_restore_gpu_addr; 989 volatile uint32_t *sr_ptr; 990 const u32 *reg_list; 991 u32 reg_list_size; 992 /* for clear state */ 993 struct radeon_bo *clear_state_obj; 994 uint64_t clear_state_gpu_addr; 995 volatile uint32_t *cs_ptr; 996 const struct cs_section_def *cs_data; 997 u32 clear_state_size; 998 /* for cp tables */ 999 struct radeon_bo *cp_table_obj; 1000 uint64_t cp_table_gpu_addr; 1001 volatile uint32_t *cp_table_ptr; 1002 u32 cp_table_size; 1003 }; 1004 1005 int radeon_ib_get(struct radeon_device *rdev, int ring, 1006 struct radeon_ib *ib, struct radeon_vm *vm, 1007 unsigned size); 1008 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1009 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1010 struct radeon_ib *const_ib, bool hdp_flush); 1011 int radeon_ib_pool_init(struct radeon_device *rdev); 1012 void radeon_ib_pool_fini(struct radeon_device *rdev); 1013 int radeon_ib_ring_tests(struct radeon_device *rdev); 1014 /* Ring access between begin & end cannot sleep */ 1015 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1016 struct radeon_ring *ring); 1017 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1018 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1019 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1020 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1021 bool hdp_flush); 1022 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1023 bool hdp_flush); 1024 void radeon_ring_undo(struct radeon_ring *ring); 1025 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1026 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1027 void radeon_ring_lockup_update(struct radeon_device *rdev, 1028 struct radeon_ring *ring); 1029 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1030 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1031 uint32_t **data); 1032 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1033 unsigned size, uint32_t *data); 1034 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1035 unsigned rptr_offs, u32 nop); 1036 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1037 1038 1039 /* r600 async dma */ 1040 void r600_dma_stop(struct radeon_device *rdev); 1041 int r600_dma_resume(struct radeon_device *rdev); 1042 void r600_dma_fini(struct radeon_device *rdev); 1043 1044 void cayman_dma_stop(struct radeon_device *rdev); 1045 int cayman_dma_resume(struct radeon_device *rdev); 1046 void cayman_dma_fini(struct radeon_device *rdev); 1047 1048 /* 1049 * CS. 1050 */ 1051 struct radeon_cs_chunk { 1052 uint32_t length_dw; 1053 uint32_t *kdata; 1054 void __user *user_ptr; 1055 }; 1056 1057 struct radeon_cs_parser { 1058 struct device *dev; 1059 struct radeon_device *rdev; 1060 struct drm_file *filp; 1061 /* chunks */ 1062 unsigned nchunks; 1063 struct radeon_cs_chunk *chunks; 1064 uint64_t *chunks_array; 1065 /* IB */ 1066 unsigned idx; 1067 /* relocations */ 1068 unsigned nrelocs; 1069 struct radeon_bo_list *relocs; 1070 struct radeon_bo_list *vm_bos; 1071 struct list_head validated; 1072 unsigned dma_reloc_idx; 1073 /* indices of various chunks */ 1074 struct radeon_cs_chunk *chunk_ib; 1075 struct radeon_cs_chunk *chunk_relocs; 1076 struct radeon_cs_chunk *chunk_flags; 1077 struct radeon_cs_chunk *chunk_const_ib; 1078 struct radeon_ib ib; 1079 struct radeon_ib const_ib; 1080 void *track; 1081 unsigned family; 1082 int parser_error; 1083 u32 cs_flags; 1084 u32 ring; 1085 s32 priority; 1086 struct ww_acquire_ctx ticket; 1087 }; 1088 1089 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1090 { 1091 struct radeon_cs_chunk *ibc = p->chunk_ib; 1092 1093 if (ibc->kdata) 1094 return ibc->kdata[idx]; 1095 return p->ib.ptr[idx]; 1096 } 1097 1098 1099 struct radeon_cs_packet { 1100 unsigned idx; 1101 unsigned type; 1102 unsigned reg; 1103 unsigned opcode; 1104 int count; 1105 unsigned one_reg_wr; 1106 }; 1107 1108 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1109 struct radeon_cs_packet *pkt, 1110 unsigned idx, unsigned reg); 1111 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1112 struct radeon_cs_packet *pkt); 1113 1114 1115 /* 1116 * AGP 1117 */ 1118 int radeon_agp_init(struct radeon_device *rdev); 1119 void radeon_agp_resume(struct radeon_device *rdev); 1120 void radeon_agp_suspend(struct radeon_device *rdev); 1121 void radeon_agp_fini(struct radeon_device *rdev); 1122 1123 1124 /* 1125 * Writeback 1126 */ 1127 struct radeon_wb { 1128 struct radeon_bo *wb_obj; 1129 volatile uint32_t *wb; 1130 uint64_t gpu_addr; 1131 bool enabled; 1132 bool use_event; 1133 }; 1134 1135 #define RADEON_WB_SCRATCH_OFFSET 0 1136 #define RADEON_WB_RING0_NEXT_RPTR 256 1137 #define RADEON_WB_CP_RPTR_OFFSET 1024 1138 #define RADEON_WB_CP1_RPTR_OFFSET 1280 1139 #define RADEON_WB_CP2_RPTR_OFFSET 1536 1140 #define R600_WB_DMA_RPTR_OFFSET 1792 1141 #define R600_WB_IH_WPTR_OFFSET 2048 1142 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1143 #define R600_WB_EVENT_OFFSET 3072 1144 #define CIK_WB_CP1_WPTR_OFFSET 3328 1145 #define CIK_WB_CP2_WPTR_OFFSET 3584 1146 #define R600_WB_DMA_RING_TEST_OFFSET 3588 1147 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1148 1149 /** 1150 * struct radeon_pm - power management datas 1151 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1152 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1153 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1154 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1155 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1156 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1157 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1158 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1159 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1160 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1161 * @needed_bandwidth: current bandwidth needs 1162 * 1163 * It keeps track of various data needed to take powermanagement decision. 1164 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1165 * Equation between gpu/memory clock and available bandwidth is hw dependent 1166 * (type of memory, bus size, efficiency, ...) 1167 */ 1168 1169 enum radeon_pm_method { 1170 PM_METHOD_PROFILE, 1171 PM_METHOD_DYNPM, 1172 PM_METHOD_DPM, 1173 }; 1174 1175 enum radeon_dynpm_state { 1176 DYNPM_STATE_DISABLED, 1177 DYNPM_STATE_MINIMUM, 1178 DYNPM_STATE_PAUSED, 1179 DYNPM_STATE_ACTIVE, 1180 DYNPM_STATE_SUSPENDED, 1181 }; 1182 enum radeon_dynpm_action { 1183 DYNPM_ACTION_NONE, 1184 DYNPM_ACTION_MINIMUM, 1185 DYNPM_ACTION_DOWNCLOCK, 1186 DYNPM_ACTION_UPCLOCK, 1187 DYNPM_ACTION_DEFAULT 1188 }; 1189 1190 enum radeon_voltage_type { 1191 VOLTAGE_NONE = 0, 1192 VOLTAGE_GPIO, 1193 VOLTAGE_VDDC, 1194 VOLTAGE_SW 1195 }; 1196 1197 enum radeon_pm_state_type { 1198 /* not used for dpm */ 1199 POWER_STATE_TYPE_DEFAULT, 1200 POWER_STATE_TYPE_POWERSAVE, 1201 /* user selectable states */ 1202 POWER_STATE_TYPE_BATTERY, 1203 POWER_STATE_TYPE_BALANCED, 1204 POWER_STATE_TYPE_PERFORMANCE, 1205 /* internal states */ 1206 POWER_STATE_TYPE_INTERNAL_UVD, 1207 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1208 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1209 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1210 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1211 POWER_STATE_TYPE_INTERNAL_BOOT, 1212 POWER_STATE_TYPE_INTERNAL_THERMAL, 1213 POWER_STATE_TYPE_INTERNAL_ACPI, 1214 POWER_STATE_TYPE_INTERNAL_ULV, 1215 POWER_STATE_TYPE_INTERNAL_3DPERF, 1216 }; 1217 1218 enum radeon_pm_profile_type { 1219 PM_PROFILE_DEFAULT, 1220 PM_PROFILE_AUTO, 1221 PM_PROFILE_LOW, 1222 PM_PROFILE_MID, 1223 PM_PROFILE_HIGH, 1224 }; 1225 1226 #define PM_PROFILE_DEFAULT_IDX 0 1227 #define PM_PROFILE_LOW_SH_IDX 1 1228 #define PM_PROFILE_MID_SH_IDX 2 1229 #define PM_PROFILE_HIGH_SH_IDX 3 1230 #define PM_PROFILE_LOW_MH_IDX 4 1231 #define PM_PROFILE_MID_MH_IDX 5 1232 #define PM_PROFILE_HIGH_MH_IDX 6 1233 #define PM_PROFILE_MAX 7 1234 1235 struct radeon_pm_profile { 1236 int dpms_off_ps_idx; 1237 int dpms_on_ps_idx; 1238 int dpms_off_cm_idx; 1239 int dpms_on_cm_idx; 1240 }; 1241 1242 enum radeon_int_thermal_type { 1243 THERMAL_TYPE_NONE, 1244 THERMAL_TYPE_EXTERNAL, 1245 THERMAL_TYPE_EXTERNAL_GPIO, 1246 THERMAL_TYPE_RV6XX, 1247 THERMAL_TYPE_RV770, 1248 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1249 THERMAL_TYPE_EVERGREEN, 1250 THERMAL_TYPE_SUMO, 1251 THERMAL_TYPE_NI, 1252 THERMAL_TYPE_SI, 1253 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1254 THERMAL_TYPE_CI, 1255 THERMAL_TYPE_KV, 1256 }; 1257 1258 struct radeon_voltage { 1259 enum radeon_voltage_type type; 1260 /* gpio voltage */ 1261 struct radeon_gpio_rec gpio; 1262 u32 delay; /* delay in usec from voltage drop to sclk change */ 1263 bool active_high; /* voltage drop is active when bit is high */ 1264 /* VDDC voltage */ 1265 u8 vddc_id; /* index into vddc voltage table */ 1266 u8 vddci_id; /* index into vddci voltage table */ 1267 bool vddci_enabled; 1268 /* r6xx+ sw */ 1269 u16 voltage; 1270 /* evergreen+ vddci */ 1271 u16 vddci; 1272 }; 1273 1274 /* clock mode flags */ 1275 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1276 1277 struct radeon_pm_clock_info { 1278 /* memory clock */ 1279 u32 mclk; 1280 /* engine clock */ 1281 u32 sclk; 1282 /* voltage info */ 1283 struct radeon_voltage voltage; 1284 /* standardized clock flags */ 1285 u32 flags; 1286 }; 1287 1288 /* state flags */ 1289 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1290 1291 struct radeon_power_state { 1292 enum radeon_pm_state_type type; 1293 struct radeon_pm_clock_info *clock_info; 1294 /* number of valid clock modes in this power state */ 1295 int num_clock_modes; 1296 struct radeon_pm_clock_info *default_clock_mode; 1297 /* standardized state flags */ 1298 u32 flags; 1299 u32 misc; /* vbios specific flags */ 1300 u32 misc2; /* vbios specific flags */ 1301 int pcie_lanes; /* pcie lanes */ 1302 }; 1303 1304 /* 1305 * Some modes are overclocked by very low value, accept them 1306 */ 1307 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1308 1309 enum radeon_dpm_auto_throttle_src { 1310 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1311 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1312 }; 1313 1314 enum radeon_dpm_event_src { 1315 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1316 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1317 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1318 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1319 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1320 }; 1321 1322 #define RADEON_MAX_VCE_LEVELS 6 1323 1324 enum radeon_vce_level { 1325 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1326 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1327 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1328 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1329 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1330 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1331 }; 1332 1333 struct radeon_ps { 1334 u32 caps; /* vbios flags */ 1335 u32 class; /* vbios flags */ 1336 u32 class2; /* vbios flags */ 1337 /* UVD clocks */ 1338 u32 vclk; 1339 u32 dclk; 1340 /* VCE clocks */ 1341 u32 evclk; 1342 u32 ecclk; 1343 bool vce_active; 1344 enum radeon_vce_level vce_level; 1345 /* asic priv */ 1346 void *ps_priv; 1347 }; 1348 1349 struct radeon_dpm_thermal { 1350 /* thermal interrupt work */ 1351 struct work_struct work; 1352 /* low temperature threshold */ 1353 int min_temp; 1354 /* high temperature threshold */ 1355 int max_temp; 1356 /* was interrupt low to high or high to low */ 1357 bool high_to_low; 1358 }; 1359 1360 enum radeon_clk_action 1361 { 1362 RADEON_SCLK_UP = 1, 1363 RADEON_SCLK_DOWN 1364 }; 1365 1366 struct radeon_blacklist_clocks 1367 { 1368 u32 sclk; 1369 u32 mclk; 1370 enum radeon_clk_action action; 1371 }; 1372 1373 struct radeon_clock_and_voltage_limits { 1374 u32 sclk; 1375 u32 mclk; 1376 u16 vddc; 1377 u16 vddci; 1378 }; 1379 1380 struct radeon_clock_array { 1381 u32 count; 1382 u32 *values; 1383 }; 1384 1385 struct radeon_clock_voltage_dependency_entry { 1386 u32 clk; 1387 u16 v; 1388 }; 1389 1390 struct radeon_clock_voltage_dependency_table { 1391 u32 count; 1392 struct radeon_clock_voltage_dependency_entry *entries; 1393 }; 1394 1395 union radeon_cac_leakage_entry { 1396 struct { 1397 u16 vddc; 1398 u32 leakage; 1399 }; 1400 struct { 1401 u16 vddc1; 1402 u16 vddc2; 1403 u16 vddc3; 1404 }; 1405 }; 1406 1407 struct radeon_cac_leakage_table { 1408 u32 count; 1409 union radeon_cac_leakage_entry *entries; 1410 }; 1411 1412 struct radeon_phase_shedding_limits_entry { 1413 u16 voltage; 1414 u32 sclk; 1415 u32 mclk; 1416 }; 1417 1418 struct radeon_phase_shedding_limits_table { 1419 u32 count; 1420 struct radeon_phase_shedding_limits_entry *entries; 1421 }; 1422 1423 struct radeon_uvd_clock_voltage_dependency_entry { 1424 u32 vclk; 1425 u32 dclk; 1426 u16 v; 1427 }; 1428 1429 struct radeon_uvd_clock_voltage_dependency_table { 1430 u8 count; 1431 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1432 }; 1433 1434 struct radeon_vce_clock_voltage_dependency_entry { 1435 u32 ecclk; 1436 u32 evclk; 1437 u16 v; 1438 }; 1439 1440 struct radeon_vce_clock_voltage_dependency_table { 1441 u8 count; 1442 struct radeon_vce_clock_voltage_dependency_entry *entries; 1443 }; 1444 1445 struct radeon_ppm_table { 1446 u8 ppm_design; 1447 u16 cpu_core_number; 1448 u32 platform_tdp; 1449 u32 small_ac_platform_tdp; 1450 u32 platform_tdc; 1451 u32 small_ac_platform_tdc; 1452 u32 apu_tdp; 1453 u32 dgpu_tdp; 1454 u32 dgpu_ulv_power; 1455 u32 tj_max; 1456 }; 1457 1458 struct radeon_cac_tdp_table { 1459 u16 tdp; 1460 u16 configurable_tdp; 1461 u16 tdc; 1462 u16 battery_power_limit; 1463 u16 small_power_limit; 1464 u16 low_cac_leakage; 1465 u16 high_cac_leakage; 1466 u16 maximum_power_delivery_limit; 1467 }; 1468 1469 struct radeon_dpm_dynamic_state { 1470 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1471 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1472 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1473 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1474 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1475 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1476 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1477 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1478 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1479 struct radeon_clock_array valid_sclk_values; 1480 struct radeon_clock_array valid_mclk_values; 1481 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1482 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1483 u32 mclk_sclk_ratio; 1484 u32 sclk_mclk_delta; 1485 u16 vddc_vddci_delta; 1486 u16 min_vddc_for_pcie_gen2; 1487 struct radeon_cac_leakage_table cac_leakage_table; 1488 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1489 struct radeon_ppm_table *ppm_table; 1490 struct radeon_cac_tdp_table *cac_tdp_table; 1491 }; 1492 1493 struct radeon_dpm_fan { 1494 u16 t_min; 1495 u16 t_med; 1496 u16 t_high; 1497 u16 pwm_min; 1498 u16 pwm_med; 1499 u16 pwm_high; 1500 u8 t_hyst; 1501 u32 cycle_delay; 1502 u16 t_max; 1503 u8 control_mode; 1504 u16 default_max_fan_pwm; 1505 u16 default_fan_output_sensitivity; 1506 u16 fan_output_sensitivity; 1507 bool ucode_fan_control; 1508 }; 1509 1510 enum radeon_pcie_gen { 1511 RADEON_PCIE_GEN1 = 0, 1512 RADEON_PCIE_GEN2 = 1, 1513 RADEON_PCIE_GEN3 = 2, 1514 RADEON_PCIE_GEN_INVALID = 0xffff 1515 }; 1516 1517 enum radeon_dpm_forced_level { 1518 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1519 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1520 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1521 }; 1522 1523 struct radeon_vce_state { 1524 /* vce clocks */ 1525 u32 evclk; 1526 u32 ecclk; 1527 /* gpu clocks */ 1528 u32 sclk; 1529 u32 mclk; 1530 u8 clk_idx; 1531 u8 pstate; 1532 }; 1533 1534 struct radeon_dpm { 1535 struct radeon_ps *ps; 1536 /* number of valid power states */ 1537 int num_ps; 1538 /* current power state that is active */ 1539 struct radeon_ps *current_ps; 1540 /* requested power state */ 1541 struct radeon_ps *requested_ps; 1542 /* boot up power state */ 1543 struct radeon_ps *boot_ps; 1544 /* default uvd power state */ 1545 struct radeon_ps *uvd_ps; 1546 /* vce requirements */ 1547 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1548 enum radeon_vce_level vce_level; 1549 enum radeon_pm_state_type state; 1550 enum radeon_pm_state_type user_state; 1551 u32 platform_caps; 1552 u32 voltage_response_time; 1553 u32 backbias_response_time; 1554 void *priv; 1555 u32 new_active_crtcs; 1556 int new_active_crtc_count; 1557 u32 current_active_crtcs; 1558 int current_active_crtc_count; 1559 bool single_display; 1560 struct radeon_dpm_dynamic_state dyn_state; 1561 struct radeon_dpm_fan fan; 1562 u32 tdp_limit; 1563 u32 near_tdp_limit; 1564 u32 near_tdp_limit_adjusted; 1565 u32 sq_ramping_threshold; 1566 u32 cac_leakage; 1567 u16 tdp_od_limit; 1568 u32 tdp_adjustment; 1569 u16 load_line_slope; 1570 bool power_control; 1571 bool ac_power; 1572 /* special states active */ 1573 bool thermal_active; 1574 bool uvd_active; 1575 bool vce_active; 1576 /* thermal handling */ 1577 struct radeon_dpm_thermal thermal; 1578 /* forced levels */ 1579 enum radeon_dpm_forced_level forced_level; 1580 /* track UVD streams */ 1581 unsigned sd; 1582 unsigned hd; 1583 }; 1584 1585 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1586 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1587 1588 struct radeon_pm { 1589 struct mutex mutex; 1590 /* write locked while reprogramming mclk */ 1591 struct rw_semaphore mclk_lock; 1592 u32 active_crtcs; 1593 int active_crtc_count; 1594 int req_vblank; 1595 bool vblank_sync; 1596 fixed20_12 max_bandwidth; 1597 fixed20_12 igp_sideport_mclk; 1598 fixed20_12 igp_system_mclk; 1599 fixed20_12 igp_ht_link_clk; 1600 fixed20_12 igp_ht_link_width; 1601 fixed20_12 k8_bandwidth; 1602 fixed20_12 sideport_bandwidth; 1603 fixed20_12 ht_bandwidth; 1604 fixed20_12 core_bandwidth; 1605 fixed20_12 sclk; 1606 fixed20_12 mclk; 1607 fixed20_12 needed_bandwidth; 1608 struct radeon_power_state *power_state; 1609 /* number of valid power states */ 1610 int num_power_states; 1611 int current_power_state_index; 1612 int current_clock_mode_index; 1613 int requested_power_state_index; 1614 int requested_clock_mode_index; 1615 int default_power_state_index; 1616 u32 current_sclk; 1617 u32 current_mclk; 1618 u16 current_vddc; 1619 u16 current_vddci; 1620 u32 default_sclk; 1621 u32 default_mclk; 1622 u16 default_vddc; 1623 u16 default_vddci; 1624 struct radeon_i2c_chan *i2c_bus; 1625 /* selected pm method */ 1626 enum radeon_pm_method pm_method; 1627 /* dynpm power management */ 1628 struct delayed_work dynpm_idle_work; 1629 enum radeon_dynpm_state dynpm_state; 1630 enum radeon_dynpm_action dynpm_planned_action; 1631 unsigned long dynpm_action_timeout; 1632 bool dynpm_can_upclock; 1633 bool dynpm_can_downclock; 1634 /* profile-based power management */ 1635 enum radeon_pm_profile_type profile; 1636 int profile_index; 1637 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1638 /* internal thermal controller on rv6xx+ */ 1639 enum radeon_int_thermal_type int_thermal_type; 1640 struct device *int_hwmon_dev; 1641 /* fan control parameters */ 1642 bool no_fan; 1643 u8 fan_pulses_per_revolution; 1644 u8 fan_min_rpm; 1645 u8 fan_max_rpm; 1646 /* dpm */ 1647 bool dpm_enabled; 1648 bool sysfs_initialized; 1649 struct radeon_dpm dpm; 1650 }; 1651 1652 #define RADEON_PCIE_SPEED_25 1 1653 #define RADEON_PCIE_SPEED_50 2 1654 #define RADEON_PCIE_SPEED_80 4 1655 1656 int radeon_pm_get_type_index(struct radeon_device *rdev, 1657 enum radeon_pm_state_type ps_type, 1658 int instance); 1659 /* 1660 * UVD 1661 */ 1662 #define RADEON_DEFAULT_UVD_HANDLES 10 1663 #define RADEON_MAX_UVD_HANDLES 30 1664 #define RADEON_UVD_STACK_SIZE (200*1024) 1665 #define RADEON_UVD_HEAP_SIZE (256*1024) 1666 #define RADEON_UVD_SESSION_SIZE (50*1024) 1667 1668 struct radeon_uvd { 1669 bool fw_header_present; 1670 struct radeon_bo *vcpu_bo; 1671 void *cpu_addr; 1672 uint64_t gpu_addr; 1673 unsigned max_handles; 1674 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1675 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1676 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1677 struct delayed_work idle_work; 1678 }; 1679 1680 int radeon_uvd_init(struct radeon_device *rdev); 1681 void radeon_uvd_fini(struct radeon_device *rdev); 1682 int radeon_uvd_suspend(struct radeon_device *rdev); 1683 int radeon_uvd_resume(struct radeon_device *rdev); 1684 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1685 uint32_t handle, struct radeon_fence **fence); 1686 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1687 uint32_t handle, struct radeon_fence **fence); 1688 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1689 uint32_t allowed_domains); 1690 void radeon_uvd_free_handles(struct radeon_device *rdev, 1691 struct drm_file *filp); 1692 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1693 void radeon_uvd_note_usage(struct radeon_device *rdev); 1694 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1695 unsigned vclk, unsigned dclk, 1696 unsigned vco_min, unsigned vco_max, 1697 unsigned fb_factor, unsigned fb_mask, 1698 unsigned pd_min, unsigned pd_max, 1699 unsigned pd_even, 1700 unsigned *optimal_fb_div, 1701 unsigned *optimal_vclk_div, 1702 unsigned *optimal_dclk_div); 1703 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1704 unsigned cg_upll_func_cntl); 1705 1706 /* 1707 * VCE 1708 */ 1709 #define RADEON_MAX_VCE_HANDLES 16 1710 1711 struct radeon_vce { 1712 struct radeon_bo *vcpu_bo; 1713 uint64_t gpu_addr; 1714 unsigned fw_version; 1715 unsigned fb_version; 1716 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1717 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1718 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1719 struct delayed_work idle_work; 1720 uint32_t keyselect; 1721 }; 1722 1723 int radeon_vce_init(struct radeon_device *rdev); 1724 void radeon_vce_fini(struct radeon_device *rdev); 1725 int radeon_vce_suspend(struct radeon_device *rdev); 1726 int radeon_vce_resume(struct radeon_device *rdev); 1727 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1728 uint32_t handle, struct radeon_fence **fence); 1729 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1730 uint32_t handle, struct radeon_fence **fence); 1731 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1732 void radeon_vce_note_usage(struct radeon_device *rdev); 1733 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1734 int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1735 bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1736 struct radeon_ring *ring, 1737 struct radeon_semaphore *semaphore, 1738 bool emit_wait); 1739 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1740 void radeon_vce_fence_emit(struct radeon_device *rdev, 1741 struct radeon_fence *fence); 1742 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1743 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1744 1745 struct r600_audio_pin { 1746 int channels; 1747 int rate; 1748 int bits_per_sample; 1749 u8 status_bits; 1750 u8 category_code; 1751 u32 offset; 1752 bool connected; 1753 u32 id; 1754 }; 1755 1756 struct r600_audio { 1757 bool enabled; 1758 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1759 int num_pins; 1760 struct radeon_audio_funcs *hdmi_funcs; 1761 struct radeon_audio_funcs *dp_funcs; 1762 struct radeon_audio_basic_funcs *funcs; 1763 }; 1764 1765 /* 1766 * Benchmarking 1767 */ 1768 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1769 1770 1771 /* 1772 * Testing 1773 */ 1774 void radeon_test_moves(struct radeon_device *rdev); 1775 void radeon_test_ring_sync(struct radeon_device *rdev, 1776 struct radeon_ring *cpA, 1777 struct radeon_ring *cpB); 1778 void radeon_test_syncing(struct radeon_device *rdev); 1779 1780 /* 1781 * MMU Notifier 1782 */ 1783 #if defined(CONFIG_MMU_NOTIFIER) 1784 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1785 void radeon_mn_unregister(struct radeon_bo *bo); 1786 #else 1787 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1788 { 1789 return -ENODEV; 1790 } 1791 static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1792 #endif 1793 1794 /* 1795 * Debugfs 1796 */ 1797 struct radeon_debugfs { 1798 struct drm_info_list *files; 1799 unsigned num_files; 1800 }; 1801 1802 int radeon_debugfs_add_files(struct radeon_device *rdev, 1803 struct drm_info_list *files, 1804 unsigned nfiles); 1805 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1806 1807 /* 1808 * ASIC ring specific functions. 1809 */ 1810 struct radeon_asic_ring { 1811 /* ring read/write ptr handling */ 1812 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1813 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1814 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1815 1816 /* validating and patching of IBs */ 1817 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1818 int (*cs_parse)(struct radeon_cs_parser *p); 1819 1820 /* command emmit functions */ 1821 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1822 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1823 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1824 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1825 struct radeon_semaphore *semaphore, bool emit_wait); 1826 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1827 unsigned vm_id, uint64_t pd_addr); 1828 1829 /* testing functions */ 1830 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1831 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1832 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1833 1834 /* deprecated */ 1835 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1836 }; 1837 1838 /* 1839 * ASIC specific functions. 1840 */ 1841 struct radeon_asic { 1842 int (*init)(struct radeon_device *rdev); 1843 void (*fini)(struct radeon_device *rdev); 1844 int (*resume)(struct radeon_device *rdev); 1845 int (*suspend)(struct radeon_device *rdev); 1846 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1847 int (*asic_reset)(struct radeon_device *rdev, bool hard); 1848 /* Flush the HDP cache via MMIO */ 1849 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1850 /* check if 3D engine is idle */ 1851 bool (*gui_idle)(struct radeon_device *rdev); 1852 /* wait for mc_idle */ 1853 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1854 /* get the reference clock */ 1855 u32 (*get_xclk)(struct radeon_device *rdev); 1856 /* get the gpu clock counter */ 1857 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1858 /* get register for info ioctl */ 1859 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1860 /* gart */ 1861 struct { 1862 void (*tlb_flush)(struct radeon_device *rdev); 1863 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1864 void (*set_page)(struct radeon_device *rdev, unsigned i, 1865 uint64_t entry); 1866 } gart; 1867 struct { 1868 int (*init)(struct radeon_device *rdev); 1869 void (*fini)(struct radeon_device *rdev); 1870 void (*copy_pages)(struct radeon_device *rdev, 1871 struct radeon_ib *ib, 1872 uint64_t pe, uint64_t src, 1873 unsigned count); 1874 void (*write_pages)(struct radeon_device *rdev, 1875 struct radeon_ib *ib, 1876 uint64_t pe, 1877 uint64_t addr, unsigned count, 1878 uint32_t incr, uint32_t flags); 1879 void (*set_pages)(struct radeon_device *rdev, 1880 struct radeon_ib *ib, 1881 uint64_t pe, 1882 uint64_t addr, unsigned count, 1883 uint32_t incr, uint32_t flags); 1884 void (*pad_ib)(struct radeon_ib *ib); 1885 } vm; 1886 /* ring specific callbacks */ 1887 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1888 /* irqs */ 1889 struct { 1890 int (*set)(struct radeon_device *rdev); 1891 int (*process)(struct radeon_device *rdev); 1892 } irq; 1893 /* displays */ 1894 struct { 1895 /* display watermarks */ 1896 void (*bandwidth_update)(struct radeon_device *rdev); 1897 /* get frame count */ 1898 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1899 /* wait for vblank */ 1900 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1901 /* set backlight level */ 1902 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1903 /* get backlight level */ 1904 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1905 /* audio callbacks */ 1906 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1907 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1908 } display; 1909 /* copy functions for bo handling */ 1910 struct { 1911 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1912 uint64_t src_offset, 1913 uint64_t dst_offset, 1914 unsigned num_gpu_pages, 1915 struct dma_resv *resv); 1916 u32 blit_ring_index; 1917 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1918 uint64_t src_offset, 1919 uint64_t dst_offset, 1920 unsigned num_gpu_pages, 1921 struct dma_resv *resv); 1922 u32 dma_ring_index; 1923 /* method used for bo copy */ 1924 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1925 uint64_t src_offset, 1926 uint64_t dst_offset, 1927 unsigned num_gpu_pages, 1928 struct dma_resv *resv); 1929 /* ring used for bo copies */ 1930 u32 copy_ring_index; 1931 } copy; 1932 /* surfaces */ 1933 struct { 1934 int (*set_reg)(struct radeon_device *rdev, int reg, 1935 uint32_t tiling_flags, uint32_t pitch, 1936 uint32_t offset, uint32_t obj_size); 1937 void (*clear_reg)(struct radeon_device *rdev, int reg); 1938 } surface; 1939 /* hotplug detect */ 1940 struct { 1941 void (*init)(struct radeon_device *rdev); 1942 void (*fini)(struct radeon_device *rdev); 1943 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1944 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1945 } hpd; 1946 /* static power management */ 1947 struct { 1948 void (*misc)(struct radeon_device *rdev); 1949 void (*prepare)(struct radeon_device *rdev); 1950 void (*finish)(struct radeon_device *rdev); 1951 void (*init_profile)(struct radeon_device *rdev); 1952 void (*get_dynpm_state)(struct radeon_device *rdev); 1953 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1954 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1955 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1956 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1957 int (*get_pcie_lanes)(struct radeon_device *rdev); 1958 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1959 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1960 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1961 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1962 int (*get_temperature)(struct radeon_device *rdev); 1963 } pm; 1964 /* dynamic power management */ 1965 struct { 1966 int (*init)(struct radeon_device *rdev); 1967 void (*setup_asic)(struct radeon_device *rdev); 1968 int (*enable)(struct radeon_device *rdev); 1969 int (*late_enable)(struct radeon_device *rdev); 1970 void (*disable)(struct radeon_device *rdev); 1971 int (*pre_set_power_state)(struct radeon_device *rdev); 1972 int (*set_power_state)(struct radeon_device *rdev); 1973 void (*post_set_power_state)(struct radeon_device *rdev); 1974 void (*display_configuration_changed)(struct radeon_device *rdev); 1975 void (*fini)(struct radeon_device *rdev); 1976 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1977 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1978 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1979 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1980 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1981 bool (*vblank_too_short)(struct radeon_device *rdev); 1982 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1983 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1984 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1985 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1986 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1987 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1988 u32 (*get_current_sclk)(struct radeon_device *rdev); 1989 u32 (*get_current_mclk)(struct radeon_device *rdev); 1990 } dpm; 1991 /* pageflipping */ 1992 struct { 1993 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async); 1994 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 1995 } pflip; 1996 }; 1997 1998 /* 1999 * Asic structures 2000 */ 2001 struct r100_asic { 2002 const unsigned *reg_safe_bm; 2003 unsigned reg_safe_bm_size; 2004 u32 hdp_cntl; 2005 }; 2006 2007 struct r300_asic { 2008 const unsigned *reg_safe_bm; 2009 unsigned reg_safe_bm_size; 2010 u32 resync_scratch; 2011 u32 hdp_cntl; 2012 }; 2013 2014 struct r600_asic { 2015 unsigned max_pipes; 2016 unsigned max_tile_pipes; 2017 unsigned max_simds; 2018 unsigned max_backends; 2019 unsigned max_gprs; 2020 unsigned max_threads; 2021 unsigned max_stack_entries; 2022 unsigned max_hw_contexts; 2023 unsigned max_gs_threads; 2024 unsigned sx_max_export_size; 2025 unsigned sx_max_export_pos_size; 2026 unsigned sx_max_export_smx_size; 2027 unsigned sq_num_cf_insts; 2028 unsigned tiling_nbanks; 2029 unsigned tiling_npipes; 2030 unsigned tiling_group_size; 2031 unsigned tile_config; 2032 unsigned backend_map; 2033 unsigned active_simds; 2034 }; 2035 2036 struct rv770_asic { 2037 unsigned max_pipes; 2038 unsigned max_tile_pipes; 2039 unsigned max_simds; 2040 unsigned max_backends; 2041 unsigned max_gprs; 2042 unsigned max_threads; 2043 unsigned max_stack_entries; 2044 unsigned max_hw_contexts; 2045 unsigned max_gs_threads; 2046 unsigned sx_max_export_size; 2047 unsigned sx_max_export_pos_size; 2048 unsigned sx_max_export_smx_size; 2049 unsigned sq_num_cf_insts; 2050 unsigned sx_num_of_sets; 2051 unsigned sc_prim_fifo_size; 2052 unsigned sc_hiz_tile_fifo_size; 2053 unsigned sc_earlyz_tile_fifo_fize; 2054 unsigned tiling_nbanks; 2055 unsigned tiling_npipes; 2056 unsigned tiling_group_size; 2057 unsigned tile_config; 2058 unsigned backend_map; 2059 unsigned active_simds; 2060 }; 2061 2062 struct evergreen_asic { 2063 unsigned num_ses; 2064 unsigned max_pipes; 2065 unsigned max_tile_pipes; 2066 unsigned max_simds; 2067 unsigned max_backends; 2068 unsigned max_gprs; 2069 unsigned max_threads; 2070 unsigned max_stack_entries; 2071 unsigned max_hw_contexts; 2072 unsigned max_gs_threads; 2073 unsigned sx_max_export_size; 2074 unsigned sx_max_export_pos_size; 2075 unsigned sx_max_export_smx_size; 2076 unsigned sq_num_cf_insts; 2077 unsigned sx_num_of_sets; 2078 unsigned sc_prim_fifo_size; 2079 unsigned sc_hiz_tile_fifo_size; 2080 unsigned sc_earlyz_tile_fifo_size; 2081 unsigned tiling_nbanks; 2082 unsigned tiling_npipes; 2083 unsigned tiling_group_size; 2084 unsigned tile_config; 2085 unsigned backend_map; 2086 unsigned active_simds; 2087 }; 2088 2089 struct cayman_asic { 2090 unsigned max_shader_engines; 2091 unsigned max_pipes_per_simd; 2092 unsigned max_tile_pipes; 2093 unsigned max_simds_per_se; 2094 unsigned max_backends_per_se; 2095 unsigned max_texture_channel_caches; 2096 unsigned max_gprs; 2097 unsigned max_threads; 2098 unsigned max_gs_threads; 2099 unsigned max_stack_entries; 2100 unsigned sx_num_of_sets; 2101 unsigned sx_max_export_size; 2102 unsigned sx_max_export_pos_size; 2103 unsigned sx_max_export_smx_size; 2104 unsigned max_hw_contexts; 2105 unsigned sq_num_cf_insts; 2106 unsigned sc_prim_fifo_size; 2107 unsigned sc_hiz_tile_fifo_size; 2108 unsigned sc_earlyz_tile_fifo_size; 2109 2110 unsigned num_shader_engines; 2111 unsigned num_shader_pipes_per_simd; 2112 unsigned num_tile_pipes; 2113 unsigned num_simds_per_se; 2114 unsigned num_backends_per_se; 2115 unsigned backend_disable_mask_per_asic; 2116 unsigned backend_map; 2117 unsigned num_texture_channel_caches; 2118 unsigned mem_max_burst_length_bytes; 2119 unsigned mem_row_size_in_kb; 2120 unsigned shader_engine_tile_size; 2121 unsigned num_gpus; 2122 unsigned multi_gpu_tile_size; 2123 2124 unsigned tile_config; 2125 unsigned active_simds; 2126 }; 2127 2128 struct si_asic { 2129 unsigned max_shader_engines; 2130 unsigned max_tile_pipes; 2131 unsigned max_cu_per_sh; 2132 unsigned max_sh_per_se; 2133 unsigned max_backends_per_se; 2134 unsigned max_texture_channel_caches; 2135 unsigned max_gprs; 2136 unsigned max_gs_threads; 2137 unsigned max_hw_contexts; 2138 unsigned sc_prim_fifo_size_frontend; 2139 unsigned sc_prim_fifo_size_backend; 2140 unsigned sc_hiz_tile_fifo_size; 2141 unsigned sc_earlyz_tile_fifo_size; 2142 2143 unsigned num_tile_pipes; 2144 unsigned backend_enable_mask; 2145 unsigned backend_disable_mask_per_asic; 2146 unsigned backend_map; 2147 unsigned num_texture_channel_caches; 2148 unsigned mem_max_burst_length_bytes; 2149 unsigned mem_row_size_in_kb; 2150 unsigned shader_engine_tile_size; 2151 unsigned num_gpus; 2152 unsigned multi_gpu_tile_size; 2153 2154 unsigned tile_config; 2155 uint32_t tile_mode_array[32]; 2156 uint32_t active_cus; 2157 }; 2158 2159 struct cik_asic { 2160 unsigned max_shader_engines; 2161 unsigned max_tile_pipes; 2162 unsigned max_cu_per_sh; 2163 unsigned max_sh_per_se; 2164 unsigned max_backends_per_se; 2165 unsigned max_texture_channel_caches; 2166 unsigned max_gprs; 2167 unsigned max_gs_threads; 2168 unsigned max_hw_contexts; 2169 unsigned sc_prim_fifo_size_frontend; 2170 unsigned sc_prim_fifo_size_backend; 2171 unsigned sc_hiz_tile_fifo_size; 2172 unsigned sc_earlyz_tile_fifo_size; 2173 2174 unsigned num_tile_pipes; 2175 unsigned backend_enable_mask; 2176 unsigned backend_disable_mask_per_asic; 2177 unsigned backend_map; 2178 unsigned num_texture_channel_caches; 2179 unsigned mem_max_burst_length_bytes; 2180 unsigned mem_row_size_in_kb; 2181 unsigned shader_engine_tile_size; 2182 unsigned num_gpus; 2183 unsigned multi_gpu_tile_size; 2184 2185 unsigned tile_config; 2186 uint32_t tile_mode_array[32]; 2187 uint32_t macrotile_mode_array[16]; 2188 uint32_t active_cus; 2189 }; 2190 2191 union radeon_asic_config { 2192 struct r300_asic r300; 2193 struct r100_asic r100; 2194 struct r600_asic r600; 2195 struct rv770_asic rv770; 2196 struct evergreen_asic evergreen; 2197 struct cayman_asic cayman; 2198 struct si_asic si; 2199 struct cik_asic cik; 2200 }; 2201 2202 /* 2203 * asic initizalization from radeon_asic.c 2204 */ 2205 void radeon_agp_disable(struct radeon_device *rdev); 2206 int radeon_asic_init(struct radeon_device *rdev); 2207 2208 2209 /* 2210 * IOCTL. 2211 */ 2212 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2213 struct drm_file *filp); 2214 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2215 struct drm_file *filp); 2216 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2217 struct drm_file *filp); 2218 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2219 struct drm_file *file_priv); 2220 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2221 struct drm_file *file_priv); 2222 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2223 struct drm_file *file_priv); 2224 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2225 struct drm_file *file_priv); 2226 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2227 struct drm_file *filp); 2228 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2229 struct drm_file *filp); 2230 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2231 struct drm_file *filp); 2232 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2233 struct drm_file *filp); 2234 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2235 struct drm_file *filp); 2236 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2237 struct drm_file *filp); 2238 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2239 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2240 struct drm_file *filp); 2241 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2242 struct drm_file *filp); 2243 2244 /* VRAM scratch page for HDP bug, default vram page */ 2245 struct r600_vram_scratch { 2246 struct radeon_bo *robj; 2247 volatile uint32_t *ptr; 2248 u64 gpu_addr; 2249 }; 2250 2251 /* 2252 * ACPI 2253 */ 2254 struct radeon_atif_notification_cfg { 2255 bool enabled; 2256 int command_code; 2257 }; 2258 2259 struct radeon_atif_notifications { 2260 bool display_switch; 2261 bool expansion_mode_change; 2262 bool thermal_state; 2263 bool forced_power_state; 2264 bool system_power_state; 2265 bool display_conf_change; 2266 bool px_gfx_switch; 2267 bool brightness_change; 2268 bool dgpu_display_event; 2269 }; 2270 2271 struct radeon_atif_functions { 2272 bool system_params; 2273 bool sbios_requests; 2274 bool select_active_disp; 2275 bool lid_state; 2276 bool get_tv_standard; 2277 bool set_tv_standard; 2278 bool get_panel_expansion_mode; 2279 bool set_panel_expansion_mode; 2280 bool temperature_change; 2281 bool graphics_device_types; 2282 }; 2283 2284 struct radeon_atif { 2285 struct radeon_atif_notifications notifications; 2286 struct radeon_atif_functions functions; 2287 struct radeon_atif_notification_cfg notification_cfg; 2288 struct radeon_encoder *encoder_for_bl; 2289 }; 2290 2291 struct radeon_atcs_functions { 2292 bool get_ext_state; 2293 bool pcie_perf_req; 2294 bool pcie_dev_rdy; 2295 bool pcie_bus_width; 2296 }; 2297 2298 struct radeon_atcs { 2299 struct radeon_atcs_functions functions; 2300 }; 2301 2302 /* 2303 * Core structure, functions and helpers. 2304 */ 2305 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2306 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2307 2308 struct radeon_device { 2309 struct device *dev; 2310 struct drm_device *ddev; 2311 struct pci_dev *pdev; 2312 struct rw_semaphore exclusive_lock; 2313 /* ASIC */ 2314 union radeon_asic_config config; 2315 enum radeon_family family; 2316 unsigned long flags; 2317 int usec_timeout; 2318 enum radeon_pll_errata pll_errata; 2319 int num_gb_pipes; 2320 int num_z_pipes; 2321 int disp_priority; 2322 /* BIOS */ 2323 uint8_t *bios; 2324 bool is_atom_bios; 2325 uint16_t bios_header_start; 2326 struct radeon_bo *stolen_vga_memory; 2327 /* Register mmio */ 2328 resource_size_t rmmio_base; 2329 resource_size_t rmmio_size; 2330 /* protects concurrent MM_INDEX/DATA based register access */ 2331 spinlock_t mmio_idx_lock; 2332 /* protects concurrent SMC based register access */ 2333 spinlock_t smc_idx_lock; 2334 /* protects concurrent PLL register access */ 2335 spinlock_t pll_idx_lock; 2336 /* protects concurrent MC register access */ 2337 spinlock_t mc_idx_lock; 2338 /* protects concurrent PCIE register access */ 2339 spinlock_t pcie_idx_lock; 2340 /* protects concurrent PCIE_PORT register access */ 2341 spinlock_t pciep_idx_lock; 2342 /* protects concurrent PIF register access */ 2343 spinlock_t pif_idx_lock; 2344 /* protects concurrent CG register access */ 2345 spinlock_t cg_idx_lock; 2346 /* protects concurrent UVD register access */ 2347 spinlock_t uvd_idx_lock; 2348 /* protects concurrent RCU register access */ 2349 spinlock_t rcu_idx_lock; 2350 /* protects concurrent DIDT register access */ 2351 spinlock_t didt_idx_lock; 2352 /* protects concurrent ENDPOINT (audio) register access */ 2353 spinlock_t end_idx_lock; 2354 void __iomem *rmmio; 2355 radeon_rreg_t mc_rreg; 2356 radeon_wreg_t mc_wreg; 2357 radeon_rreg_t pll_rreg; 2358 radeon_wreg_t pll_wreg; 2359 uint32_t pcie_reg_mask; 2360 radeon_rreg_t pciep_rreg; 2361 radeon_wreg_t pciep_wreg; 2362 /* io port */ 2363 void __iomem *rio_mem; 2364 resource_size_t rio_mem_size; 2365 struct radeon_clock clock; 2366 struct radeon_mc mc; 2367 struct radeon_gart gart; 2368 struct radeon_mode_info mode_info; 2369 struct radeon_scratch scratch; 2370 struct radeon_doorbell doorbell; 2371 struct radeon_mman mman; 2372 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2373 wait_queue_head_t fence_queue; 2374 u64 fence_context; 2375 struct mutex ring_lock; 2376 struct radeon_ring ring[RADEON_NUM_RINGS]; 2377 bool ib_pool_ready; 2378 struct radeon_sa_manager ring_tmp_bo; 2379 struct radeon_irq irq; 2380 struct radeon_asic *asic; 2381 struct radeon_gem gem; 2382 struct radeon_pm pm; 2383 struct radeon_uvd uvd; 2384 struct radeon_vce vce; 2385 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2386 struct radeon_wb wb; 2387 struct radeon_dummy_page dummy_page; 2388 bool shutdown; 2389 bool need_swiotlb; 2390 bool accel_working; 2391 bool fastfb_working; /* IGP feature*/ 2392 bool needs_reset, in_reset; 2393 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2394 const struct firmware *me_fw; /* all family ME firmware */ 2395 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2396 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2397 const struct firmware *mc_fw; /* NI MC firmware */ 2398 const struct firmware *ce_fw; /* SI CE firmware */ 2399 const struct firmware *mec_fw; /* CIK MEC firmware */ 2400 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2401 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2402 const struct firmware *smc_fw; /* SMC firmware */ 2403 const struct firmware *uvd_fw; /* UVD firmware */ 2404 const struct firmware *vce_fw; /* VCE firmware */ 2405 bool new_fw; 2406 struct r600_vram_scratch vram_scratch; 2407 int msi_enabled; /* msi enabled */ 2408 struct r600_ih ih; /* r6/700 interrupt ring */ 2409 struct radeon_rlc rlc; 2410 struct radeon_mec mec; 2411 struct delayed_work hotplug_work; 2412 struct work_struct dp_work; 2413 struct work_struct audio_work; 2414 int num_crtc; /* number of crtcs */ 2415 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2416 bool has_uvd; 2417 bool has_vce; 2418 struct r600_audio audio; /* audio stuff */ 2419 struct notifier_block acpi_nb; 2420 /* only one userspace can use Hyperz features or CMASK at a time */ 2421 struct drm_file *hyperz_filp; 2422 struct drm_file *cmask_filp; 2423 /* i2c buses */ 2424 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2425 /* debugfs */ 2426 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2427 unsigned debugfs_count; 2428 /* virtual memory */ 2429 struct radeon_vm_manager vm_manager; 2430 struct mutex gpu_clock_mutex; 2431 /* memory stats */ 2432 atomic64_t vram_usage; 2433 atomic64_t gtt_usage; 2434 atomic64_t num_bytes_moved; 2435 atomic_t gpu_reset_counter; 2436 /* ACPI interface */ 2437 struct radeon_atif atif; 2438 struct radeon_atcs atcs; 2439 /* srbm instance registers */ 2440 struct mutex srbm_mutex; 2441 /* clock, powergating flags */ 2442 u32 cg_flags; 2443 u32 pg_flags; 2444 2445 struct dev_pm_domain vga_pm_domain; 2446 bool have_disp_power_ref; 2447 u32 px_quirk_flags; 2448 2449 /* tracking pinned memory */ 2450 u64 vram_pin_size; 2451 u64 gart_pin_size; 2452 }; 2453 2454 bool radeon_is_px(struct drm_device *dev); 2455 int radeon_device_init(struct radeon_device *rdev, 2456 struct drm_device *ddev, 2457 struct pci_dev *pdev, 2458 uint32_t flags); 2459 void radeon_device_fini(struct radeon_device *rdev); 2460 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2461 2462 #define RADEON_MIN_MMIO_SIZE 0x10000 2463 2464 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg); 2465 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2466 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2467 bool always_indirect) 2468 { 2469 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2470 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2471 return readl(((void __iomem *)rdev->rmmio) + reg); 2472 else 2473 return r100_mm_rreg_slow(rdev, reg); 2474 } 2475 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2476 bool always_indirect) 2477 { 2478 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2479 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2480 else 2481 r100_mm_wreg_slow(rdev, reg, v); 2482 } 2483 2484 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2485 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2486 2487 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2488 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2489 2490 /* 2491 * Cast helper 2492 */ 2493 extern const struct dma_fence_ops radeon_fence_ops; 2494 2495 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f) 2496 { 2497 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2498 2499 if (__f->base.ops == &radeon_fence_ops) 2500 return __f; 2501 2502 return NULL; 2503 } 2504 2505 /* 2506 * Registers read & write functions. 2507 */ 2508 #define RREG8(reg) readb((rdev->rmmio) + (reg)) 2509 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2510 #define RREG16(reg) readw((rdev->rmmio) + (reg)) 2511 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2512 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2513 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2514 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \ 2515 r100_mm_rreg(rdev, (reg), false)) 2516 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2517 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2518 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2519 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2520 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2521 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2522 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2523 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2524 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2525 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2526 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2527 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2528 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2529 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2530 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2531 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2532 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2533 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2534 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2535 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2536 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2537 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2538 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2539 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2540 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2541 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2542 #define WREG32_P(reg, val, mask) \ 2543 do { \ 2544 uint32_t tmp_ = RREG32(reg); \ 2545 tmp_ &= (mask); \ 2546 tmp_ |= ((val) & ~(mask)); \ 2547 WREG32(reg, tmp_); \ 2548 } while (0) 2549 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2550 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2551 #define WREG32_PLL_P(reg, val, mask) \ 2552 do { \ 2553 uint32_t tmp_ = RREG32_PLL(reg); \ 2554 tmp_ &= (mask); \ 2555 tmp_ |= ((val) & ~(mask)); \ 2556 WREG32_PLL(reg, tmp_); \ 2557 } while (0) 2558 #define WREG32_SMC_P(reg, val, mask) \ 2559 do { \ 2560 uint32_t tmp_ = RREG32_SMC(reg); \ 2561 tmp_ &= (mask); \ 2562 tmp_ |= ((val) & ~(mask)); \ 2563 WREG32_SMC(reg, tmp_); \ 2564 } while (0) 2565 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2566 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2567 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2568 2569 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2570 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2571 2572 /* 2573 * Indirect registers accessors. 2574 * They used to be inlined, but this increases code size by ~65 kbytes. 2575 * Since each performs a pair of MMIO ops 2576 * within a spin_lock_irqsave/spin_unlock_irqrestore region, 2577 * the cost of call+ret is almost negligible. MMIO and locking 2578 * costs several dozens of cycles each at best, call+ret is ~5 cycles. 2579 */ 2580 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); 2581 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 2582 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg); 2583 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2584 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg); 2585 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2586 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg); 2587 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2588 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg); 2589 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2590 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg); 2591 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2592 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg); 2593 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2594 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg); 2595 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2596 2597 void r100_pll_errata_after_index(struct radeon_device *rdev); 2598 2599 2600 /* 2601 * ASICs helpers. 2602 */ 2603 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2604 (rdev->pdev->device == 0x5969)) 2605 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2606 (rdev->family == CHIP_RV200) || \ 2607 (rdev->family == CHIP_RS100) || \ 2608 (rdev->family == CHIP_RS200) || \ 2609 (rdev->family == CHIP_RV250) || \ 2610 (rdev->family == CHIP_RV280) || \ 2611 (rdev->family == CHIP_RS300)) 2612 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2613 (rdev->family == CHIP_RV350) || \ 2614 (rdev->family == CHIP_R350) || \ 2615 (rdev->family == CHIP_RV380) || \ 2616 (rdev->family == CHIP_R420) || \ 2617 (rdev->family == CHIP_R423) || \ 2618 (rdev->family == CHIP_RV410) || \ 2619 (rdev->family == CHIP_RS400) || \ 2620 (rdev->family == CHIP_RS480)) 2621 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2622 (rdev->ddev->pdev->device == 0x9443) || \ 2623 (rdev->ddev->pdev->device == 0x944B) || \ 2624 (rdev->ddev->pdev->device == 0x9506) || \ 2625 (rdev->ddev->pdev->device == 0x9509) || \ 2626 (rdev->ddev->pdev->device == 0x950F) || \ 2627 (rdev->ddev->pdev->device == 0x689C) || \ 2628 (rdev->ddev->pdev->device == 0x689D)) 2629 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2630 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2631 (rdev->family == CHIP_RS690) || \ 2632 (rdev->family == CHIP_RS740) || \ 2633 (rdev->family >= CHIP_R600)) 2634 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2635 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2636 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2637 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2638 (rdev->flags & RADEON_IS_IGP)) 2639 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2640 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2641 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2642 (rdev->flags & RADEON_IS_IGP)) 2643 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2644 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2645 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2646 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2647 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2648 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2649 (rdev->family == CHIP_MULLINS)) 2650 2651 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2652 (rdev->ddev->pdev->device == 0x6850) || \ 2653 (rdev->ddev->pdev->device == 0x6858) || \ 2654 (rdev->ddev->pdev->device == 0x6859) || \ 2655 (rdev->ddev->pdev->device == 0x6840) || \ 2656 (rdev->ddev->pdev->device == 0x6841) || \ 2657 (rdev->ddev->pdev->device == 0x6842) || \ 2658 (rdev->ddev->pdev->device == 0x6843)) 2659 2660 /* 2661 * BIOS helpers. 2662 */ 2663 #define RBIOS8(i) (rdev->bios[i]) 2664 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2665 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2666 2667 int radeon_combios_init(struct radeon_device *rdev); 2668 void radeon_combios_fini(struct radeon_device *rdev); 2669 int radeon_atombios_init(struct radeon_device *rdev); 2670 void radeon_atombios_fini(struct radeon_device *rdev); 2671 2672 2673 /* 2674 * RING helpers. 2675 */ 2676 2677 /** 2678 * radeon_ring_write - write a value to the ring 2679 * 2680 * @ring: radeon_ring structure holding ring information 2681 * @v: dword (dw) value to write 2682 * 2683 * Write a value to the requested ring buffer (all asics). 2684 */ 2685 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2686 { 2687 if (ring->count_dw <= 0) 2688 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2689 2690 ring->ring[ring->wptr++] = v; 2691 ring->wptr &= ring->ptr_mask; 2692 ring->count_dw--; 2693 ring->ring_free_dw--; 2694 } 2695 2696 /* 2697 * ASICs macro. 2698 */ 2699 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 2700 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2701 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2702 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2703 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2704 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2705 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false) 2706 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2707 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2708 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2709 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2710 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2711 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2712 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2713 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2714 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2715 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2716 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2717 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2718 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2719 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2720 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2721 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2722 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2723 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2724 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2725 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2726 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2727 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2728 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2729 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2730 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2731 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2732 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2733 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2734 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2735 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2736 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2737 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2738 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2739 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2740 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2741 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2742 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2743 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2744 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2745 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2746 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2747 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2748 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2749 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2750 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2751 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2752 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2753 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2754 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2755 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2756 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2757 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2758 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2759 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2760 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2761 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2762 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2763 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async)) 2764 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2765 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2766 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2767 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2768 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2769 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2770 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2771 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2772 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2773 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2774 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2775 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2776 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2777 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2778 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2779 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2780 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2781 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2782 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2783 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2784 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2785 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2786 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2787 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2788 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2789 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2790 2791 /* Common functions */ 2792 /* AGP */ 2793 extern int radeon_gpu_reset(struct radeon_device *rdev); 2794 extern void radeon_pci_config_reset(struct radeon_device *rdev); 2795 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2796 extern void radeon_agp_disable(struct radeon_device *rdev); 2797 extern int radeon_modeset_init(struct radeon_device *rdev); 2798 extern void radeon_modeset_fini(struct radeon_device *rdev); 2799 extern bool radeon_card_posted(struct radeon_device *rdev); 2800 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2801 extern void radeon_update_display_priority(struct radeon_device *rdev); 2802 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2803 extern void radeon_scratch_init(struct radeon_device *rdev); 2804 extern void radeon_wb_fini(struct radeon_device *rdev); 2805 extern int radeon_wb_init(struct radeon_device *rdev); 2806 extern void radeon_wb_disable(struct radeon_device *rdev); 2807 extern void radeon_surface_init(struct radeon_device *rdev); 2808 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2809 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2810 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2811 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2812 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2813 extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2814 uint32_t flags); 2815 extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2816 extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2817 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2818 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2819 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2820 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, 2821 bool fbcon, bool freeze); 2822 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2823 extern void radeon_program_register_sequence(struct radeon_device *rdev, 2824 const u32 *registers, 2825 const u32 array_size); 2826 2827 /* 2828 * vm 2829 */ 2830 int radeon_vm_manager_init(struct radeon_device *rdev); 2831 void radeon_vm_manager_fini(struct radeon_device *rdev); 2832 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2833 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2834 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 2835 struct radeon_vm *vm, 2836 struct list_head *head); 2837 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2838 struct radeon_vm *vm, int ring); 2839 void radeon_vm_flush(struct radeon_device *rdev, 2840 struct radeon_vm *vm, 2841 int ring, struct radeon_fence *fence); 2842 void radeon_vm_fence(struct radeon_device *rdev, 2843 struct radeon_vm *vm, 2844 struct radeon_fence *fence); 2845 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 2846 int radeon_vm_update_page_directory(struct radeon_device *rdev, 2847 struct radeon_vm *vm); 2848 int radeon_vm_clear_freed(struct radeon_device *rdev, 2849 struct radeon_vm *vm); 2850 int radeon_vm_clear_invalids(struct radeon_device *rdev, 2851 struct radeon_vm *vm); 2852 int radeon_vm_bo_update(struct radeon_device *rdev, 2853 struct radeon_bo_va *bo_va, 2854 struct ttm_mem_reg *mem); 2855 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 2856 struct radeon_bo *bo); 2857 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 2858 struct radeon_bo *bo); 2859 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 2860 struct radeon_vm *vm, 2861 struct radeon_bo *bo); 2862 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 2863 struct radeon_bo_va *bo_va, 2864 uint64_t offset, 2865 uint32_t flags); 2866 void radeon_vm_bo_rmv(struct radeon_device *rdev, 2867 struct radeon_bo_va *bo_va); 2868 2869 /* audio */ 2870 void r600_audio_update_hdmi(struct work_struct *work); 2871 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 2872 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 2873 void r600_audio_enable(struct radeon_device *rdev, 2874 struct r600_audio_pin *pin, 2875 u8 enable_mask); 2876 void dce6_audio_enable(struct radeon_device *rdev, 2877 struct r600_audio_pin *pin, 2878 u8 enable_mask); 2879 2880 /* 2881 * R600 vram scratch functions 2882 */ 2883 int r600_vram_scratch_init(struct radeon_device *rdev); 2884 void r600_vram_scratch_fini(struct radeon_device *rdev); 2885 2886 /* 2887 * r600 cs checking helper 2888 */ 2889 unsigned r600_mip_minify(unsigned size, unsigned level); 2890 bool r600_fmt_is_valid_color(u32 format); 2891 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 2892 int r600_fmt_get_blocksize(u32 format); 2893 int r600_fmt_get_nblocksx(u32 format, u32 w); 2894 int r600_fmt_get_nblocksy(u32 format, u32 h); 2895 2896 /* 2897 * r600 functions used by radeon_encoder.c 2898 */ 2899 struct radeon_hdmi_acr { 2900 u32 clock; 2901 2902 int n_32khz; 2903 int cts_32khz; 2904 2905 int n_44_1khz; 2906 int cts_44_1khz; 2907 2908 int n_48khz; 2909 int cts_48khz; 2910 2911 }; 2912 2913 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2914 2915 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2916 u32 tiling_pipe_num, 2917 u32 max_rb_num, 2918 u32 total_max_rb_num, 2919 u32 enabled_rb_mask); 2920 2921 /* 2922 * evergreen functions used by radeon_encoder.c 2923 */ 2924 2925 extern int ni_init_microcode(struct radeon_device *rdev); 2926 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2927 2928 /* radeon_acpi.c */ 2929 #if defined(CONFIG_ACPI) 2930 extern int radeon_acpi_init(struct radeon_device *rdev); 2931 extern void radeon_acpi_fini(struct radeon_device *rdev); 2932 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 2933 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 2934 u8 perf_req, bool advertise); 2935 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 2936 #else 2937 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2938 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2939 #endif 2940 2941 int radeon_cs_packet_parse(struct radeon_cs_parser *p, 2942 struct radeon_cs_packet *pkt, 2943 unsigned idx); 2944 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 2945 void radeon_cs_dump_packet(struct radeon_cs_parser *p, 2946 struct radeon_cs_packet *pkt); 2947 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 2948 struct radeon_bo_list **cs_reloc, 2949 int nomm); 2950 int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 2951 uint32_t *vline_start_end, 2952 uint32_t *vline_status); 2953 2954 /* interrupt control register helpers */ 2955 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, 2956 u32 reg, u32 mask, 2957 bool enable, const char *name, 2958 unsigned n); 2959 2960 #include "radeon_object.h" 2961 2962 #endif 2963