1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/pci.h> 28 29 #include <drm/drm_device.h> 30 #include <drm/drm_edid.h> 31 #include <drm/radeon_drm.h> 32 33 #include "radeon.h" 34 35 #include "atom.h" 36 #include "atom-bits.h" 37 #include "radeon_asic.h" 38 #include "radeon_atombios.h" 39 #include "radeon_legacy_encoders.h" 40 41 union atom_supported_devices { 42 struct _ATOM_SUPPORTED_DEVICES_INFO info; 43 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 44 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 45 }; 46 47 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 48 ATOM_GPIO_I2C_ASSIGMENT *gpio, 49 u8 index) 50 { 51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 52 if ((rdev->family == CHIP_R420) || 53 (rdev->family == CHIP_R423) || 54 (rdev->family == CHIP_RV410)) { 55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 58 gpio->ucClkMaskShift = 0x19; 59 gpio->ucDataMaskShift = 0x18; 60 } 61 } 62 63 /* some evergreen boards have bad data for this entry */ 64 if (ASIC_IS_DCE4(rdev)) { 65 if ((index == 7) && 66 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 67 (gpio->sucI2cId.ucAccess == 0)) { 68 gpio->sucI2cId.ucAccess = 0x97; 69 gpio->ucDataMaskShift = 8; 70 gpio->ucDataEnShift = 8; 71 gpio->ucDataY_Shift = 8; 72 gpio->ucDataA_Shift = 8; 73 } 74 } 75 76 /* some DCE3 boards have bad data for this entry */ 77 if (ASIC_IS_DCE3(rdev)) { 78 if ((index == 4) && 79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 80 (gpio->sucI2cId.ucAccess == 0x94)) 81 gpio->sucI2cId.ucAccess = 0x14; 82 } 83 } 84 85 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 86 { 87 struct radeon_i2c_bus_rec i2c; 88 89 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 90 91 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 92 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 93 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 94 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 95 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 96 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 97 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 98 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 99 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 100 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 101 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 102 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 103 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 104 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 105 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 106 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 107 108 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 109 i2c.hw_capable = true; 110 else 111 i2c.hw_capable = false; 112 113 if (gpio->sucI2cId.ucAccess == 0xa0) 114 i2c.mm_i2c = true; 115 else 116 i2c.mm_i2c = false; 117 118 i2c.i2c_id = gpio->sucI2cId.ucAccess; 119 120 if (i2c.mask_clk_reg) 121 i2c.valid = true; 122 else 123 i2c.valid = false; 124 125 return i2c; 126 } 127 128 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 129 uint8_t id) 130 { 131 struct atom_context *ctx = rdev->mode_info.atom_context; 132 ATOM_GPIO_I2C_ASSIGMENT *gpio; 133 struct radeon_i2c_bus_rec i2c; 134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 135 struct _ATOM_GPIO_I2C_INFO *i2c_info; 136 uint16_t data_offset, size; 137 int i, num_indices; 138 139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 140 i2c.valid = false; 141 142 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 144 145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 146 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 147 148 gpio = &i2c_info->asGPIO_Info[0]; 149 for (i = 0; i < num_indices; i++) { 150 151 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 152 153 if (gpio->sucI2cId.ucAccess == id) { 154 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 155 break; 156 } 157 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 158 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 159 } 160 } 161 162 return i2c; 163 } 164 165 void radeon_atombios_i2c_init(struct radeon_device *rdev) 166 { 167 struct atom_context *ctx = rdev->mode_info.atom_context; 168 ATOM_GPIO_I2C_ASSIGMENT *gpio; 169 struct radeon_i2c_bus_rec i2c; 170 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 171 struct _ATOM_GPIO_I2C_INFO *i2c_info; 172 uint16_t data_offset, size; 173 int i, num_indices; 174 char stmp[32]; 175 176 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 177 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 178 179 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 180 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 181 182 gpio = &i2c_info->asGPIO_Info[0]; 183 for (i = 0; i < num_indices; i++) { 184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 185 186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 187 188 if (i2c.valid) { 189 sprintf(stmp, "0x%x", i2c.i2c_id); 190 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 191 } 192 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 193 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 194 } 195 } 196 } 197 198 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 199 u8 id) 200 { 201 struct atom_context *ctx = rdev->mode_info.atom_context; 202 struct radeon_gpio_rec gpio; 203 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 204 struct _ATOM_GPIO_PIN_LUT *gpio_info; 205 ATOM_GPIO_PIN_ASSIGNMENT *pin; 206 u16 data_offset, size; 207 int i, num_indices; 208 209 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 210 gpio.valid = false; 211 212 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 213 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 214 215 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 216 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 217 218 pin = gpio_info->asGPIO_Pin; 219 for (i = 0; i < num_indices; i++) { 220 if (id == pin->ucGPIO_ID) { 221 gpio.id = pin->ucGPIO_ID; 222 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 223 gpio.shift = pin->ucGpioPinBitShift; 224 gpio.mask = (1 << pin->ucGpioPinBitShift); 225 gpio.valid = true; 226 break; 227 } 228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 230 } 231 } 232 233 return gpio; 234 } 235 236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 237 struct radeon_gpio_rec *gpio) 238 { 239 struct radeon_hpd hpd; 240 u32 reg; 241 242 memset(&hpd, 0, sizeof(struct radeon_hpd)); 243 244 if (ASIC_IS_DCE6(rdev)) 245 reg = SI_DC_GPIO_HPD_A; 246 else if (ASIC_IS_DCE4(rdev)) 247 reg = EVERGREEN_DC_GPIO_HPD_A; 248 else 249 reg = AVIVO_DC_GPIO_HPD_A; 250 251 hpd.gpio = *gpio; 252 if (gpio->reg == reg) { 253 switch(gpio->mask) { 254 case (1 << 0): 255 hpd.hpd = RADEON_HPD_1; 256 break; 257 case (1 << 8): 258 hpd.hpd = RADEON_HPD_2; 259 break; 260 case (1 << 16): 261 hpd.hpd = RADEON_HPD_3; 262 break; 263 case (1 << 24): 264 hpd.hpd = RADEON_HPD_4; 265 break; 266 case (1 << 26): 267 hpd.hpd = RADEON_HPD_5; 268 break; 269 case (1 << 28): 270 hpd.hpd = RADEON_HPD_6; 271 break; 272 default: 273 hpd.hpd = RADEON_HPD_NONE; 274 break; 275 } 276 } else 277 hpd.hpd = RADEON_HPD_NONE; 278 return hpd; 279 } 280 281 static bool radeon_atom_apply_quirks(struct drm_device *dev, 282 uint32_t supported_device, 283 int *connector_type, 284 struct radeon_i2c_bus_rec *i2c_bus, 285 uint16_t *line_mux, 286 struct radeon_hpd *hpd) 287 { 288 struct pci_dev *pdev = to_pci_dev(dev->dev); 289 290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 291 if ((pdev->device == 0x791e) && 292 (pdev->subsystem_vendor == 0x1043) && 293 (pdev->subsystem_device == 0x826d)) { 294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 296 *connector_type = DRM_MODE_CONNECTOR_DVID; 297 } 298 299 /* Asrock RS600 board lists the DVI port as HDMI */ 300 if ((pdev->device == 0x7941) && 301 (pdev->subsystem_vendor == 0x1849) && 302 (pdev->subsystem_device == 0x7941)) { 303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 305 *connector_type = DRM_MODE_CONNECTOR_DVID; 306 } 307 308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 309 if ((pdev->device == 0x796e) && 310 (pdev->subsystem_vendor == 0x1462) && 311 (pdev->subsystem_device == 0x7302)) { 312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 314 return false; 315 } 316 317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 318 if ((pdev->device == 0x7941) && 319 (pdev->subsystem_vendor == 0x147b) && 320 (pdev->subsystem_device == 0x2412)) { 321 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 322 return false; 323 } 324 325 /* Falcon NW laptop lists vga ddc line for LVDS */ 326 if ((pdev->device == 0x5653) && 327 (pdev->subsystem_vendor == 0x1462) && 328 (pdev->subsystem_device == 0x0291)) { 329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 330 i2c_bus->valid = false; 331 *line_mux = 53; 332 } 333 } 334 335 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 336 if ((pdev->device == 0x7146) && 337 (pdev->subsystem_vendor == 0x17af) && 338 (pdev->subsystem_device == 0x2058)) { 339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 340 return false; 341 } 342 343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 344 if ((pdev->device == 0x7142) && 345 (pdev->subsystem_vendor == 0x1458) && 346 (pdev->subsystem_device == 0x2134)) { 347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 348 return false; 349 } 350 351 352 /* Funky macbooks */ 353 if ((pdev->device == 0x71C5) && 354 (pdev->subsystem_vendor == 0x106b) && 355 (pdev->subsystem_device == 0x0080)) { 356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 358 return false; 359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 360 *line_mux = 0x90; 361 } 362 363 /* mac rv630, rv730, others */ 364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 368 } 369 370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 371 if ((pdev->device == 0x9598) && 372 (pdev->subsystem_vendor == 0x1043) && 373 (pdev->subsystem_device == 0x01da)) { 374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 375 *connector_type = DRM_MODE_CONNECTOR_DVII; 376 } 377 } 378 379 /* ASUS HD 3600 board lists the DVI port as HDMI */ 380 if ((pdev->device == 0x9598) && 381 (pdev->subsystem_vendor == 0x1043) && 382 (pdev->subsystem_device == 0x01e4)) { 383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 384 *connector_type = DRM_MODE_CONNECTOR_DVII; 385 } 386 } 387 388 /* ASUS HD 3450 board lists the DVI port as HDMI */ 389 if ((pdev->device == 0x95C5) && 390 (pdev->subsystem_vendor == 0x1043) && 391 (pdev->subsystem_device == 0x01e2)) { 392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 393 *connector_type = DRM_MODE_CONNECTOR_DVII; 394 } 395 } 396 397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 398 * HDMI + VGA reporting as HDMI 399 */ 400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 402 *connector_type = DRM_MODE_CONNECTOR_VGA; 403 *line_mux = 0; 404 } 405 } 406 407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 408 * on the laptop and a DVI port on the docking station and 409 * both share the same encoder, hpd pin, and ddc line. 410 * So while the bios table is technically correct, 411 * we drop the DVI port here since xrandr has no concept of 412 * encoders and will try and drive both connectors 413 * with different crtcs which isn't possible on the hardware 414 * side and leaves no crtcs for LVDS or VGA. 415 */ 416 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) && 417 (pdev->subsystem_vendor == 0x1025) && 418 (pdev->subsystem_device == 0x013c)) { 419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 421 /* actually it's a DVI-D port not DVI-I */ 422 *connector_type = DRM_MODE_CONNECTOR_DVID; 423 return false; 424 } 425 } 426 427 /* XFX Pine Group device rv730 reports no VGA DDC lines 428 * even though they are wired up to record 0x93 429 */ 430 if ((pdev->device == 0x9498) && 431 (pdev->subsystem_vendor == 0x1682) && 432 (pdev->subsystem_device == 0x2452) && 433 (i2c_bus->valid == false) && 434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 435 struct radeon_device *rdev = dev->dev_private; 436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 437 } 438 439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 440 if (((pdev->device == 0x9802) || 441 (pdev->device == 0x9805) || 442 (pdev->device == 0x9806)) && 443 (pdev->subsystem_vendor == 0x1734) && 444 (pdev->subsystem_device == 0x11bd)) { 445 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 446 *connector_type = DRM_MODE_CONNECTOR_DVII; 447 *line_mux = 0x3103; 448 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 449 *connector_type = DRM_MODE_CONNECTOR_DVII; 450 } 451 } 452 453 return true; 454 } 455 456 static const int supported_devices_connector_convert[] = { 457 DRM_MODE_CONNECTOR_Unknown, 458 DRM_MODE_CONNECTOR_VGA, 459 DRM_MODE_CONNECTOR_DVII, 460 DRM_MODE_CONNECTOR_DVID, 461 DRM_MODE_CONNECTOR_DVIA, 462 DRM_MODE_CONNECTOR_SVIDEO, 463 DRM_MODE_CONNECTOR_Composite, 464 DRM_MODE_CONNECTOR_LVDS, 465 DRM_MODE_CONNECTOR_Unknown, 466 DRM_MODE_CONNECTOR_Unknown, 467 DRM_MODE_CONNECTOR_HDMIA, 468 DRM_MODE_CONNECTOR_HDMIB, 469 DRM_MODE_CONNECTOR_Unknown, 470 DRM_MODE_CONNECTOR_Unknown, 471 DRM_MODE_CONNECTOR_9PinDIN, 472 DRM_MODE_CONNECTOR_DisplayPort 473 }; 474 475 static const uint16_t supported_devices_connector_object_id_convert[] = { 476 CONNECTOR_OBJECT_ID_NONE, 477 CONNECTOR_OBJECT_ID_VGA, 478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 480 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 481 CONNECTOR_OBJECT_ID_COMPOSITE, 482 CONNECTOR_OBJECT_ID_SVIDEO, 483 CONNECTOR_OBJECT_ID_LVDS, 484 CONNECTOR_OBJECT_ID_9PIN_DIN, 485 CONNECTOR_OBJECT_ID_9PIN_DIN, 486 CONNECTOR_OBJECT_ID_DISPLAYPORT, 487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 489 CONNECTOR_OBJECT_ID_SVIDEO 490 }; 491 492 static const int object_connector_convert[] = { 493 DRM_MODE_CONNECTOR_Unknown, 494 DRM_MODE_CONNECTOR_DVII, 495 DRM_MODE_CONNECTOR_DVII, 496 DRM_MODE_CONNECTOR_DVID, 497 DRM_MODE_CONNECTOR_DVID, 498 DRM_MODE_CONNECTOR_VGA, 499 DRM_MODE_CONNECTOR_Composite, 500 DRM_MODE_CONNECTOR_SVIDEO, 501 DRM_MODE_CONNECTOR_Unknown, 502 DRM_MODE_CONNECTOR_Unknown, 503 DRM_MODE_CONNECTOR_9PinDIN, 504 DRM_MODE_CONNECTOR_Unknown, 505 DRM_MODE_CONNECTOR_HDMIA, 506 DRM_MODE_CONNECTOR_HDMIB, 507 DRM_MODE_CONNECTOR_LVDS, 508 DRM_MODE_CONNECTOR_9PinDIN, 509 DRM_MODE_CONNECTOR_Unknown, 510 DRM_MODE_CONNECTOR_Unknown, 511 DRM_MODE_CONNECTOR_Unknown, 512 DRM_MODE_CONNECTOR_DisplayPort, 513 DRM_MODE_CONNECTOR_eDP, 514 DRM_MODE_CONNECTOR_Unknown 515 }; 516 517 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 518 { 519 struct radeon_device *rdev = dev->dev_private; 520 struct radeon_mode_info *mode_info = &rdev->mode_info; 521 struct atom_context *ctx = mode_info->atom_context; 522 int index = GetIndexIntoMasterTable(DATA, Object_Header); 523 u16 size, data_offset; 524 u8 frev, crev; 525 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 526 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 527 ATOM_OBJECT_TABLE *router_obj; 528 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 529 ATOM_OBJECT_HEADER *obj_header; 530 int i, j, k, path_size, device_support; 531 int connector_type; 532 u16 igp_lane_info, conn_id, connector_object_id; 533 struct radeon_i2c_bus_rec ddc_bus; 534 struct radeon_router router; 535 struct radeon_gpio_rec gpio; 536 struct radeon_hpd hpd; 537 538 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 539 return false; 540 541 if (crev < 2) 542 return false; 543 544 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 545 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 546 (ctx->bios + data_offset + 547 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 548 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 549 (ctx->bios + data_offset + 550 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 551 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 552 (ctx->bios + data_offset + 553 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 554 router_obj = (ATOM_OBJECT_TABLE *) 555 (ctx->bios + data_offset + 556 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 557 device_support = le16_to_cpu(obj_header->usDeviceSupport); 558 559 path_size = 0; 560 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 561 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 562 ATOM_DISPLAY_OBJECT_PATH *path; 563 addr += path_size; 564 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 565 path_size += le16_to_cpu(path->usSize); 566 567 if (device_support & le16_to_cpu(path->usDeviceTag)) { 568 uint8_t con_obj_id, con_obj_num; 569 570 con_obj_id = 571 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 572 >> OBJECT_ID_SHIFT; 573 con_obj_num = 574 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 575 >> ENUM_ID_SHIFT; 576 577 /* TODO CV support */ 578 if (le16_to_cpu(path->usDeviceTag) == 579 ATOM_DEVICE_CV_SUPPORT) 580 continue; 581 582 /* IGP chips */ 583 if ((rdev->flags & RADEON_IS_IGP) && 584 (con_obj_id == 585 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 586 uint16_t igp_offset = 0; 587 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 588 589 index = 590 GetIndexIntoMasterTable(DATA, 591 IntegratedSystemInfo); 592 593 if (atom_parse_data_header(ctx, index, &size, &frev, 594 &crev, &igp_offset)) { 595 596 if (crev >= 2) { 597 igp_obj = 598 (ATOM_INTEGRATED_SYSTEM_INFO_V2 599 *) (ctx->bios + igp_offset); 600 601 if (igp_obj) { 602 uint32_t slot_config, ct; 603 604 if (con_obj_num == 1) 605 slot_config = 606 igp_obj-> 607 ulDDISlot1Config; 608 else 609 slot_config = 610 igp_obj-> 611 ulDDISlot2Config; 612 613 ct = (slot_config >> 16) & 0xff; 614 connector_type = 615 object_connector_convert 616 [ct]; 617 connector_object_id = ct; 618 igp_lane_info = 619 slot_config & 0xffff; 620 } else 621 continue; 622 } else 623 continue; 624 } else { 625 igp_lane_info = 0; 626 connector_type = 627 object_connector_convert[con_obj_id]; 628 connector_object_id = con_obj_id; 629 } 630 } else { 631 igp_lane_info = 0; 632 connector_type = 633 object_connector_convert[con_obj_id]; 634 connector_object_id = con_obj_id; 635 } 636 637 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 638 continue; 639 640 router.ddc_valid = false; 641 router.cd_valid = false; 642 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 643 uint8_t grph_obj_type = 644 (le16_to_cpu(path->usGraphicObjIds[j]) & 645 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 646 647 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 648 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 649 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 650 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 651 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 652 (ctx->bios + data_offset + 653 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 654 ATOM_ENCODER_CAP_RECORD *cap_record; 655 u16 caps = 0; 656 657 while (record->ucRecordSize > 0 && 658 record->ucRecordType > 0 && 659 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 660 switch (record->ucRecordType) { 661 case ATOM_ENCODER_CAP_RECORD_TYPE: 662 cap_record =(ATOM_ENCODER_CAP_RECORD *) 663 record; 664 caps = le16_to_cpu(cap_record->usEncoderCap); 665 break; 666 } 667 record = (ATOM_COMMON_RECORD_HEADER *) 668 ((char *)record + record->ucRecordSize); 669 } 670 radeon_add_atom_encoder(dev, 671 encoder_obj, 672 le16_to_cpu 673 (path-> 674 usDeviceTag), 675 caps); 676 } 677 } 678 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 679 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 680 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 681 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 682 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 683 (ctx->bios + data_offset + 684 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 685 ATOM_I2C_RECORD *i2c_record; 686 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 687 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 688 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 689 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 690 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 691 (ctx->bios + data_offset + 692 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 693 u8 *num_dst_objs = (u8 *) 694 ((u8 *)router_src_dst_table + 1 + 695 (router_src_dst_table->ucNumberOfSrc * 2)); 696 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 697 int enum_id; 698 699 router.router_id = router_obj_id; 700 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 701 if (le16_to_cpu(path->usConnObjectId) == 702 le16_to_cpu(dst_objs[enum_id])) 703 break; 704 } 705 706 while (record->ucRecordSize > 0 && 707 record->ucRecordType > 0 && 708 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 709 switch (record->ucRecordType) { 710 case ATOM_I2C_RECORD_TYPE: 711 i2c_record = 712 (ATOM_I2C_RECORD *) 713 record; 714 i2c_config = 715 (ATOM_I2C_ID_CONFIG_ACCESS *) 716 &i2c_record->sucI2cId; 717 router.i2c_info = 718 radeon_lookup_i2c_gpio(rdev, 719 i2c_config-> 720 ucAccess); 721 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 722 break; 723 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 724 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 725 record; 726 router.ddc_valid = true; 727 router.ddc_mux_type = ddc_path->ucMuxType; 728 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 729 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 730 break; 731 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 732 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 733 record; 734 router.cd_valid = true; 735 router.cd_mux_type = cd_path->ucMuxType; 736 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 737 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 738 break; 739 } 740 record = (ATOM_COMMON_RECORD_HEADER *) 741 ((char *)record + record->ucRecordSize); 742 } 743 } 744 } 745 } 746 } 747 748 /* look up gpio for ddc, hpd */ 749 ddc_bus.valid = false; 750 hpd.hpd = RADEON_HPD_NONE; 751 if ((le16_to_cpu(path->usDeviceTag) & 752 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 753 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 754 if (le16_to_cpu(path->usConnObjectId) == 755 le16_to_cpu(con_obj->asObjects[j]. 756 usObjectID)) { 757 ATOM_COMMON_RECORD_HEADER 758 *record = 759 (ATOM_COMMON_RECORD_HEADER 760 *) 761 (ctx->bios + data_offset + 762 le16_to_cpu(con_obj-> 763 asObjects[j]. 764 usRecordOffset)); 765 ATOM_I2C_RECORD *i2c_record; 766 ATOM_HPD_INT_RECORD *hpd_record; 767 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 768 769 while (record->ucRecordSize > 0 && 770 record->ucRecordType > 0 && 771 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 772 switch (record->ucRecordType) { 773 case ATOM_I2C_RECORD_TYPE: 774 i2c_record = 775 (ATOM_I2C_RECORD *) 776 record; 777 i2c_config = 778 (ATOM_I2C_ID_CONFIG_ACCESS *) 779 &i2c_record->sucI2cId; 780 ddc_bus = radeon_lookup_i2c_gpio(rdev, 781 i2c_config-> 782 ucAccess); 783 break; 784 case ATOM_HPD_INT_RECORD_TYPE: 785 hpd_record = 786 (ATOM_HPD_INT_RECORD *) 787 record; 788 gpio = radeon_atombios_lookup_gpio(rdev, 789 hpd_record->ucHPDIntGPIOID); 790 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 791 hpd.plugged_state = hpd_record->ucPlugged_PinState; 792 break; 793 } 794 record = 795 (ATOM_COMMON_RECORD_HEADER 796 *) ((char *)record 797 + 798 record-> 799 ucRecordSize); 800 } 801 break; 802 } 803 } 804 } 805 806 /* needed for aux chan transactions */ 807 ddc_bus.hpd = hpd.hpd; 808 809 conn_id = le16_to_cpu(path->usConnObjectId); 810 811 if (!radeon_atom_apply_quirks 812 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 813 &ddc_bus, &conn_id, &hpd)) 814 continue; 815 816 radeon_add_atom_connector(dev, 817 conn_id, 818 le16_to_cpu(path-> 819 usDeviceTag), 820 connector_type, &ddc_bus, 821 igp_lane_info, 822 connector_object_id, 823 &hpd, 824 &router); 825 826 } 827 } 828 829 radeon_link_encoder_connector(dev); 830 return true; 831 } 832 833 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 834 int connector_type, 835 uint16_t devices) 836 { 837 struct radeon_device *rdev = dev->dev_private; 838 839 if (rdev->flags & RADEON_IS_IGP) { 840 return supported_devices_connector_object_id_convert 841 [connector_type]; 842 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 843 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 844 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 845 struct radeon_mode_info *mode_info = &rdev->mode_info; 846 struct atom_context *ctx = mode_info->atom_context; 847 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 848 uint16_t size, data_offset; 849 uint8_t frev, crev; 850 ATOM_XTMDS_INFO *xtmds; 851 852 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 853 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 854 855 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 856 if (connector_type == DRM_MODE_CONNECTOR_DVII) 857 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 858 else 859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 860 } else { 861 if (connector_type == DRM_MODE_CONNECTOR_DVII) 862 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 863 else 864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 865 } 866 } else 867 return supported_devices_connector_object_id_convert 868 [connector_type]; 869 } else { 870 return supported_devices_connector_object_id_convert 871 [connector_type]; 872 } 873 } 874 875 struct bios_connector { 876 bool valid; 877 uint16_t line_mux; 878 uint16_t devices; 879 int connector_type; 880 struct radeon_i2c_bus_rec ddc_bus; 881 struct radeon_hpd hpd; 882 }; 883 884 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 885 drm_device 886 *dev) 887 { 888 struct radeon_device *rdev = dev->dev_private; 889 struct radeon_mode_info *mode_info = &rdev->mode_info; 890 struct atom_context *ctx = mode_info->atom_context; 891 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 892 uint16_t size, data_offset; 893 uint8_t frev, crev; 894 uint16_t device_support; 895 uint8_t dac; 896 union atom_supported_devices *supported_devices; 897 int i, j, max_device; 898 struct bios_connector *bios_connectors; 899 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 900 struct radeon_router router; 901 902 router.ddc_valid = false; 903 router.cd_valid = false; 904 905 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 906 if (!bios_connectors) 907 return false; 908 909 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 910 &data_offset)) { 911 kfree(bios_connectors); 912 return false; 913 } 914 915 supported_devices = 916 (union atom_supported_devices *)(ctx->bios + data_offset); 917 918 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 919 920 if (frev > 1) 921 max_device = ATOM_MAX_SUPPORTED_DEVICE; 922 else 923 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 924 925 for (i = 0; i < max_device; i++) { 926 ATOM_CONNECTOR_INFO_I2C ci = 927 supported_devices->info.asConnInfo[i]; 928 929 bios_connectors[i].valid = false; 930 931 if (!(device_support & (1 << i))) { 932 continue; 933 } 934 935 if (i == ATOM_DEVICE_CV_INDEX) { 936 DRM_DEBUG_KMS("Skipping Component Video\n"); 937 continue; 938 } 939 940 bios_connectors[i].connector_type = 941 supported_devices_connector_convert[ci.sucConnectorInfo. 942 sbfAccess. 943 bfConnectorType]; 944 945 if (bios_connectors[i].connector_type == 946 DRM_MODE_CONNECTOR_Unknown) 947 continue; 948 949 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 950 951 bios_connectors[i].line_mux = 952 ci.sucI2cId.ucAccess; 953 954 /* give tv unique connector ids */ 955 if (i == ATOM_DEVICE_TV1_INDEX) { 956 bios_connectors[i].ddc_bus.valid = false; 957 bios_connectors[i].line_mux = 50; 958 } else if (i == ATOM_DEVICE_TV2_INDEX) { 959 bios_connectors[i].ddc_bus.valid = false; 960 bios_connectors[i].line_mux = 51; 961 } else if (i == ATOM_DEVICE_CV_INDEX) { 962 bios_connectors[i].ddc_bus.valid = false; 963 bios_connectors[i].line_mux = 52; 964 } else 965 bios_connectors[i].ddc_bus = 966 radeon_lookup_i2c_gpio(rdev, 967 bios_connectors[i].line_mux); 968 969 if ((crev > 1) && (frev > 1)) { 970 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 971 switch (isb) { 972 case 0x4: 973 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 974 break; 975 case 0xa: 976 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 977 break; 978 default: 979 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 980 break; 981 } 982 } else { 983 if (i == ATOM_DEVICE_DFP1_INDEX) 984 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 985 else if (i == ATOM_DEVICE_DFP2_INDEX) 986 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 987 else 988 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 989 } 990 991 /* Always set the connector type to VGA for CRT1/CRT2. if they are 992 * shared with a DVI port, we'll pick up the DVI connector when we 993 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 994 */ 995 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 996 bios_connectors[i].connector_type = 997 DRM_MODE_CONNECTOR_VGA; 998 999 if (!radeon_atom_apply_quirks 1000 (dev, (1 << i), &bios_connectors[i].connector_type, 1001 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1002 &bios_connectors[i].hpd)) 1003 continue; 1004 1005 bios_connectors[i].valid = true; 1006 bios_connectors[i].devices = (1 << i); 1007 1008 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1009 radeon_add_atom_encoder(dev, 1010 radeon_get_encoder_enum(dev, 1011 (1 << i), 1012 dac), 1013 (1 << i), 1014 0); 1015 else 1016 radeon_add_legacy_encoder(dev, 1017 radeon_get_encoder_enum(dev, 1018 (1 << i), 1019 dac), 1020 (1 << i)); 1021 } 1022 1023 /* combine shared connectors */ 1024 for (i = 0; i < max_device; i++) { 1025 if (bios_connectors[i].valid) { 1026 for (j = 0; j < max_device; j++) { 1027 if (bios_connectors[j].valid && (i != j)) { 1028 if (bios_connectors[i].line_mux == 1029 bios_connectors[j].line_mux) { 1030 /* make sure not to combine LVDS */ 1031 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1032 bios_connectors[i].line_mux = 53; 1033 bios_connectors[i].ddc_bus.valid = false; 1034 continue; 1035 } 1036 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1037 bios_connectors[j].line_mux = 53; 1038 bios_connectors[j].ddc_bus.valid = false; 1039 continue; 1040 } 1041 /* combine analog and digital for DVI-I */ 1042 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1043 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1044 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1045 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1046 bios_connectors[i].devices |= 1047 bios_connectors[j].devices; 1048 bios_connectors[i].connector_type = 1049 DRM_MODE_CONNECTOR_DVII; 1050 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1051 bios_connectors[i].hpd = 1052 bios_connectors[j].hpd; 1053 bios_connectors[j].valid = false; 1054 } 1055 } 1056 } 1057 } 1058 } 1059 } 1060 1061 /* add the connectors */ 1062 for (i = 0; i < max_device; i++) { 1063 if (bios_connectors[i].valid) { 1064 uint16_t connector_object_id = 1065 atombios_get_connector_object_id(dev, 1066 bios_connectors[i].connector_type, 1067 bios_connectors[i].devices); 1068 radeon_add_atom_connector(dev, 1069 bios_connectors[i].line_mux, 1070 bios_connectors[i].devices, 1071 bios_connectors[i]. 1072 connector_type, 1073 &bios_connectors[i].ddc_bus, 1074 0, 1075 connector_object_id, 1076 &bios_connectors[i].hpd, 1077 &router); 1078 } 1079 } 1080 1081 radeon_link_encoder_connector(dev); 1082 1083 kfree(bios_connectors); 1084 return true; 1085 } 1086 1087 union firmware_info { 1088 ATOM_FIRMWARE_INFO info; 1089 ATOM_FIRMWARE_INFO_V1_2 info_12; 1090 ATOM_FIRMWARE_INFO_V1_3 info_13; 1091 ATOM_FIRMWARE_INFO_V1_4 info_14; 1092 ATOM_FIRMWARE_INFO_V2_1 info_21; 1093 ATOM_FIRMWARE_INFO_V2_2 info_22; 1094 }; 1095 1096 union igp_info { 1097 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1098 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1099 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1100 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1101 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1102 }; 1103 1104 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) 1105 { 1106 struct radeon_mode_info *mode_info = &rdev->mode_info; 1107 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1108 union igp_info *igp_info; 1109 u8 frev, crev; 1110 u16 data_offset; 1111 1112 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1113 &frev, &crev, &data_offset)) { 1114 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1115 data_offset); 1116 rdev->clock.vco_freq = 1117 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); 1118 } 1119 } 1120 1121 bool radeon_atom_get_clock_info(struct drm_device *dev) 1122 { 1123 struct radeon_device *rdev = dev->dev_private; 1124 struct radeon_mode_info *mode_info = &rdev->mode_info; 1125 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1126 union firmware_info *firmware_info; 1127 uint8_t frev, crev; 1128 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1129 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1130 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1131 struct radeon_pll *spll = &rdev->clock.spll; 1132 struct radeon_pll *mpll = &rdev->clock.mpll; 1133 uint16_t data_offset; 1134 1135 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1136 &frev, &crev, &data_offset)) { 1137 firmware_info = 1138 (union firmware_info *)(mode_info->atom_context->bios + 1139 data_offset); 1140 /* pixel clocks */ 1141 p1pll->reference_freq = 1142 le16_to_cpu(firmware_info->info.usReferenceClock); 1143 p1pll->reference_div = 0; 1144 1145 if ((frev < 2) && (crev < 2)) 1146 p1pll->pll_out_min = 1147 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1148 else 1149 p1pll->pll_out_min = 1150 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1151 p1pll->pll_out_max = 1152 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1153 1154 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { 1155 p1pll->lcd_pll_out_min = 1156 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1157 if (p1pll->lcd_pll_out_min == 0) 1158 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1159 p1pll->lcd_pll_out_max = 1160 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1161 if (p1pll->lcd_pll_out_max == 0) 1162 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1163 } else { 1164 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1165 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1166 } 1167 1168 if (p1pll->pll_out_min == 0) { 1169 if (ASIC_IS_AVIVO(rdev)) 1170 p1pll->pll_out_min = 64800; 1171 else 1172 p1pll->pll_out_min = 20000; 1173 } 1174 1175 p1pll->pll_in_min = 1176 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1177 p1pll->pll_in_max = 1178 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1179 1180 *p2pll = *p1pll; 1181 1182 /* system clock */ 1183 if (ASIC_IS_DCE4(rdev)) 1184 spll->reference_freq = 1185 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1186 else 1187 spll->reference_freq = 1188 le16_to_cpu(firmware_info->info.usReferenceClock); 1189 spll->reference_div = 0; 1190 1191 spll->pll_out_min = 1192 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1193 spll->pll_out_max = 1194 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1195 1196 /* ??? */ 1197 if (spll->pll_out_min == 0) { 1198 if (ASIC_IS_AVIVO(rdev)) 1199 spll->pll_out_min = 64800; 1200 else 1201 spll->pll_out_min = 20000; 1202 } 1203 1204 spll->pll_in_min = 1205 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1206 spll->pll_in_max = 1207 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1208 1209 /* memory clock */ 1210 if (ASIC_IS_DCE4(rdev)) 1211 mpll->reference_freq = 1212 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1213 else 1214 mpll->reference_freq = 1215 le16_to_cpu(firmware_info->info.usReferenceClock); 1216 mpll->reference_div = 0; 1217 1218 mpll->pll_out_min = 1219 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1220 mpll->pll_out_max = 1221 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1222 1223 /* ??? */ 1224 if (mpll->pll_out_min == 0) { 1225 if (ASIC_IS_AVIVO(rdev)) 1226 mpll->pll_out_min = 64800; 1227 else 1228 mpll->pll_out_min = 20000; 1229 } 1230 1231 mpll->pll_in_min = 1232 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1233 mpll->pll_in_max = 1234 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1235 1236 rdev->clock.default_sclk = 1237 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1238 rdev->clock.default_mclk = 1239 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1240 1241 if (ASIC_IS_DCE4(rdev)) { 1242 rdev->clock.default_dispclk = 1243 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1244 if (rdev->clock.default_dispclk == 0) { 1245 if (ASIC_IS_DCE6(rdev)) 1246 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1247 else if (ASIC_IS_DCE5(rdev)) 1248 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1249 else 1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1251 } 1252 /* set a reasonable default for DP */ 1253 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1254 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1255 rdev->clock.default_dispclk / 100); 1256 rdev->clock.default_dispclk = 60000; 1257 } 1258 rdev->clock.dp_extclk = 1259 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1260 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1261 } 1262 *dcpll = *p1pll; 1263 1264 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1265 if (rdev->clock.max_pixel_clock == 0) 1266 rdev->clock.max_pixel_clock = 40000; 1267 1268 /* not technically a clock, but... */ 1269 rdev->mode_info.firmware_flags = 1270 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1271 1272 if (ASIC_IS_DCE8(rdev)) 1273 rdev->clock.vco_freq = 1274 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); 1275 else if (ASIC_IS_DCE5(rdev)) 1276 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1277 else if (ASIC_IS_DCE41(rdev)) 1278 radeon_atombios_get_dentist_vco_freq(rdev); 1279 else 1280 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1281 1282 if (rdev->clock.vco_freq == 0) 1283 rdev->clock.vco_freq = 360000; /* 3.6 GHz */ 1284 1285 return true; 1286 } 1287 1288 return false; 1289 } 1290 1291 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1292 { 1293 struct radeon_mode_info *mode_info = &rdev->mode_info; 1294 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1295 union igp_info *igp_info; 1296 u8 frev, crev; 1297 u16 data_offset; 1298 1299 /* sideport is AMD only */ 1300 if (rdev->family == CHIP_RS600) 1301 return false; 1302 1303 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1304 &frev, &crev, &data_offset)) { 1305 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1306 data_offset); 1307 switch (crev) { 1308 case 1: 1309 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1310 return true; 1311 break; 1312 case 2: 1313 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1314 return true; 1315 break; 1316 default: 1317 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1318 break; 1319 } 1320 } 1321 return false; 1322 } 1323 1324 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1325 struct radeon_encoder_int_tmds *tmds) 1326 { 1327 struct drm_device *dev = encoder->base.dev; 1328 struct radeon_device *rdev = dev->dev_private; 1329 struct radeon_mode_info *mode_info = &rdev->mode_info; 1330 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1331 uint16_t data_offset; 1332 struct _ATOM_TMDS_INFO *tmds_info; 1333 uint8_t frev, crev; 1334 uint16_t maxfreq; 1335 int i; 1336 1337 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1338 &frev, &crev, &data_offset)) { 1339 tmds_info = 1340 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1341 data_offset); 1342 1343 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1344 for (i = 0; i < 4; i++) { 1345 tmds->tmds_pll[i].freq = 1346 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1347 tmds->tmds_pll[i].value = 1348 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1349 tmds->tmds_pll[i].value |= 1350 (tmds_info->asMiscInfo[i]. 1351 ucPLL_VCO_Gain & 0x3f) << 6; 1352 tmds->tmds_pll[i].value |= 1353 (tmds_info->asMiscInfo[i]. 1354 ucPLL_DutyCycle & 0xf) << 12; 1355 tmds->tmds_pll[i].value |= 1356 (tmds_info->asMiscInfo[i]. 1357 ucPLL_VoltageSwing & 0xf) << 16; 1358 1359 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1360 tmds->tmds_pll[i].freq, 1361 tmds->tmds_pll[i].value); 1362 1363 if (maxfreq == tmds->tmds_pll[i].freq) { 1364 tmds->tmds_pll[i].freq = 0xffffffff; 1365 break; 1366 } 1367 } 1368 return true; 1369 } 1370 return false; 1371 } 1372 1373 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1374 struct radeon_atom_ss *ss, 1375 int id) 1376 { 1377 struct radeon_mode_info *mode_info = &rdev->mode_info; 1378 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1379 uint16_t data_offset, size; 1380 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1381 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1382 uint8_t frev, crev; 1383 int i, num_indices; 1384 1385 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1386 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1387 &frev, &crev, &data_offset)) { 1388 ss_info = 1389 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1390 1391 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1392 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1393 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1394 ((u8 *)&ss_info->asSS_Info[0]); 1395 for (i = 0; i < num_indices; i++) { 1396 if (ss_assign->ucSS_Id == id) { 1397 ss->percentage = 1398 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1399 ss->type = ss_assign->ucSpreadSpectrumType; 1400 ss->step = ss_assign->ucSS_Step; 1401 ss->delay = ss_assign->ucSS_Delay; 1402 ss->range = ss_assign->ucSS_Range; 1403 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1404 return true; 1405 } 1406 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1407 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1408 } 1409 } 1410 return false; 1411 } 1412 1413 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1414 struct radeon_atom_ss *ss, 1415 int id) 1416 { 1417 struct radeon_mode_info *mode_info = &rdev->mode_info; 1418 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1419 u16 data_offset, size; 1420 union igp_info *igp_info; 1421 u8 frev, crev; 1422 u16 percentage = 0, rate = 0; 1423 1424 /* get any igp specific overrides */ 1425 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1426 &frev, &crev, &data_offset)) { 1427 igp_info = (union igp_info *) 1428 (mode_info->atom_context->bios + data_offset); 1429 switch (crev) { 1430 case 6: 1431 switch (id) { 1432 case ASIC_INTERNAL_SS_ON_TMDS: 1433 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1434 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1435 break; 1436 case ASIC_INTERNAL_SS_ON_HDMI: 1437 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1438 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1439 break; 1440 case ASIC_INTERNAL_SS_ON_LVDS: 1441 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1442 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1443 break; 1444 } 1445 break; 1446 case 7: 1447 switch (id) { 1448 case ASIC_INTERNAL_SS_ON_TMDS: 1449 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1450 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1451 break; 1452 case ASIC_INTERNAL_SS_ON_HDMI: 1453 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1454 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1455 break; 1456 case ASIC_INTERNAL_SS_ON_LVDS: 1457 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1458 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1459 break; 1460 } 1461 break; 1462 case 8: 1463 switch (id) { 1464 case ASIC_INTERNAL_SS_ON_TMDS: 1465 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1466 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1467 break; 1468 case ASIC_INTERNAL_SS_ON_HDMI: 1469 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1470 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1471 break; 1472 case ASIC_INTERNAL_SS_ON_LVDS: 1473 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1474 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1475 break; 1476 } 1477 break; 1478 default: 1479 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1480 break; 1481 } 1482 if (percentage) 1483 ss->percentage = percentage; 1484 if (rate) 1485 ss->rate = rate; 1486 } 1487 } 1488 1489 union asic_ss_info { 1490 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1491 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1492 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1493 }; 1494 1495 union asic_ss_assignment { 1496 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1497 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1498 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1499 }; 1500 1501 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1502 struct radeon_atom_ss *ss, 1503 int id, u32 clock) 1504 { 1505 struct radeon_mode_info *mode_info = &rdev->mode_info; 1506 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1507 uint16_t data_offset, size; 1508 union asic_ss_info *ss_info; 1509 union asic_ss_assignment *ss_assign; 1510 uint8_t frev, crev; 1511 int i, num_indices; 1512 1513 if (id == ASIC_INTERNAL_MEMORY_SS) { 1514 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1515 return false; 1516 } 1517 if (id == ASIC_INTERNAL_ENGINE_SS) { 1518 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1519 return false; 1520 } 1521 1522 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1523 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1524 &frev, &crev, &data_offset)) { 1525 1526 ss_info = 1527 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1528 1529 switch (frev) { 1530 case 1: 1531 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1532 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1533 1534 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1535 for (i = 0; i < num_indices; i++) { 1536 if ((ss_assign->v1.ucClockIndication == id) && 1537 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1538 ss->percentage = 1539 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1540 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1541 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1542 ss->percentage_divider = 100; 1543 return true; 1544 } 1545 ss_assign = (union asic_ss_assignment *) 1546 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1547 } 1548 break; 1549 case 2: 1550 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1551 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1552 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1553 for (i = 0; i < num_indices; i++) { 1554 if ((ss_assign->v2.ucClockIndication == id) && 1555 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1556 ss->percentage = 1557 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1558 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1559 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1560 ss->percentage_divider = 100; 1561 if ((crev == 2) && 1562 ((id == ASIC_INTERNAL_ENGINE_SS) || 1563 (id == ASIC_INTERNAL_MEMORY_SS))) 1564 ss->rate /= 100; 1565 return true; 1566 } 1567 ss_assign = (union asic_ss_assignment *) 1568 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1569 } 1570 break; 1571 case 3: 1572 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1573 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1574 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1575 for (i = 0; i < num_indices; i++) { 1576 if ((ss_assign->v3.ucClockIndication == id) && 1577 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1578 ss->percentage = 1579 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1580 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1581 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1582 if (ss_assign->v3.ucSpreadSpectrumMode & 1583 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1584 ss->percentage_divider = 1000; 1585 else 1586 ss->percentage_divider = 100; 1587 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1588 (id == ASIC_INTERNAL_MEMORY_SS)) 1589 ss->rate /= 100; 1590 if (rdev->flags & RADEON_IS_IGP) 1591 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1592 return true; 1593 } 1594 ss_assign = (union asic_ss_assignment *) 1595 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1596 } 1597 break; 1598 default: 1599 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1600 break; 1601 } 1602 1603 } 1604 return false; 1605 } 1606 1607 union lvds_info { 1608 struct _ATOM_LVDS_INFO info; 1609 struct _ATOM_LVDS_INFO_V12 info_12; 1610 }; 1611 1612 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1613 radeon_encoder 1614 *encoder) 1615 { 1616 struct drm_device *dev = encoder->base.dev; 1617 struct radeon_device *rdev = dev->dev_private; 1618 struct radeon_mode_info *mode_info = &rdev->mode_info; 1619 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1620 uint16_t data_offset, misc; 1621 union lvds_info *lvds_info; 1622 uint8_t frev, crev; 1623 struct radeon_encoder_atom_dig *lvds = NULL; 1624 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1625 1626 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1627 &frev, &crev, &data_offset)) { 1628 lvds_info = 1629 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1630 lvds = 1631 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1632 1633 if (!lvds) 1634 return NULL; 1635 1636 lvds->native_mode.clock = 1637 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1638 lvds->native_mode.hdisplay = 1639 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1640 lvds->native_mode.vdisplay = 1641 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1642 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1643 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1644 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1645 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1646 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1648 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1649 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1650 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1651 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1652 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1654 lvds->panel_pwr_delay = 1655 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1656 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1657 1658 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1659 if (misc & ATOM_VSYNC_POLARITY) 1660 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1661 if (misc & ATOM_HSYNC_POLARITY) 1662 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1663 if (misc & ATOM_COMPOSITESYNC) 1664 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1665 if (misc & ATOM_INTERLACE) 1666 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1667 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1668 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1669 1670 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1671 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1672 1673 /* set crtc values */ 1674 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1675 1676 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1677 1678 encoder->native_mode = lvds->native_mode; 1679 1680 if (encoder_enum == 2) 1681 lvds->linkb = true; 1682 else 1683 lvds->linkb = false; 1684 1685 /* parse the lcd record table */ 1686 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1687 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1688 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1689 bool bad_record = false; 1690 u8 *record; 1691 1692 if ((frev == 1) && (crev < 2)) 1693 /* absolute */ 1694 record = (u8 *)(mode_info->atom_context->bios + 1695 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1696 else 1697 /* relative */ 1698 record = (u8 *)(mode_info->atom_context->bios + 1699 data_offset + 1700 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1701 while (*record != ATOM_RECORD_END_TYPE) { 1702 switch (*record) { 1703 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1704 record += sizeof(ATOM_PATCH_RECORD_MODE); 1705 break; 1706 case LCD_RTS_RECORD_TYPE: 1707 record += sizeof(ATOM_LCD_RTS_RECORD); 1708 break; 1709 case LCD_CAP_RECORD_TYPE: 1710 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1711 break; 1712 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1713 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1714 if (fake_edid_record->ucFakeEDIDLength) { 1715 struct edid *edid; 1716 int edid_size = 1717 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1718 edid = kmalloc(edid_size, GFP_KERNEL); 1719 if (edid) { 1720 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1721 fake_edid_record->ucFakeEDIDLength); 1722 1723 if (drm_edid_is_valid(edid)) { 1724 rdev->mode_info.bios_hardcoded_edid = edid; 1725 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1726 } else 1727 kfree(edid); 1728 } 1729 } 1730 record += fake_edid_record->ucFakeEDIDLength ? 1731 struct_size(fake_edid_record, 1732 ucFakeEDIDString, 1733 fake_edid_record->ucFakeEDIDLength) : 1734 /* empty fake edid record must be 3 bytes long */ 1735 sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1; 1736 break; 1737 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1738 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1739 lvds->native_mode.width_mm = panel_res_record->usHSize; 1740 lvds->native_mode.height_mm = panel_res_record->usVSize; 1741 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1742 break; 1743 default: 1744 DRM_ERROR("Bad LCD record %d\n", *record); 1745 bad_record = true; 1746 break; 1747 } 1748 if (bad_record) 1749 break; 1750 } 1751 } 1752 } 1753 return lvds; 1754 } 1755 1756 struct radeon_encoder_primary_dac * 1757 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1758 { 1759 struct drm_device *dev = encoder->base.dev; 1760 struct radeon_device *rdev = dev->dev_private; 1761 struct radeon_mode_info *mode_info = &rdev->mode_info; 1762 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1763 uint16_t data_offset; 1764 struct _COMPASSIONATE_DATA *dac_info; 1765 uint8_t frev, crev; 1766 uint8_t bg, dac; 1767 struct radeon_encoder_primary_dac *p_dac = NULL; 1768 1769 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1770 &frev, &crev, &data_offset)) { 1771 dac_info = (struct _COMPASSIONATE_DATA *) 1772 (mode_info->atom_context->bios + data_offset); 1773 1774 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1775 1776 if (!p_dac) 1777 return NULL; 1778 1779 bg = dac_info->ucDAC1_BG_Adjustment; 1780 dac = dac_info->ucDAC1_DAC_Adjustment; 1781 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1782 1783 } 1784 return p_dac; 1785 } 1786 1787 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1788 struct drm_display_mode *mode) 1789 { 1790 struct radeon_mode_info *mode_info = &rdev->mode_info; 1791 ATOM_ANALOG_TV_INFO *tv_info; 1792 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1793 ATOM_DTD_FORMAT *dtd_timings; 1794 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1795 u8 frev, crev; 1796 u16 data_offset, misc; 1797 1798 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1799 &frev, &crev, &data_offset)) 1800 return false; 1801 1802 switch (crev) { 1803 case 1: 1804 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1805 if (index >= MAX_SUPPORTED_TV_TIMING) 1806 return false; 1807 1808 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1809 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1810 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1811 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1812 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1813 1814 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1815 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1816 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1817 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1818 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1819 1820 mode->flags = 0; 1821 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1822 if (misc & ATOM_VSYNC_POLARITY) 1823 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1824 if (misc & ATOM_HSYNC_POLARITY) 1825 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1826 if (misc & ATOM_COMPOSITESYNC) 1827 mode->flags |= DRM_MODE_FLAG_CSYNC; 1828 if (misc & ATOM_INTERLACE) 1829 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1830 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1831 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1832 1833 mode->crtc_clock = mode->clock = 1834 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1835 1836 if (index == 1) { 1837 /* PAL timings appear to have wrong values for totals */ 1838 mode->crtc_htotal -= 1; 1839 mode->crtc_vtotal -= 1; 1840 } 1841 break; 1842 case 2: 1843 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1844 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1845 return false; 1846 1847 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1848 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1849 le16_to_cpu(dtd_timings->usHBlanking_Time); 1850 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1851 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1852 le16_to_cpu(dtd_timings->usHSyncOffset); 1853 mode->crtc_hsync_end = mode->crtc_hsync_start + 1854 le16_to_cpu(dtd_timings->usHSyncWidth); 1855 1856 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1857 le16_to_cpu(dtd_timings->usVBlanking_Time); 1858 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1859 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1860 le16_to_cpu(dtd_timings->usVSyncOffset); 1861 mode->crtc_vsync_end = mode->crtc_vsync_start + 1862 le16_to_cpu(dtd_timings->usVSyncWidth); 1863 1864 mode->flags = 0; 1865 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1866 if (misc & ATOM_VSYNC_POLARITY) 1867 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1868 if (misc & ATOM_HSYNC_POLARITY) 1869 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1870 if (misc & ATOM_COMPOSITESYNC) 1871 mode->flags |= DRM_MODE_FLAG_CSYNC; 1872 if (misc & ATOM_INTERLACE) 1873 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1874 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1875 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1876 1877 mode->crtc_clock = mode->clock = 1878 le16_to_cpu(dtd_timings->usPixClk) * 10; 1879 break; 1880 } 1881 return true; 1882 } 1883 1884 enum radeon_tv_std 1885 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1886 { 1887 struct radeon_mode_info *mode_info = &rdev->mode_info; 1888 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1889 uint16_t data_offset; 1890 uint8_t frev, crev; 1891 struct _ATOM_ANALOG_TV_INFO *tv_info; 1892 enum radeon_tv_std tv_std = TV_STD_NTSC; 1893 1894 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1895 &frev, &crev, &data_offset)) { 1896 1897 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1898 (mode_info->atom_context->bios + data_offset); 1899 1900 switch (tv_info->ucTV_BootUpDefaultStandard) { 1901 case ATOM_TV_NTSC: 1902 tv_std = TV_STD_NTSC; 1903 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1904 break; 1905 case ATOM_TV_NTSCJ: 1906 tv_std = TV_STD_NTSC_J; 1907 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1908 break; 1909 case ATOM_TV_PAL: 1910 tv_std = TV_STD_PAL; 1911 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1912 break; 1913 case ATOM_TV_PALM: 1914 tv_std = TV_STD_PAL_M; 1915 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1916 break; 1917 case ATOM_TV_PALN: 1918 tv_std = TV_STD_PAL_N; 1919 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1920 break; 1921 case ATOM_TV_PALCN: 1922 tv_std = TV_STD_PAL_CN; 1923 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1924 break; 1925 case ATOM_TV_PAL60: 1926 tv_std = TV_STD_PAL_60; 1927 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1928 break; 1929 case ATOM_TV_SECAM: 1930 tv_std = TV_STD_SECAM; 1931 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1932 break; 1933 default: 1934 tv_std = TV_STD_NTSC; 1935 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1936 break; 1937 } 1938 } 1939 return tv_std; 1940 } 1941 1942 struct radeon_encoder_tv_dac * 1943 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1944 { 1945 struct drm_device *dev = encoder->base.dev; 1946 struct radeon_device *rdev = dev->dev_private; 1947 struct radeon_mode_info *mode_info = &rdev->mode_info; 1948 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1949 uint16_t data_offset; 1950 struct _COMPASSIONATE_DATA *dac_info; 1951 uint8_t frev, crev; 1952 uint8_t bg, dac; 1953 struct radeon_encoder_tv_dac *tv_dac = NULL; 1954 1955 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1956 &frev, &crev, &data_offset)) { 1957 1958 dac_info = (struct _COMPASSIONATE_DATA *) 1959 (mode_info->atom_context->bios + data_offset); 1960 1961 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1962 1963 if (!tv_dac) 1964 return NULL; 1965 1966 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1967 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1968 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1969 1970 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1971 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1972 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1973 1974 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1975 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1976 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1977 1978 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1979 } 1980 return tv_dac; 1981 } 1982 1983 static const char *thermal_controller_names[] = { 1984 "NONE", 1985 "lm63", 1986 "adm1032", 1987 "adm1030", 1988 "max6649", 1989 "lm63", /* lm64 */ 1990 "f75375", 1991 "asc7xxx", 1992 }; 1993 1994 static const char *pp_lib_thermal_controller_names[] = { 1995 "NONE", 1996 "lm63", 1997 "adm1032", 1998 "adm1030", 1999 "max6649", 2000 "lm63", /* lm64 */ 2001 "f75375", 2002 "RV6xx", 2003 "RV770", 2004 "adt7473", 2005 "NONE", 2006 "External GPIO", 2007 "Evergreen", 2008 "emc2103", 2009 "Sumo", 2010 "Northern Islands", 2011 "Southern Islands", 2012 "lm96163", 2013 "Sea Islands", 2014 }; 2015 2016 union power_info { 2017 struct _ATOM_POWERPLAY_INFO info; 2018 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2019 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2020 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2021 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2022 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2023 }; 2024 2025 union pplib_clock_info { 2026 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2027 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2028 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2029 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2030 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2031 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2032 }; 2033 2034 union pplib_power_state { 2035 struct _ATOM_PPLIB_STATE v1; 2036 struct _ATOM_PPLIB_STATE_V2 v2; 2037 }; 2038 2039 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2040 int state_index, 2041 u32 misc, u32 misc2) 2042 { 2043 rdev->pm.power_state[state_index].misc = misc; 2044 rdev->pm.power_state[state_index].misc2 = misc2; 2045 /* order matters! */ 2046 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2047 rdev->pm.power_state[state_index].type = 2048 POWER_STATE_TYPE_POWERSAVE; 2049 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2050 rdev->pm.power_state[state_index].type = 2051 POWER_STATE_TYPE_BATTERY; 2052 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2053 rdev->pm.power_state[state_index].type = 2054 POWER_STATE_TYPE_BATTERY; 2055 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2056 rdev->pm.power_state[state_index].type = 2057 POWER_STATE_TYPE_BALANCED; 2058 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2059 rdev->pm.power_state[state_index].type = 2060 POWER_STATE_TYPE_PERFORMANCE; 2061 rdev->pm.power_state[state_index].flags &= 2062 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2063 } 2064 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2065 rdev->pm.power_state[state_index].type = 2066 POWER_STATE_TYPE_BALANCED; 2067 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2068 rdev->pm.power_state[state_index].type = 2069 POWER_STATE_TYPE_DEFAULT; 2070 rdev->pm.default_power_state_index = state_index; 2071 rdev->pm.power_state[state_index].default_clock_mode = 2072 &rdev->pm.power_state[state_index].clock_info[0]; 2073 } else if (state_index == 0) { 2074 rdev->pm.power_state[state_index].clock_info[0].flags |= 2075 RADEON_PM_MODE_NO_DISPLAY; 2076 } 2077 } 2078 2079 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2080 { 2081 struct radeon_mode_info *mode_info = &rdev->mode_info; 2082 u32 misc, misc2 = 0; 2083 int num_modes = 0, i; 2084 int state_index = 0; 2085 struct radeon_i2c_bus_rec i2c_bus; 2086 union power_info *power_info; 2087 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2088 u16 data_offset; 2089 u8 frev, crev; 2090 2091 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2092 &frev, &crev, &data_offset)) 2093 return state_index; 2094 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2095 2096 /* add the i2c bus for thermal/fan chip */ 2097 if ((power_info->info.ucOverdriveThermalController > 0) && 2098 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2099 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2100 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2101 power_info->info.ucOverdriveControllerAddress >> 1); 2102 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2103 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2104 if (rdev->pm.i2c_bus) { 2105 struct i2c_board_info info = { }; 2106 const char *name = thermal_controller_names[power_info->info. 2107 ucOverdriveThermalController]; 2108 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2109 strscpy(info.type, name, sizeof(info.type)); 2110 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2111 } 2112 } 2113 num_modes = power_info->info.ucNumOfPowerModeEntries; 2114 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2115 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2116 if (num_modes == 0) 2117 return state_index; 2118 rdev->pm.power_state = kcalloc(num_modes, 2119 sizeof(struct radeon_power_state), 2120 GFP_KERNEL); 2121 if (!rdev->pm.power_state) 2122 return state_index; 2123 /* last mode is usually default, array is low to high */ 2124 for (i = 0; i < num_modes; i++) { 2125 /* avoid memory leaks from invalid modes or unknown frev. */ 2126 if (!rdev->pm.power_state[state_index].clock_info) { 2127 rdev->pm.power_state[state_index].clock_info = 2128 kzalloc(sizeof(struct radeon_pm_clock_info), 2129 GFP_KERNEL); 2130 } 2131 if (!rdev->pm.power_state[state_index].clock_info) 2132 goto out; 2133 rdev->pm.power_state[state_index].num_clock_modes = 1; 2134 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2135 switch (frev) { 2136 case 1: 2137 rdev->pm.power_state[state_index].clock_info[0].mclk = 2138 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2139 rdev->pm.power_state[state_index].clock_info[0].sclk = 2140 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2141 /* skip invalid modes */ 2142 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2143 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2144 continue; 2145 rdev->pm.power_state[state_index].pcie_lanes = 2146 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2147 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2148 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2149 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2150 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2151 VOLTAGE_GPIO; 2152 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2153 radeon_atombios_lookup_gpio(rdev, 2154 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2155 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2156 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2157 true; 2158 else 2159 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2160 false; 2161 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2162 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2163 VOLTAGE_VDDC; 2164 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2165 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2166 } 2167 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2168 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2169 state_index++; 2170 break; 2171 case 2: 2172 rdev->pm.power_state[state_index].clock_info[0].mclk = 2173 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2174 rdev->pm.power_state[state_index].clock_info[0].sclk = 2175 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2176 /* skip invalid modes */ 2177 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2178 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2179 continue; 2180 rdev->pm.power_state[state_index].pcie_lanes = 2181 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2182 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2183 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2184 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2185 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2186 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2187 VOLTAGE_GPIO; 2188 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2189 radeon_atombios_lookup_gpio(rdev, 2190 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2191 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2192 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2193 true; 2194 else 2195 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2196 false; 2197 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2198 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2199 VOLTAGE_VDDC; 2200 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2201 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2202 } 2203 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2204 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2205 state_index++; 2206 break; 2207 case 3: 2208 rdev->pm.power_state[state_index].clock_info[0].mclk = 2209 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2210 rdev->pm.power_state[state_index].clock_info[0].sclk = 2211 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2212 /* skip invalid modes */ 2213 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2214 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2215 continue; 2216 rdev->pm.power_state[state_index].pcie_lanes = 2217 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2218 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2219 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2220 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2221 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2222 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2223 VOLTAGE_GPIO; 2224 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2225 radeon_atombios_lookup_gpio(rdev, 2226 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2227 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2228 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2229 true; 2230 else 2231 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2232 false; 2233 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2234 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2235 VOLTAGE_VDDC; 2236 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2237 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2238 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2239 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2240 true; 2241 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2242 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2243 } 2244 } 2245 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2246 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2247 state_index++; 2248 break; 2249 } 2250 } 2251 out: 2252 /* free any unused clock_info allocation. */ 2253 if (state_index && state_index < num_modes) { 2254 kfree(rdev->pm.power_state[state_index].clock_info); 2255 rdev->pm.power_state[state_index].clock_info = NULL; 2256 } 2257 2258 /* last mode is usually default */ 2259 if (state_index && rdev->pm.default_power_state_index == -1) { 2260 rdev->pm.power_state[state_index - 1].type = 2261 POWER_STATE_TYPE_DEFAULT; 2262 rdev->pm.default_power_state_index = state_index - 1; 2263 rdev->pm.power_state[state_index - 1].default_clock_mode = 2264 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2265 rdev->pm.power_state[state_index - 1].flags &= 2266 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2267 rdev->pm.power_state[state_index - 1].misc = 0; 2268 rdev->pm.power_state[state_index - 1].misc2 = 0; 2269 } 2270 return state_index; 2271 } 2272 2273 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2274 ATOM_PPLIB_THERMALCONTROLLER *controller) 2275 { 2276 struct radeon_i2c_bus_rec i2c_bus; 2277 2278 /* add the i2c bus for thermal/fan chip */ 2279 if (controller->ucType > 0) { 2280 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2281 rdev->pm.no_fan = true; 2282 rdev->pm.fan_pulses_per_revolution = 2283 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2284 if (rdev->pm.fan_pulses_per_revolution) { 2285 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2286 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2287 } 2288 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2289 DRM_INFO("Internal thermal controller %s fan control\n", 2290 (controller->ucFanParameters & 2291 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2292 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2293 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2294 DRM_INFO("Internal thermal controller %s fan control\n", 2295 (controller->ucFanParameters & 2296 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2297 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2298 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2299 DRM_INFO("Internal thermal controller %s fan control\n", 2300 (controller->ucFanParameters & 2301 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2302 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2303 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2304 DRM_INFO("Internal thermal controller %s fan control\n", 2305 (controller->ucFanParameters & 2306 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2307 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2308 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2309 DRM_INFO("Internal thermal controller %s fan control\n", 2310 (controller->ucFanParameters & 2311 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2312 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2313 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2314 DRM_INFO("Internal thermal controller %s fan control\n", 2315 (controller->ucFanParameters & 2316 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2317 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2318 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2319 DRM_INFO("Internal thermal controller %s fan control\n", 2320 (controller->ucFanParameters & 2321 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2322 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2323 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2324 DRM_INFO("Internal thermal controller %s fan control\n", 2325 (controller->ucFanParameters & 2326 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2327 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2328 } else if (controller->ucType == 2329 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2330 DRM_INFO("External GPIO thermal controller %s fan control\n", 2331 (controller->ucFanParameters & 2332 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2333 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2334 } else if (controller->ucType == 2335 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2336 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2337 (controller->ucFanParameters & 2338 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2339 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2340 } else if (controller->ucType == 2341 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2342 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2343 (controller->ucFanParameters & 2344 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2345 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2346 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2347 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2348 pp_lib_thermal_controller_names[controller->ucType], 2349 controller->ucI2cAddress >> 1, 2350 (controller->ucFanParameters & 2351 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2352 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2353 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2354 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2355 if (rdev->pm.i2c_bus) { 2356 struct i2c_board_info info = { }; 2357 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2358 info.addr = controller->ucI2cAddress >> 1; 2359 strscpy(info.type, name, sizeof(info.type)); 2360 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2361 } 2362 } else { 2363 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2364 controller->ucType, 2365 controller->ucI2cAddress >> 1, 2366 (controller->ucFanParameters & 2367 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2368 } 2369 } 2370 } 2371 2372 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2373 u16 *vddc, u16 *vddci, u16 *mvdd) 2374 { 2375 struct radeon_mode_info *mode_info = &rdev->mode_info; 2376 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2377 u8 frev, crev; 2378 u16 data_offset; 2379 union firmware_info *firmware_info; 2380 2381 *vddc = 0; 2382 *vddci = 0; 2383 *mvdd = 0; 2384 2385 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2386 &frev, &crev, &data_offset)) { 2387 firmware_info = 2388 (union firmware_info *)(mode_info->atom_context->bios + 2389 data_offset); 2390 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2391 if ((frev == 2) && (crev >= 2)) { 2392 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2393 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2394 } 2395 } 2396 } 2397 2398 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2399 int state_index, int mode_index, 2400 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2401 { 2402 int j; 2403 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2404 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2405 u16 vddc, vddci, mvdd; 2406 2407 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2408 2409 rdev->pm.power_state[state_index].misc = misc; 2410 rdev->pm.power_state[state_index].misc2 = misc2; 2411 rdev->pm.power_state[state_index].pcie_lanes = 2412 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2413 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2414 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2415 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2416 rdev->pm.power_state[state_index].type = 2417 POWER_STATE_TYPE_BATTERY; 2418 break; 2419 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2420 rdev->pm.power_state[state_index].type = 2421 POWER_STATE_TYPE_BALANCED; 2422 break; 2423 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2424 rdev->pm.power_state[state_index].type = 2425 POWER_STATE_TYPE_PERFORMANCE; 2426 break; 2427 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2428 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2429 rdev->pm.power_state[state_index].type = 2430 POWER_STATE_TYPE_PERFORMANCE; 2431 break; 2432 } 2433 rdev->pm.power_state[state_index].flags = 0; 2434 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2435 rdev->pm.power_state[state_index].flags |= 2436 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2437 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2438 rdev->pm.power_state[state_index].type = 2439 POWER_STATE_TYPE_DEFAULT; 2440 rdev->pm.default_power_state_index = state_index; 2441 rdev->pm.power_state[state_index].default_clock_mode = 2442 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2443 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2444 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2445 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2446 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2447 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2448 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2449 } else { 2450 u16 max_vddci = 0; 2451 2452 if (ASIC_IS_DCE4(rdev)) 2453 radeon_atom_get_max_voltage(rdev, 2454 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2455 &max_vddci); 2456 /* patch the table values with the default sclk/mclk from firmware info */ 2457 for (j = 0; j < mode_index; j++) { 2458 rdev->pm.power_state[state_index].clock_info[j].mclk = 2459 rdev->clock.default_mclk; 2460 rdev->pm.power_state[state_index].clock_info[j].sclk = 2461 rdev->clock.default_sclk; 2462 if (vddc) 2463 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2464 vddc; 2465 if (max_vddci) 2466 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2467 max_vddci; 2468 } 2469 } 2470 } 2471 } 2472 2473 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2474 int state_index, int mode_index, 2475 union pplib_clock_info *clock_info) 2476 { 2477 u32 sclk, mclk; 2478 u16 vddc; 2479 2480 if (rdev->flags & RADEON_IS_IGP) { 2481 if (rdev->family >= CHIP_PALM) { 2482 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2483 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2484 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2485 } else { 2486 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2487 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2488 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2489 } 2490 } else if (rdev->family >= CHIP_BONAIRE) { 2491 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2492 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2493 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2494 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2495 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2496 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2497 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2498 VOLTAGE_NONE; 2499 } else if (rdev->family >= CHIP_TAHITI) { 2500 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2501 sclk |= clock_info->si.ucEngineClockHigh << 16; 2502 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2503 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2504 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2505 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2506 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2507 VOLTAGE_SW; 2508 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2509 le16_to_cpu(clock_info->si.usVDDC); 2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2511 le16_to_cpu(clock_info->si.usVDDCI); 2512 } else if (rdev->family >= CHIP_CEDAR) { 2513 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2514 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2515 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2516 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2517 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2518 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2519 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2520 VOLTAGE_SW; 2521 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2522 le16_to_cpu(clock_info->evergreen.usVDDC); 2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2524 le16_to_cpu(clock_info->evergreen.usVDDCI); 2525 } else { 2526 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2527 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2528 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2529 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2530 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2531 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2532 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2533 VOLTAGE_SW; 2534 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2535 le16_to_cpu(clock_info->r600.usVDDC); 2536 } 2537 2538 /* patch up vddc if necessary */ 2539 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2540 case ATOM_VIRTUAL_VOLTAGE_ID0: 2541 case ATOM_VIRTUAL_VOLTAGE_ID1: 2542 case ATOM_VIRTUAL_VOLTAGE_ID2: 2543 case ATOM_VIRTUAL_VOLTAGE_ID3: 2544 case ATOM_VIRTUAL_VOLTAGE_ID4: 2545 case ATOM_VIRTUAL_VOLTAGE_ID5: 2546 case ATOM_VIRTUAL_VOLTAGE_ID6: 2547 case ATOM_VIRTUAL_VOLTAGE_ID7: 2548 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2549 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2550 &vddc) == 0) 2551 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2552 break; 2553 default: 2554 break; 2555 } 2556 2557 if (rdev->flags & RADEON_IS_IGP) { 2558 /* skip invalid modes */ 2559 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2560 return false; 2561 } else { 2562 /* skip invalid modes */ 2563 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2564 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2565 return false; 2566 } 2567 return true; 2568 } 2569 2570 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2571 { 2572 struct radeon_mode_info *mode_info = &rdev->mode_info; 2573 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2574 union pplib_power_state *power_state; 2575 int i, j; 2576 int state_index = 0, mode_index = 0; 2577 union pplib_clock_info *clock_info; 2578 bool valid; 2579 union power_info *power_info; 2580 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2581 u16 data_offset; 2582 u8 frev, crev; 2583 2584 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2585 &frev, &crev, &data_offset)) 2586 return state_index; 2587 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2588 2589 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2590 if (power_info->pplib.ucNumStates == 0) 2591 return state_index; 2592 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates, 2593 sizeof(struct radeon_power_state), 2594 GFP_KERNEL); 2595 if (!rdev->pm.power_state) 2596 return state_index; 2597 /* first mode is usually default, followed by low to high */ 2598 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2599 mode_index = 0; 2600 power_state = (union pplib_power_state *) 2601 (mode_info->atom_context->bios + data_offset + 2602 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2603 i * power_info->pplib.ucStateEntrySize); 2604 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2605 (mode_info->atom_context->bios + data_offset + 2606 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2607 (power_state->v1.ucNonClockStateIndex * 2608 power_info->pplib.ucNonClockSize)); 2609 rdev->pm.power_state[i].clock_info = 2610 kcalloc((power_info->pplib.ucStateEntrySize - 1) ? 2611 (power_info->pplib.ucStateEntrySize - 1) : 1, 2612 sizeof(struct radeon_pm_clock_info), 2613 GFP_KERNEL); 2614 if (!rdev->pm.power_state[i].clock_info) 2615 return state_index; 2616 if (power_info->pplib.ucStateEntrySize - 1) { 2617 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2618 clock_info = (union pplib_clock_info *) 2619 (mode_info->atom_context->bios + data_offset + 2620 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2621 (power_state->v1.ucClockStateIndices[j] * 2622 power_info->pplib.ucClockInfoSize)); 2623 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2624 state_index, mode_index, 2625 clock_info); 2626 if (valid) 2627 mode_index++; 2628 } 2629 } else { 2630 rdev->pm.power_state[state_index].clock_info[0].mclk = 2631 rdev->clock.default_mclk; 2632 rdev->pm.power_state[state_index].clock_info[0].sclk = 2633 rdev->clock.default_sclk; 2634 mode_index++; 2635 } 2636 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2637 if (mode_index) { 2638 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2639 non_clock_info); 2640 state_index++; 2641 } 2642 } 2643 /* if multiple clock modes, mark the lowest as no display */ 2644 for (i = 0; i < state_index; i++) { 2645 if (rdev->pm.power_state[i].num_clock_modes > 1) 2646 rdev->pm.power_state[i].clock_info[0].flags |= 2647 RADEON_PM_MODE_NO_DISPLAY; 2648 } 2649 /* first mode is usually default */ 2650 if (rdev->pm.default_power_state_index == -1) { 2651 rdev->pm.power_state[0].type = 2652 POWER_STATE_TYPE_DEFAULT; 2653 rdev->pm.default_power_state_index = 0; 2654 rdev->pm.power_state[0].default_clock_mode = 2655 &rdev->pm.power_state[0].clock_info[0]; 2656 } 2657 return state_index; 2658 } 2659 2660 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2661 { 2662 struct radeon_mode_info *mode_info = &rdev->mode_info; 2663 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2664 union pplib_power_state *power_state; 2665 int i, j, non_clock_array_index, clock_array_index; 2666 int state_index = 0, mode_index = 0; 2667 union pplib_clock_info *clock_info; 2668 struct _StateArray *state_array; 2669 struct _ClockInfoArray *clock_info_array; 2670 struct _NonClockInfoArray *non_clock_info_array; 2671 bool valid; 2672 union power_info *power_info; 2673 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2674 u16 data_offset; 2675 u8 frev, crev; 2676 u8 *power_state_offset; 2677 2678 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2679 &frev, &crev, &data_offset)) 2680 return state_index; 2681 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2682 2683 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2684 state_array = (struct _StateArray *) 2685 (mode_info->atom_context->bios + data_offset + 2686 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2687 clock_info_array = (struct _ClockInfoArray *) 2688 (mode_info->atom_context->bios + data_offset + 2689 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2690 non_clock_info_array = (struct _NonClockInfoArray *) 2691 (mode_info->atom_context->bios + data_offset + 2692 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2693 if (state_array->ucNumEntries == 0) 2694 return state_index; 2695 rdev->pm.power_state = kcalloc(state_array->ucNumEntries, 2696 sizeof(struct radeon_power_state), 2697 GFP_KERNEL); 2698 if (!rdev->pm.power_state) 2699 return state_index; 2700 power_state_offset = (u8 *)state_array->states; 2701 for (i = 0; i < state_array->ucNumEntries; i++) { 2702 mode_index = 0; 2703 power_state = (union pplib_power_state *)power_state_offset; 2704 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2705 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2706 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2707 rdev->pm.power_state[i].clock_info = 2708 kcalloc(power_state->v2.ucNumDPMLevels ? 2709 power_state->v2.ucNumDPMLevels : 1, 2710 sizeof(struct radeon_pm_clock_info), 2711 GFP_KERNEL); 2712 if (!rdev->pm.power_state[i].clock_info) 2713 return state_index; 2714 if (power_state->v2.ucNumDPMLevels) { 2715 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2716 clock_array_index = power_state->v2.clockInfoIndex[j]; 2717 clock_info = (union pplib_clock_info *) 2718 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2719 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2720 state_index, mode_index, 2721 clock_info); 2722 if (valid) 2723 mode_index++; 2724 } 2725 } else { 2726 rdev->pm.power_state[state_index].clock_info[0].mclk = 2727 rdev->clock.default_mclk; 2728 rdev->pm.power_state[state_index].clock_info[0].sclk = 2729 rdev->clock.default_sclk; 2730 mode_index++; 2731 } 2732 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2733 if (mode_index) { 2734 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2735 non_clock_info); 2736 state_index++; 2737 } 2738 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2739 } 2740 /* if multiple clock modes, mark the lowest as no display */ 2741 for (i = 0; i < state_index; i++) { 2742 if (rdev->pm.power_state[i].num_clock_modes > 1) 2743 rdev->pm.power_state[i].clock_info[0].flags |= 2744 RADEON_PM_MODE_NO_DISPLAY; 2745 } 2746 /* first mode is usually default */ 2747 if (rdev->pm.default_power_state_index == -1) { 2748 rdev->pm.power_state[0].type = 2749 POWER_STATE_TYPE_DEFAULT; 2750 rdev->pm.default_power_state_index = 0; 2751 rdev->pm.power_state[0].default_clock_mode = 2752 &rdev->pm.power_state[0].clock_info[0]; 2753 } 2754 return state_index; 2755 } 2756 2757 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2758 { 2759 struct radeon_mode_info *mode_info = &rdev->mode_info; 2760 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2761 u16 data_offset; 2762 u8 frev, crev; 2763 int state_index = 0; 2764 2765 rdev->pm.default_power_state_index = -1; 2766 2767 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2768 &frev, &crev, &data_offset)) { 2769 switch (frev) { 2770 case 1: 2771 case 2: 2772 case 3: 2773 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2774 break; 2775 case 4: 2776 case 5: 2777 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2778 break; 2779 case 6: 2780 state_index = radeon_atombios_parse_power_table_6(rdev); 2781 break; 2782 default: 2783 break; 2784 } 2785 } 2786 2787 if (state_index == 0) { 2788 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2789 if (rdev->pm.power_state) { 2790 rdev->pm.power_state[0].clock_info = 2791 kcalloc(1, 2792 sizeof(struct radeon_pm_clock_info), 2793 GFP_KERNEL); 2794 if (rdev->pm.power_state[0].clock_info) { 2795 /* add the default mode */ 2796 rdev->pm.power_state[state_index].type = 2797 POWER_STATE_TYPE_DEFAULT; 2798 rdev->pm.power_state[state_index].num_clock_modes = 1; 2799 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2800 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2801 rdev->pm.power_state[state_index].default_clock_mode = 2802 &rdev->pm.power_state[state_index].clock_info[0]; 2803 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2804 rdev->pm.power_state[state_index].pcie_lanes = 16; 2805 rdev->pm.default_power_state_index = state_index; 2806 rdev->pm.power_state[state_index].flags = 0; 2807 state_index++; 2808 } 2809 } 2810 } 2811 2812 rdev->pm.num_power_states = state_index; 2813 2814 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2815 rdev->pm.current_clock_mode_index = 0; 2816 if (rdev->pm.default_power_state_index >= 0) 2817 rdev->pm.current_vddc = 2818 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2819 else 2820 rdev->pm.current_vddc = 0; 2821 } 2822 2823 union get_clock_dividers { 2824 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2825 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2826 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2828 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2829 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2830 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2831 }; 2832 2833 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2834 u8 clock_type, 2835 u32 clock, 2836 bool strobe_mode, 2837 struct atom_clock_dividers *dividers) 2838 { 2839 union get_clock_dividers args; 2840 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2841 u8 frev, crev; 2842 2843 memset(&args, 0, sizeof(args)); 2844 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2845 2846 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2847 return -EINVAL; 2848 2849 switch (crev) { 2850 case 1: 2851 /* r4xx, r5xx */ 2852 args.v1.ucAction = clock_type; 2853 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2854 2855 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2856 2857 dividers->post_div = args.v1.ucPostDiv; 2858 dividers->fb_div = args.v1.ucFbDiv; 2859 dividers->enable_post_div = true; 2860 break; 2861 case 2: 2862 case 3: 2863 case 5: 2864 /* r6xx, r7xx, evergreen, ni, si */ 2865 if (rdev->family <= CHIP_RV770) { 2866 args.v2.ucAction = clock_type; 2867 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2868 2869 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2870 2871 dividers->post_div = args.v2.ucPostDiv; 2872 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2873 dividers->ref_div = args.v2.ucAction; 2874 if (rdev->family == CHIP_RV770) { 2875 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2876 true : false; 2877 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2878 } else 2879 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2880 } else { 2881 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2882 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2883 2884 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2885 2886 dividers->post_div = args.v3.ucPostDiv; 2887 dividers->enable_post_div = (args.v3.ucCntlFlag & 2888 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2889 dividers->enable_dithen = (args.v3.ucCntlFlag & 2890 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2891 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2892 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2893 dividers->ref_div = args.v3.ucRefDiv; 2894 dividers->vco_mode = (args.v3.ucCntlFlag & 2895 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2896 } else { 2897 /* for SI we use ComputeMemoryClockParam for memory plls */ 2898 if (rdev->family >= CHIP_TAHITI) 2899 return -EINVAL; 2900 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2901 if (strobe_mode) 2902 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2903 2904 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2905 2906 dividers->post_div = args.v5.ucPostDiv; 2907 dividers->enable_post_div = (args.v5.ucCntlFlag & 2908 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2909 dividers->enable_dithen = (args.v5.ucCntlFlag & 2910 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2911 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2912 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2913 dividers->ref_div = args.v5.ucRefDiv; 2914 dividers->vco_mode = (args.v5.ucCntlFlag & 2915 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2916 } 2917 } 2918 break; 2919 case 4: 2920 /* fusion */ 2921 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2922 2923 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2924 2925 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2926 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2927 break; 2928 case 6: 2929 /* CI */ 2930 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2931 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2932 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2933 2934 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2935 2936 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2937 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2938 dividers->ref_div = args.v6_out.ucPllRefDiv; 2939 dividers->post_div = args.v6_out.ucPllPostDiv; 2940 dividers->flags = args.v6_out.ucPllCntlFlag; 2941 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2942 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2943 break; 2944 default: 2945 return -EINVAL; 2946 } 2947 return 0; 2948 } 2949 2950 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2951 u32 clock, 2952 bool strobe_mode, 2953 struct atom_mpll_param *mpll_param) 2954 { 2955 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2956 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2957 u8 frev, crev; 2958 2959 memset(&args, 0, sizeof(args)); 2960 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2961 2962 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2963 return -EINVAL; 2964 2965 switch (frev) { 2966 case 2: 2967 switch (crev) { 2968 case 1: 2969 /* SI */ 2970 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2971 args.ucInputFlag = 0; 2972 if (strobe_mode) 2973 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2974 2975 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2976 2977 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2978 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2979 mpll_param->post_div = args.ucPostDiv; 2980 mpll_param->dll_speed = args.ucDllSpeed; 2981 mpll_param->bwcntl = args.ucBWCntl; 2982 mpll_param->vco_mode = 2983 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2984 mpll_param->yclk_sel = 2985 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2986 mpll_param->qdr = 2987 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2988 mpll_param->half_rate = 2989 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2990 break; 2991 default: 2992 return -EINVAL; 2993 } 2994 break; 2995 default: 2996 return -EINVAL; 2997 } 2998 return 0; 2999 } 3000 3001 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 3002 { 3003 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 3004 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 3005 3006 args.ucEnable = enable; 3007 3008 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3009 } 3010 3011 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 3012 { 3013 GET_ENGINE_CLOCK_PS_ALLOCATION args; 3014 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 3015 3016 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3017 return le32_to_cpu(args.ulReturnEngineClock); 3018 } 3019 3020 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 3021 { 3022 GET_MEMORY_CLOCK_PS_ALLOCATION args; 3023 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 3024 3025 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3026 return le32_to_cpu(args.ulReturnMemoryClock); 3027 } 3028 3029 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 3030 uint32_t eng_clock) 3031 { 3032 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3033 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3034 3035 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3036 3037 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3038 } 3039 3040 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3041 uint32_t mem_clock) 3042 { 3043 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3044 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3045 3046 if (rdev->flags & RADEON_IS_IGP) 3047 return; 3048 3049 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3050 3051 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3052 } 3053 3054 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3055 u32 eng_clock, u32 mem_clock) 3056 { 3057 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3058 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3059 u32 tmp; 3060 3061 memset(&args, 0, sizeof(args)); 3062 3063 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3064 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3065 3066 args.ulTargetEngineClock = cpu_to_le32(tmp); 3067 if (mem_clock) 3068 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3069 3070 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3071 } 3072 3073 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3074 u32 mem_clock) 3075 { 3076 u32 args; 3077 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3078 3079 args = cpu_to_le32(mem_clock); /* 10 khz */ 3080 3081 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3082 } 3083 3084 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3085 u32 mem_clock) 3086 { 3087 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3088 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3089 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3090 3091 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3092 3093 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3094 } 3095 3096 union set_voltage { 3097 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3098 struct _SET_VOLTAGE_PARAMETERS v1; 3099 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3100 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3101 }; 3102 3103 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3104 { 3105 union set_voltage args; 3106 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3107 u8 frev, crev, volt_index = voltage_level; 3108 3109 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3110 return; 3111 3112 /* 0xff01 is a flag rather then an actual voltage */ 3113 if (voltage_level == 0xff01) 3114 return; 3115 3116 switch (crev) { 3117 case 1: 3118 args.v1.ucVoltageType = voltage_type; 3119 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3120 args.v1.ucVoltageIndex = volt_index; 3121 break; 3122 case 2: 3123 args.v2.ucVoltageType = voltage_type; 3124 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3125 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3126 break; 3127 case 3: 3128 args.v3.ucVoltageType = voltage_type; 3129 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3130 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3131 break; 3132 default: 3133 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3134 return; 3135 } 3136 3137 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3138 } 3139 3140 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3141 u16 voltage_id, u16 *voltage) 3142 { 3143 union set_voltage args; 3144 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3145 u8 frev, crev; 3146 3147 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3148 return -EINVAL; 3149 3150 switch (crev) { 3151 case 1: 3152 return -EINVAL; 3153 case 2: 3154 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3155 args.v2.ucVoltageMode = 0; 3156 args.v2.usVoltageLevel = 0; 3157 3158 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3159 3160 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3161 break; 3162 case 3: 3163 args.v3.ucVoltageType = voltage_type; 3164 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3165 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3166 3167 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3168 3169 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3170 break; 3171 default: 3172 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3173 return -EINVAL; 3174 } 3175 3176 return 0; 3177 } 3178 3179 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3180 u16 *voltage, 3181 u16 leakage_idx) 3182 { 3183 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3184 } 3185 3186 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3187 u16 *leakage_id) 3188 { 3189 union set_voltage args; 3190 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3191 u8 frev, crev; 3192 3193 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3194 return -EINVAL; 3195 3196 switch (crev) { 3197 case 3: 3198 case 4: 3199 args.v3.ucVoltageType = 0; 3200 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3201 args.v3.usVoltageLevel = 0; 3202 3203 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3204 3205 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3206 break; 3207 default: 3208 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3209 return -EINVAL; 3210 } 3211 3212 return 0; 3213 } 3214 3215 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3216 u16 *vddc, u16 *vddci, 3217 u16 virtual_voltage_id, 3218 u16 vbios_voltage_id) 3219 { 3220 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3221 u8 frev, crev; 3222 u16 data_offset, size; 3223 int i, j; 3224 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3225 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3226 3227 *vddc = 0; 3228 *vddci = 0; 3229 3230 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3231 &frev, &crev, &data_offset)) 3232 return -EINVAL; 3233 3234 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3235 (rdev->mode_info.atom_context->bios + data_offset); 3236 3237 switch (frev) { 3238 case 1: 3239 return -EINVAL; 3240 case 2: 3241 switch (crev) { 3242 case 1: 3243 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3244 return -EINVAL; 3245 leakage_bin = (u16 *) 3246 (rdev->mode_info.atom_context->bios + data_offset + 3247 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3248 vddc_id_buf = (u16 *) 3249 (rdev->mode_info.atom_context->bios + data_offset + 3250 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3251 vddc_buf = (u16 *) 3252 (rdev->mode_info.atom_context->bios + data_offset + 3253 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3254 vddci_id_buf = (u16 *) 3255 (rdev->mode_info.atom_context->bios + data_offset + 3256 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3257 vddci_buf = (u16 *) 3258 (rdev->mode_info.atom_context->bios + data_offset + 3259 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3260 3261 if (profile->ucElbVDDC_Num > 0) { 3262 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3263 if (vddc_id_buf[i] == virtual_voltage_id) { 3264 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3265 if (vbios_voltage_id <= leakage_bin[j]) { 3266 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3267 break; 3268 } 3269 } 3270 break; 3271 } 3272 } 3273 } 3274 if (profile->ucElbVDDCI_Num > 0) { 3275 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3276 if (vddci_id_buf[i] == virtual_voltage_id) { 3277 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3278 if (vbios_voltage_id <= leakage_bin[j]) { 3279 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3280 break; 3281 } 3282 } 3283 break; 3284 } 3285 } 3286 } 3287 break; 3288 default: 3289 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3290 return -EINVAL; 3291 } 3292 break; 3293 default: 3294 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3295 return -EINVAL; 3296 } 3297 3298 return 0; 3299 } 3300 3301 union get_voltage_info { 3302 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3303 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3304 }; 3305 3306 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3307 u16 virtual_voltage_id, 3308 u16 *voltage) 3309 { 3310 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3311 u32 entry_id; 3312 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3313 union get_voltage_info args; 3314 3315 for (entry_id = 0; entry_id < count; entry_id++) { 3316 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3317 virtual_voltage_id) 3318 break; 3319 } 3320 3321 if (entry_id >= count) 3322 return -EINVAL; 3323 3324 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3325 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3326 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3327 args.in.ulSCLKFreq = 3328 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3329 3330 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3331 3332 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3333 3334 return 0; 3335 } 3336 3337 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3338 u16 voltage_level, u8 voltage_type, 3339 u32 *gpio_value, u32 *gpio_mask) 3340 { 3341 union set_voltage args; 3342 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3343 u8 frev, crev; 3344 3345 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3346 return -EINVAL; 3347 3348 switch (crev) { 3349 case 1: 3350 return -EINVAL; 3351 case 2: 3352 args.v2.ucVoltageType = voltage_type; 3353 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3354 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3355 3356 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3357 3358 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3359 3360 args.v2.ucVoltageType = voltage_type; 3361 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3362 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3363 3364 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 3365 3366 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3367 break; 3368 default: 3369 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3370 return -EINVAL; 3371 } 3372 3373 return 0; 3374 } 3375 3376 union voltage_object_info { 3377 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3378 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3379 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3380 }; 3381 3382 union voltage_object { 3383 struct _ATOM_VOLTAGE_OBJECT v1; 3384 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3385 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3386 }; 3387 3388 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3389 u8 voltage_type) 3390 { 3391 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3392 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3393 u8 *start = (u8 *)v1; 3394 3395 while (offset < size) { 3396 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3397 if (vo->ucVoltageType == voltage_type) 3398 return vo; 3399 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3400 vo->asFormula.ucNumOfVoltageEntries; 3401 } 3402 return NULL; 3403 } 3404 3405 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3406 u8 voltage_type) 3407 { 3408 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3409 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3410 u8 *start = (u8 *)v2; 3411 3412 while (offset < size) { 3413 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3414 if (vo->ucVoltageType == voltage_type) 3415 return vo; 3416 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3417 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3418 } 3419 return NULL; 3420 } 3421 3422 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3423 u8 voltage_type, u8 voltage_mode) 3424 { 3425 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3426 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3427 u8 *start = (u8 *)v3; 3428 3429 while (offset < size) { 3430 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3431 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3432 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3433 return vo; 3434 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3435 } 3436 return NULL; 3437 } 3438 3439 bool 3440 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3441 u8 voltage_type, u8 voltage_mode) 3442 { 3443 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3444 u8 frev, crev; 3445 u16 data_offset, size; 3446 union voltage_object_info *voltage_info; 3447 union voltage_object *voltage_object = NULL; 3448 3449 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3450 &frev, &crev, &data_offset)) { 3451 voltage_info = (union voltage_object_info *) 3452 (rdev->mode_info.atom_context->bios + data_offset); 3453 3454 switch (frev) { 3455 case 1: 3456 case 2: 3457 switch (crev) { 3458 case 1: 3459 voltage_object = (union voltage_object *) 3460 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3461 if (voltage_object && 3462 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3463 return true; 3464 break; 3465 case 2: 3466 voltage_object = (union voltage_object *) 3467 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3468 if (voltage_object && 3469 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3470 return true; 3471 break; 3472 default: 3473 DRM_ERROR("unknown voltage object table\n"); 3474 return false; 3475 } 3476 break; 3477 case 3: 3478 switch (crev) { 3479 case 1: 3480 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3481 voltage_type, voltage_mode)) 3482 return true; 3483 break; 3484 default: 3485 DRM_ERROR("unknown voltage object table\n"); 3486 return false; 3487 } 3488 break; 3489 default: 3490 DRM_ERROR("unknown voltage object table\n"); 3491 return false; 3492 } 3493 3494 } 3495 return false; 3496 } 3497 3498 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3499 u8 voltage_type, 3500 u8 *svd_gpio_id, u8 *svc_gpio_id) 3501 { 3502 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3503 u8 frev, crev; 3504 u16 data_offset, size; 3505 union voltage_object_info *voltage_info; 3506 union voltage_object *voltage_object = NULL; 3507 3508 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3509 &frev, &crev, &data_offset)) { 3510 voltage_info = (union voltage_object_info *) 3511 (rdev->mode_info.atom_context->bios + data_offset); 3512 3513 switch (frev) { 3514 case 3: 3515 switch (crev) { 3516 case 1: 3517 voltage_object = (union voltage_object *) 3518 atom_lookup_voltage_object_v3(&voltage_info->v3, 3519 voltage_type, 3520 VOLTAGE_OBJ_SVID2); 3521 if (voltage_object) { 3522 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3523 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3524 } else { 3525 return -EINVAL; 3526 } 3527 break; 3528 default: 3529 DRM_ERROR("unknown voltage object table\n"); 3530 return -EINVAL; 3531 } 3532 break; 3533 default: 3534 DRM_ERROR("unknown voltage object table\n"); 3535 return -EINVAL; 3536 } 3537 3538 } 3539 return 0; 3540 } 3541 3542 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3543 u8 voltage_type, u16 *max_voltage) 3544 { 3545 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3546 u8 frev, crev; 3547 u16 data_offset, size; 3548 union voltage_object_info *voltage_info; 3549 union voltage_object *voltage_object = NULL; 3550 3551 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3552 &frev, &crev, &data_offset)) { 3553 voltage_info = (union voltage_object_info *) 3554 (rdev->mode_info.atom_context->bios + data_offset); 3555 3556 switch (crev) { 3557 case 1: 3558 voltage_object = (union voltage_object *) 3559 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3560 if (voltage_object) { 3561 ATOM_VOLTAGE_FORMULA *formula = 3562 &voltage_object->v1.asFormula; 3563 if (formula->ucFlag & 1) 3564 *max_voltage = 3565 le16_to_cpu(formula->usVoltageBaseLevel) + 3566 formula->ucNumOfVoltageEntries / 2 * 3567 le16_to_cpu(formula->usVoltageStep); 3568 else 3569 *max_voltage = 3570 le16_to_cpu(formula->usVoltageBaseLevel) + 3571 (formula->ucNumOfVoltageEntries - 1) * 3572 le16_to_cpu(formula->usVoltageStep); 3573 return 0; 3574 } 3575 break; 3576 case 2: 3577 voltage_object = (union voltage_object *) 3578 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3579 if (voltage_object) { 3580 ATOM_VOLTAGE_FORMULA_V2 *formula = 3581 &voltage_object->v2.asFormula; 3582 if (formula->ucNumOfVoltageEntries) { 3583 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3584 ((u8 *)&formula->asVIDAdjustEntries[0] + 3585 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3586 *max_voltage = 3587 le16_to_cpu(lut->usVoltageValue); 3588 return 0; 3589 } 3590 } 3591 break; 3592 default: 3593 DRM_ERROR("unknown voltage object table\n"); 3594 return -EINVAL; 3595 } 3596 3597 } 3598 return -EINVAL; 3599 } 3600 3601 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3602 u8 voltage_type, u16 *min_voltage) 3603 { 3604 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3605 u8 frev, crev; 3606 u16 data_offset, size; 3607 union voltage_object_info *voltage_info; 3608 union voltage_object *voltage_object = NULL; 3609 3610 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3611 &frev, &crev, &data_offset)) { 3612 voltage_info = (union voltage_object_info *) 3613 (rdev->mode_info.atom_context->bios + data_offset); 3614 3615 switch (crev) { 3616 case 1: 3617 voltage_object = (union voltage_object *) 3618 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3619 if (voltage_object) { 3620 ATOM_VOLTAGE_FORMULA *formula = 3621 &voltage_object->v1.asFormula; 3622 *min_voltage = 3623 le16_to_cpu(formula->usVoltageBaseLevel); 3624 return 0; 3625 } 3626 break; 3627 case 2: 3628 voltage_object = (union voltage_object *) 3629 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3630 if (voltage_object) { 3631 ATOM_VOLTAGE_FORMULA_V2 *formula = 3632 &voltage_object->v2.asFormula; 3633 if (formula->ucNumOfVoltageEntries) { 3634 *min_voltage = 3635 le16_to_cpu(formula->asVIDAdjustEntries[ 3636 0 3637 ].usVoltageValue); 3638 return 0; 3639 } 3640 } 3641 break; 3642 default: 3643 DRM_ERROR("unknown voltage object table\n"); 3644 return -EINVAL; 3645 } 3646 3647 } 3648 return -EINVAL; 3649 } 3650 3651 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3652 u8 voltage_type, u16 *voltage_step) 3653 { 3654 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3655 u8 frev, crev; 3656 u16 data_offset, size; 3657 union voltage_object_info *voltage_info; 3658 union voltage_object *voltage_object = NULL; 3659 3660 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3661 &frev, &crev, &data_offset)) { 3662 voltage_info = (union voltage_object_info *) 3663 (rdev->mode_info.atom_context->bios + data_offset); 3664 3665 switch (crev) { 3666 case 1: 3667 voltage_object = (union voltage_object *) 3668 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3669 if (voltage_object) { 3670 ATOM_VOLTAGE_FORMULA *formula = 3671 &voltage_object->v1.asFormula; 3672 if (formula->ucFlag & 1) 3673 *voltage_step = 3674 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3675 else 3676 *voltage_step = 3677 le16_to_cpu(formula->usVoltageStep); 3678 return 0; 3679 } 3680 break; 3681 case 2: 3682 return -EINVAL; 3683 default: 3684 DRM_ERROR("unknown voltage object table\n"); 3685 return -EINVAL; 3686 } 3687 3688 } 3689 return -EINVAL; 3690 } 3691 3692 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3693 u8 voltage_type, 3694 u16 nominal_voltage, 3695 u16 *true_voltage) 3696 { 3697 u16 min_voltage, max_voltage, voltage_step; 3698 3699 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3700 return -EINVAL; 3701 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3702 return -EINVAL; 3703 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3704 return -EINVAL; 3705 3706 if (nominal_voltage <= min_voltage) 3707 *true_voltage = min_voltage; 3708 else if (nominal_voltage >= max_voltage) 3709 *true_voltage = max_voltage; 3710 else 3711 *true_voltage = min_voltage + 3712 ((nominal_voltage - min_voltage) / voltage_step) * 3713 voltage_step; 3714 3715 return 0; 3716 } 3717 3718 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3719 u8 voltage_type, u8 voltage_mode, 3720 struct atom_voltage_table *voltage_table) 3721 { 3722 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3723 u8 frev, crev; 3724 u16 data_offset, size; 3725 int i, ret; 3726 union voltage_object_info *voltage_info; 3727 union voltage_object *voltage_object = NULL; 3728 3729 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3730 &frev, &crev, &data_offset)) { 3731 voltage_info = (union voltage_object_info *) 3732 (rdev->mode_info.atom_context->bios + data_offset); 3733 3734 switch (frev) { 3735 case 1: 3736 case 2: 3737 switch (crev) { 3738 case 1: 3739 DRM_ERROR("old table version %d, %d\n", frev, crev); 3740 return -EINVAL; 3741 case 2: 3742 voltage_object = (union voltage_object *) 3743 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3744 if (voltage_object) { 3745 ATOM_VOLTAGE_FORMULA_V2 *formula = 3746 &voltage_object->v2.asFormula; 3747 VOLTAGE_LUT_ENTRY *lut; 3748 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3749 return -EINVAL; 3750 lut = &formula->asVIDAdjustEntries[0]; 3751 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3752 voltage_table->entries[i].value = 3753 le16_to_cpu(lut->usVoltageValue); 3754 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3755 voltage_table->entries[i].value, 3756 voltage_type, 3757 &voltage_table->entries[i].smio_low, 3758 &voltage_table->mask_low); 3759 if (ret) 3760 return ret; 3761 lut = (VOLTAGE_LUT_ENTRY *) 3762 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3763 } 3764 voltage_table->count = formula->ucNumOfVoltageEntries; 3765 return 0; 3766 } 3767 break; 3768 default: 3769 DRM_ERROR("unknown voltage object table\n"); 3770 return -EINVAL; 3771 } 3772 break; 3773 case 3: 3774 switch (crev) { 3775 case 1: 3776 voltage_object = (union voltage_object *) 3777 atom_lookup_voltage_object_v3(&voltage_info->v3, 3778 voltage_type, voltage_mode); 3779 if (voltage_object) { 3780 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3781 &voltage_object->v3.asGpioVoltageObj; 3782 VOLTAGE_LUT_ENTRY_V2 *lut; 3783 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3784 return -EINVAL; 3785 lut = &gpio->asVolGpioLut[0]; 3786 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3787 voltage_table->entries[i].value = 3788 le16_to_cpu(lut->usVoltageValue); 3789 voltage_table->entries[i].smio_low = 3790 le32_to_cpu(lut->ulVoltageId); 3791 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3792 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3793 } 3794 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3795 voltage_table->count = gpio->ucGpioEntryNum; 3796 voltage_table->phase_delay = gpio->ucPhaseDelay; 3797 return 0; 3798 } 3799 break; 3800 default: 3801 DRM_ERROR("unknown voltage object table\n"); 3802 return -EINVAL; 3803 } 3804 break; 3805 default: 3806 DRM_ERROR("unknown voltage object table\n"); 3807 return -EINVAL; 3808 } 3809 } 3810 return -EINVAL; 3811 } 3812 3813 union vram_info { 3814 struct _ATOM_VRAM_INFO_V3 v1_3; 3815 struct _ATOM_VRAM_INFO_V4 v1_4; 3816 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3817 }; 3818 3819 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3820 u8 module_index, struct atom_memory_info *mem_info) 3821 { 3822 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3823 u8 frev, crev, i; 3824 u16 data_offset, size; 3825 union vram_info *vram_info; 3826 3827 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3828 3829 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3830 &frev, &crev, &data_offset)) { 3831 vram_info = (union vram_info *) 3832 (rdev->mode_info.atom_context->bios + data_offset); 3833 switch (frev) { 3834 case 1: 3835 switch (crev) { 3836 case 3: 3837 /* r6xx */ 3838 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3839 ATOM_VRAM_MODULE_V3 *vram_module = 3840 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3841 3842 for (i = 0; i < module_index; i++) { 3843 if (le16_to_cpu(vram_module->usSize) == 0) 3844 return -EINVAL; 3845 vram_module = (ATOM_VRAM_MODULE_V3 *) 3846 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3847 } 3848 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3849 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3850 } else 3851 return -EINVAL; 3852 break; 3853 case 4: 3854 /* r7xx, evergreen */ 3855 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3856 ATOM_VRAM_MODULE_V4 *vram_module = 3857 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3858 3859 for (i = 0; i < module_index; i++) { 3860 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3861 return -EINVAL; 3862 vram_module = (ATOM_VRAM_MODULE_V4 *) 3863 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3864 } 3865 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3866 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3867 } else 3868 return -EINVAL; 3869 break; 3870 default: 3871 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3872 return -EINVAL; 3873 } 3874 break; 3875 case 2: 3876 switch (crev) { 3877 case 1: 3878 /* ni */ 3879 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3880 ATOM_VRAM_MODULE_V7 *vram_module = 3881 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3882 3883 for (i = 0; i < module_index; i++) { 3884 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3885 return -EINVAL; 3886 vram_module = (ATOM_VRAM_MODULE_V7 *) 3887 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3888 } 3889 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3890 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3891 } else 3892 return -EINVAL; 3893 break; 3894 default: 3895 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3896 return -EINVAL; 3897 } 3898 break; 3899 default: 3900 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3901 return -EINVAL; 3902 } 3903 return 0; 3904 } 3905 return -EINVAL; 3906 } 3907 3908 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3909 bool gddr5, u8 module_index, 3910 struct atom_memory_clock_range_table *mclk_range_table) 3911 { 3912 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3913 u8 frev, crev, i; 3914 u16 data_offset, size; 3915 union vram_info *vram_info; 3916 u32 mem_timing_size = gddr5 ? 3917 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3918 3919 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3920 3921 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3922 &frev, &crev, &data_offset)) { 3923 vram_info = (union vram_info *) 3924 (rdev->mode_info.atom_context->bios + data_offset); 3925 switch (frev) { 3926 case 1: 3927 switch (crev) { 3928 case 3: 3929 DRM_ERROR("old table version %d, %d\n", frev, crev); 3930 return -EINVAL; 3931 case 4: 3932 /* r7xx, evergreen */ 3933 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3934 ATOM_VRAM_MODULE_V4 *vram_module = 3935 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3936 ATOM_MEMORY_TIMING_FORMAT *format; 3937 3938 for (i = 0; i < module_index; i++) { 3939 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3940 return -EINVAL; 3941 vram_module = (ATOM_VRAM_MODULE_V4 *) 3942 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3943 } 3944 mclk_range_table->num_entries = (u8) 3945 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3946 mem_timing_size); 3947 format = &vram_module->asMemTiming[0]; 3948 for (i = 0; i < mclk_range_table->num_entries; i++) { 3949 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3950 format = (ATOM_MEMORY_TIMING_FORMAT *) 3951 ((u8 *)format + mem_timing_size); 3952 } 3953 } else 3954 return -EINVAL; 3955 break; 3956 default: 3957 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3958 return -EINVAL; 3959 } 3960 break; 3961 case 2: 3962 DRM_ERROR("new table version %d, %d\n", frev, crev); 3963 return -EINVAL; 3964 default: 3965 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3966 return -EINVAL; 3967 } 3968 return 0; 3969 } 3970 return -EINVAL; 3971 } 3972 3973 #define MEM_ID_MASK 0xff000000 3974 #define MEM_ID_SHIFT 24 3975 #define CLOCK_RANGE_MASK 0x00ffffff 3976 #define CLOCK_RANGE_SHIFT 0 3977 #define LOW_NIBBLE_MASK 0xf 3978 #define DATA_EQU_PREV 0 3979 #define DATA_FROM_TABLE 4 3980 3981 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3982 u8 module_index, 3983 struct atom_mc_reg_table *reg_table) 3984 { 3985 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3986 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3987 u32 i = 0, j; 3988 u16 data_offset, size; 3989 union vram_info *vram_info; 3990 3991 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3992 3993 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3994 &frev, &crev, &data_offset)) { 3995 vram_info = (union vram_info *) 3996 (rdev->mode_info.atom_context->bios + data_offset); 3997 switch (frev) { 3998 case 1: 3999 DRM_ERROR("old table version %d, %d\n", frev, crev); 4000 return -EINVAL; 4001 case 2: 4002 switch (crev) { 4003 case 1: 4004 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 4005 ATOM_INIT_REG_BLOCK *reg_block = 4006 (ATOM_INIT_REG_BLOCK *) 4007 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 4008 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 4009 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4010 ((u8 *)reg_block + (2 * sizeof(u16)) + 4011 le16_to_cpu(reg_block->usRegIndexTblSize)); 4012 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 4013 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 4014 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 4015 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 4016 return -EINVAL; 4017 while (i < num_entries) { 4018 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 4019 break; 4020 reg_table->mc_reg_address[i].s1 = 4021 (u16)(le16_to_cpu(format->usRegIndex)); 4022 reg_table->mc_reg_address[i].pre_reg_data = 4023 (u8)(format->ucPreRegDataLength); 4024 i++; 4025 format = (ATOM_INIT_REG_INDEX_FORMAT *) 4026 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 4027 } 4028 reg_table->last = i; 4029 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4030 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 4031 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4032 >> MEM_ID_SHIFT); 4033 if (module_index == t_mem_id) { 4034 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4035 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4036 >> CLOCK_RANGE_SHIFT); 4037 for (i = 0, j = 1; i < reg_table->last; i++) { 4038 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4039 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4040 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4041 j++; 4042 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4043 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4044 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4045 } 4046 } 4047 num_ranges++; 4048 } 4049 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4050 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4051 } 4052 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4053 return -EINVAL; 4054 reg_table->num_entries = num_ranges; 4055 } else 4056 return -EINVAL; 4057 break; 4058 default: 4059 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4060 return -EINVAL; 4061 } 4062 break; 4063 default: 4064 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4065 return -EINVAL; 4066 } 4067 return 0; 4068 } 4069 return -EINVAL; 4070 } 4071 4072 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4073 { 4074 struct radeon_device *rdev = dev->dev_private; 4075 uint32_t bios_2_scratch, bios_6_scratch; 4076 4077 if (rdev->family >= CHIP_R600) { 4078 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4079 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4080 } else { 4081 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4082 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4083 } 4084 4085 /* let the bios control the backlight */ 4086 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4087 4088 /* tell the bios not to handle mode switching */ 4089 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4090 4091 /* clear the vbios dpms state */ 4092 if (ASIC_IS_DCE4(rdev)) 4093 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4094 4095 if (rdev->family >= CHIP_R600) { 4096 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4097 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4098 } else { 4099 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4100 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4101 } 4102 4103 } 4104 4105 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4106 { 4107 uint32_t scratch_reg; 4108 int i; 4109 4110 if (rdev->family >= CHIP_R600) 4111 scratch_reg = R600_BIOS_0_SCRATCH; 4112 else 4113 scratch_reg = RADEON_BIOS_0_SCRATCH; 4114 4115 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4116 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4117 } 4118 4119 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4120 { 4121 uint32_t scratch_reg; 4122 int i; 4123 4124 if (rdev->family >= CHIP_R600) 4125 scratch_reg = R600_BIOS_0_SCRATCH; 4126 else 4127 scratch_reg = RADEON_BIOS_0_SCRATCH; 4128 4129 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4130 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4131 } 4132 4133 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4134 { 4135 struct drm_device *dev = encoder->dev; 4136 struct radeon_device *rdev = dev->dev_private; 4137 uint32_t bios_6_scratch; 4138 4139 if (rdev->family >= CHIP_R600) 4140 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4141 else 4142 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4143 4144 if (lock) { 4145 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4146 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4147 } else { 4148 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4149 bios_6_scratch |= ATOM_S6_ACC_MODE; 4150 } 4151 4152 if (rdev->family >= CHIP_R600) 4153 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4154 else 4155 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4156 } 4157 4158 /* at some point we may want to break this out into individual functions */ 4159 void 4160 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4161 struct drm_encoder *encoder, 4162 bool connected) 4163 { 4164 struct drm_device *dev = connector->dev; 4165 struct radeon_device *rdev = dev->dev_private; 4166 struct radeon_connector *radeon_connector = 4167 to_radeon_connector(connector); 4168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4169 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4170 4171 if (rdev->family >= CHIP_R600) { 4172 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4173 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4174 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4175 } else { 4176 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4177 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4178 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4179 } 4180 4181 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4182 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4183 if (connected) { 4184 DRM_DEBUG_KMS("TV1 connected\n"); 4185 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4186 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4187 } else { 4188 DRM_DEBUG_KMS("TV1 disconnected\n"); 4189 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4190 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4191 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4192 } 4193 } 4194 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4195 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4196 if (connected) { 4197 DRM_DEBUG_KMS("CV connected\n"); 4198 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4199 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4200 } else { 4201 DRM_DEBUG_KMS("CV disconnected\n"); 4202 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4203 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4204 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4205 } 4206 } 4207 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4208 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4209 if (connected) { 4210 DRM_DEBUG_KMS("LCD1 connected\n"); 4211 bios_0_scratch |= ATOM_S0_LCD1; 4212 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4213 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4214 } else { 4215 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4216 bios_0_scratch &= ~ATOM_S0_LCD1; 4217 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4218 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4219 } 4220 } 4221 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4222 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4223 if (connected) { 4224 DRM_DEBUG_KMS("CRT1 connected\n"); 4225 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4226 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4227 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4228 } else { 4229 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4230 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4231 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4232 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4233 } 4234 } 4235 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4236 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4237 if (connected) { 4238 DRM_DEBUG_KMS("CRT2 connected\n"); 4239 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4240 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4241 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4242 } else { 4243 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4244 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4245 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4246 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4247 } 4248 } 4249 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4250 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4251 if (connected) { 4252 DRM_DEBUG_KMS("DFP1 connected\n"); 4253 bios_0_scratch |= ATOM_S0_DFP1; 4254 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4255 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4256 } else { 4257 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4258 bios_0_scratch &= ~ATOM_S0_DFP1; 4259 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4260 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4261 } 4262 } 4263 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4264 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4265 if (connected) { 4266 DRM_DEBUG_KMS("DFP2 connected\n"); 4267 bios_0_scratch |= ATOM_S0_DFP2; 4268 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4269 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4270 } else { 4271 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4272 bios_0_scratch &= ~ATOM_S0_DFP2; 4273 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4274 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4275 } 4276 } 4277 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4278 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4279 if (connected) { 4280 DRM_DEBUG_KMS("DFP3 connected\n"); 4281 bios_0_scratch |= ATOM_S0_DFP3; 4282 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4283 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4284 } else { 4285 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4286 bios_0_scratch &= ~ATOM_S0_DFP3; 4287 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4288 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4289 } 4290 } 4291 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4292 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4293 if (connected) { 4294 DRM_DEBUG_KMS("DFP4 connected\n"); 4295 bios_0_scratch |= ATOM_S0_DFP4; 4296 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4297 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4298 } else { 4299 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4300 bios_0_scratch &= ~ATOM_S0_DFP4; 4301 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4302 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4303 } 4304 } 4305 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4306 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4307 if (connected) { 4308 DRM_DEBUG_KMS("DFP5 connected\n"); 4309 bios_0_scratch |= ATOM_S0_DFP5; 4310 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4311 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4312 } else { 4313 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4314 bios_0_scratch &= ~ATOM_S0_DFP5; 4315 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4316 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4317 } 4318 } 4319 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4320 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4321 if (connected) { 4322 DRM_DEBUG_KMS("DFP6 connected\n"); 4323 bios_0_scratch |= ATOM_S0_DFP6; 4324 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4325 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4326 } else { 4327 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4328 bios_0_scratch &= ~ATOM_S0_DFP6; 4329 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4330 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4331 } 4332 } 4333 4334 if (rdev->family >= CHIP_R600) { 4335 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4336 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4337 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4338 } else { 4339 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4340 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4341 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4342 } 4343 } 4344 4345 void 4346 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4347 { 4348 struct drm_device *dev = encoder->dev; 4349 struct radeon_device *rdev = dev->dev_private; 4350 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4351 uint32_t bios_3_scratch; 4352 4353 if (ASIC_IS_DCE4(rdev)) 4354 return; 4355 4356 if (rdev->family >= CHIP_R600) 4357 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4358 else 4359 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4360 4361 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4362 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4363 bios_3_scratch |= (crtc << 18); 4364 } 4365 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4366 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4367 bios_3_scratch |= (crtc << 24); 4368 } 4369 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4370 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4371 bios_3_scratch |= (crtc << 16); 4372 } 4373 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4374 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4375 bios_3_scratch |= (crtc << 20); 4376 } 4377 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4378 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4379 bios_3_scratch |= (crtc << 17); 4380 } 4381 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4382 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4383 bios_3_scratch |= (crtc << 19); 4384 } 4385 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4386 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4387 bios_3_scratch |= (crtc << 23); 4388 } 4389 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4390 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4391 bios_3_scratch |= (crtc << 25); 4392 } 4393 4394 if (rdev->family >= CHIP_R600) 4395 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4396 else 4397 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4398 } 4399 4400 void 4401 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4402 { 4403 struct drm_device *dev = encoder->dev; 4404 struct radeon_device *rdev = dev->dev_private; 4405 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4406 uint32_t bios_2_scratch; 4407 4408 if (ASIC_IS_DCE4(rdev)) 4409 return; 4410 4411 if (rdev->family >= CHIP_R600) 4412 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4413 else 4414 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4415 4416 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4417 if (on) 4418 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4419 else 4420 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4421 } 4422 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4423 if (on) 4424 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4425 else 4426 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4427 } 4428 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4429 if (on) 4430 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4431 else 4432 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4433 } 4434 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4435 if (on) 4436 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4437 else 4438 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4439 } 4440 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4441 if (on) 4442 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4443 else 4444 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4445 } 4446 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4447 if (on) 4448 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4449 else 4450 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4451 } 4452 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4453 if (on) 4454 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4455 else 4456 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4457 } 4458 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4459 if (on) 4460 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4461 else 4462 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4463 } 4464 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4465 if (on) 4466 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4467 else 4468 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4469 } 4470 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4471 if (on) 4472 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4473 else 4474 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4475 } 4476 4477 if (rdev->family >= CHIP_R600) 4478 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4479 else 4480 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4481 } 4482