1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <linux/pci.h> 28 29 #include <drm/drm_device.h> 30 #include <drm/drm_edid.h> 31 #include <drm/radeon_drm.h> 32 33 #include "radeon.h" 34 35 #include "atom.h" 36 #include "atom-bits.h" 37 #include "radeon_asic.h" 38 #include "radeon_atombios.h" 39 #include "radeon_legacy_encoders.h" 40 41 union atom_supported_devices { 42 struct _ATOM_SUPPORTED_DEVICES_INFO info; 43 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; 44 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; 45 }; 46 47 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev, 48 ATOM_GPIO_I2C_ASSIGMENT *gpio, 49 u8 index) 50 { 51 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */ 52 if ((rdev->family == CHIP_R420) || 53 (rdev->family == CHIP_R423) || 54 (rdev->family == CHIP_RV410)) { 55 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) || 56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) || 57 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) { 58 gpio->ucClkMaskShift = 0x19; 59 gpio->ucDataMaskShift = 0x18; 60 } 61 } 62 63 /* some evergreen boards have bad data for this entry */ 64 if (ASIC_IS_DCE4(rdev)) { 65 if ((index == 7) && 66 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) && 67 (gpio->sucI2cId.ucAccess == 0)) { 68 gpio->sucI2cId.ucAccess = 0x97; 69 gpio->ucDataMaskShift = 8; 70 gpio->ucDataEnShift = 8; 71 gpio->ucDataY_Shift = 8; 72 gpio->ucDataA_Shift = 8; 73 } 74 } 75 76 /* some DCE3 boards have bad data for this entry */ 77 if (ASIC_IS_DCE3(rdev)) { 78 if ((index == 4) && 79 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) && 80 (gpio->sucI2cId.ucAccess == 0x94)) 81 gpio->sucI2cId.ucAccess = 0x14; 82 } 83 } 84 85 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 86 { 87 struct radeon_i2c_bus_rec i2c; 88 89 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 90 91 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4; 92 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4; 93 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4; 94 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4; 95 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4; 96 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4; 97 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4; 98 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4; 99 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 100 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 101 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 102 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 103 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 104 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 105 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 106 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 107 108 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 109 i2c.hw_capable = true; 110 else 111 i2c.hw_capable = false; 112 113 if (gpio->sucI2cId.ucAccess == 0xa0) 114 i2c.mm_i2c = true; 115 else 116 i2c.mm_i2c = false; 117 118 i2c.i2c_id = gpio->sucI2cId.ucAccess; 119 120 if (i2c.mask_clk_reg) 121 i2c.valid = true; 122 else 123 i2c.valid = false; 124 125 return i2c; 126 } 127 128 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev, 129 uint8_t id) 130 { 131 struct atom_context *ctx = rdev->mode_info.atom_context; 132 ATOM_GPIO_I2C_ASSIGMENT *gpio; 133 struct radeon_i2c_bus_rec i2c; 134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 135 struct _ATOM_GPIO_I2C_INFO *i2c_info; 136 uint16_t data_offset, size; 137 int i, num_indices; 138 139 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); 140 i2c.valid = false; 141 142 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 144 145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 146 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 147 148 gpio = &i2c_info->asGPIO_Info[0]; 149 for (i = 0; i < num_indices; i++) { 150 151 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 152 153 if (gpio->sucI2cId.ucAccess == id) { 154 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 155 break; 156 } 157 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 158 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 159 } 160 } 161 162 return i2c; 163 } 164 165 void radeon_atombios_i2c_init(struct radeon_device *rdev) 166 { 167 struct atom_context *ctx = rdev->mode_info.atom_context; 168 ATOM_GPIO_I2C_ASSIGMENT *gpio; 169 struct radeon_i2c_bus_rec i2c; 170 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 171 struct _ATOM_GPIO_I2C_INFO *i2c_info; 172 uint16_t data_offset, size; 173 int i, num_indices; 174 char stmp[32]; 175 176 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 177 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 178 179 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 180 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 181 182 gpio = &i2c_info->asGPIO_Info[0]; 183 for (i = 0; i < num_indices; i++) { 184 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i); 185 186 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio); 187 188 if (i2c.valid) { 189 sprintf(stmp, "0x%x", i2c.i2c_id); 190 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp); 191 } 192 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 193 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 194 } 195 } 196 } 197 198 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev, 199 u8 id) 200 { 201 struct atom_context *ctx = rdev->mode_info.atom_context; 202 struct radeon_gpio_rec gpio; 203 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 204 struct _ATOM_GPIO_PIN_LUT *gpio_info; 205 ATOM_GPIO_PIN_ASSIGNMENT *pin; 206 u16 data_offset, size; 207 int i, num_indices; 208 209 memset(&gpio, 0, sizeof(struct radeon_gpio_rec)); 210 gpio.valid = false; 211 212 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 213 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 214 215 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 216 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 217 218 pin = gpio_info->asGPIO_Pin; 219 for (i = 0; i < num_indices; i++) { 220 if (id == pin->ucGPIO_ID) { 221 gpio.id = pin->ucGPIO_ID; 222 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4; 223 gpio.shift = pin->ucGpioPinBitShift; 224 gpio.mask = (1 << pin->ucGpioPinBitShift); 225 gpio.valid = true; 226 break; 227 } 228 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 229 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 230 } 231 } 232 233 return gpio; 234 } 235 236 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev, 237 struct radeon_gpio_rec *gpio) 238 { 239 struct radeon_hpd hpd; 240 u32 reg; 241 242 memset(&hpd, 0, sizeof(struct radeon_hpd)); 243 244 if (ASIC_IS_DCE6(rdev)) 245 reg = SI_DC_GPIO_HPD_A; 246 else if (ASIC_IS_DCE4(rdev)) 247 reg = EVERGREEN_DC_GPIO_HPD_A; 248 else 249 reg = AVIVO_DC_GPIO_HPD_A; 250 251 hpd.gpio = *gpio; 252 if (gpio->reg == reg) { 253 switch(gpio->mask) { 254 case (1 << 0): 255 hpd.hpd = RADEON_HPD_1; 256 break; 257 case (1 << 8): 258 hpd.hpd = RADEON_HPD_2; 259 break; 260 case (1 << 16): 261 hpd.hpd = RADEON_HPD_3; 262 break; 263 case (1 << 24): 264 hpd.hpd = RADEON_HPD_4; 265 break; 266 case (1 << 26): 267 hpd.hpd = RADEON_HPD_5; 268 break; 269 case (1 << 28): 270 hpd.hpd = RADEON_HPD_6; 271 break; 272 default: 273 hpd.hpd = RADEON_HPD_NONE; 274 break; 275 } 276 } else 277 hpd.hpd = RADEON_HPD_NONE; 278 return hpd; 279 } 280 281 static bool radeon_atom_apply_quirks(struct drm_device *dev, 282 uint32_t supported_device, 283 int *connector_type, 284 struct radeon_i2c_bus_rec *i2c_bus, 285 uint16_t *line_mux, 286 struct radeon_hpd *hpd) 287 { 288 struct pci_dev *pdev = to_pci_dev(dev->dev); 289 290 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ 291 if ((pdev->device == 0x791e) && 292 (pdev->subsystem_vendor == 0x1043) && 293 (pdev->subsystem_device == 0x826d)) { 294 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 295 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 296 *connector_type = DRM_MODE_CONNECTOR_DVID; 297 } 298 299 /* Asrock RS600 board lists the DVI port as HDMI */ 300 if ((pdev->device == 0x7941) && 301 (pdev->subsystem_vendor == 0x1849) && 302 (pdev->subsystem_device == 0x7941)) { 303 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && 304 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 305 *connector_type = DRM_MODE_CONNECTOR_DVID; 306 } 307 308 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */ 309 if ((pdev->device == 0x796e) && 310 (pdev->subsystem_vendor == 0x1462) && 311 (pdev->subsystem_device == 0x7302)) { 312 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) || 313 (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) 314 return false; 315 } 316 317 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ 318 if ((pdev->device == 0x7941) && 319 (pdev->subsystem_vendor == 0x147b) && 320 (pdev->subsystem_device == 0x2412)) { 321 if (*connector_type == DRM_MODE_CONNECTOR_DVII) 322 return false; 323 } 324 325 /* Falcon NW laptop lists vga ddc line for LVDS */ 326 if ((pdev->device == 0x5653) && 327 (pdev->subsystem_vendor == 0x1462) && 328 (pdev->subsystem_device == 0x0291)) { 329 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) { 330 i2c_bus->valid = false; 331 *line_mux = 53; 332 } 333 } 334 335 /* HIS X1300 is DVI+VGA, not DVI+DVI */ 336 if ((pdev->device == 0x7146) && 337 (pdev->subsystem_vendor == 0x17af) && 338 (pdev->subsystem_device == 0x2058)) { 339 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 340 return false; 341 } 342 343 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */ 344 if ((pdev->device == 0x7142) && 345 (pdev->subsystem_vendor == 0x1458) && 346 (pdev->subsystem_device == 0x2134)) { 347 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT) 348 return false; 349 } 350 351 352 /* Funky macbooks */ 353 if ((pdev->device == 0x71C5) && 354 (pdev->subsystem_vendor == 0x106b) && 355 (pdev->subsystem_device == 0x0080)) { 356 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || 357 (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) 358 return false; 359 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT) 360 *line_mux = 0x90; 361 } 362 363 /* mac rv630, rv730, others */ 364 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) && 365 (*connector_type == DRM_MODE_CONNECTOR_DVII)) { 366 *connector_type = DRM_MODE_CONNECTOR_9PinDIN; 367 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1; 368 } 369 370 /* ASUS HD 3600 XT board lists the DVI port as HDMI */ 371 if ((pdev->device == 0x9598) && 372 (pdev->subsystem_vendor == 0x1043) && 373 (pdev->subsystem_device == 0x01da)) { 374 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 375 *connector_type = DRM_MODE_CONNECTOR_DVII; 376 } 377 } 378 379 /* ASUS HD 3600 board lists the DVI port as HDMI */ 380 if ((pdev->device == 0x9598) && 381 (pdev->subsystem_vendor == 0x1043) && 382 (pdev->subsystem_device == 0x01e4)) { 383 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 384 *connector_type = DRM_MODE_CONNECTOR_DVII; 385 } 386 } 387 388 /* ASUS HD 3450 board lists the DVI port as HDMI */ 389 if ((pdev->device == 0x95C5) && 390 (pdev->subsystem_vendor == 0x1043) && 391 (pdev->subsystem_device == 0x01e2)) { 392 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 393 *connector_type = DRM_MODE_CONNECTOR_DVII; 394 } 395 } 396 397 /* some BIOSes seem to report DAC on HDMI - usually this is a board with 398 * HDMI + VGA reporting as HDMI 399 */ 400 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) { 401 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { 402 *connector_type = DRM_MODE_CONNECTOR_VGA; 403 *line_mux = 0; 404 } 405 } 406 407 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port 408 * on the laptop and a DVI port on the docking station and 409 * both share the same encoder, hpd pin, and ddc line. 410 * So while the bios table is technically correct, 411 * we drop the DVI port here since xrandr has no concept of 412 * encoders and will try and drive both connectors 413 * with different crtcs which isn't possible on the hardware 414 * side and leaves no crtcs for LVDS or VGA. 415 */ 416 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) && 417 (pdev->subsystem_vendor == 0x1025) && 418 (pdev->subsystem_device == 0x013c)) { 419 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) && 420 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) { 421 /* actually it's a DVI-D port not DVI-I */ 422 *connector_type = DRM_MODE_CONNECTOR_DVID; 423 return false; 424 } 425 } 426 427 /* XFX Pine Group device rv730 reports no VGA DDC lines 428 * even though they are wired up to record 0x93 429 */ 430 if ((pdev->device == 0x9498) && 431 (pdev->subsystem_vendor == 0x1682) && 432 (pdev->subsystem_device == 0x2452) && 433 (i2c_bus->valid == false) && 434 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) { 435 struct radeon_device *rdev = dev->dev_private; 436 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); 437 } 438 439 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 440 if (((pdev->device == 0x9802) || 441 (pdev->device == 0x9805) || 442 (pdev->device == 0x9806)) && 443 (pdev->subsystem_vendor == 0x1734) && 444 (pdev->subsystem_device == 0x11bd)) { 445 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 446 *connector_type = DRM_MODE_CONNECTOR_DVII; 447 *line_mux = 0x3103; 448 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) { 449 *connector_type = DRM_MODE_CONNECTOR_DVII; 450 } 451 } 452 453 return true; 454 } 455 456 static const int supported_devices_connector_convert[] = { 457 DRM_MODE_CONNECTOR_Unknown, 458 DRM_MODE_CONNECTOR_VGA, 459 DRM_MODE_CONNECTOR_DVII, 460 DRM_MODE_CONNECTOR_DVID, 461 DRM_MODE_CONNECTOR_DVIA, 462 DRM_MODE_CONNECTOR_SVIDEO, 463 DRM_MODE_CONNECTOR_Composite, 464 DRM_MODE_CONNECTOR_LVDS, 465 DRM_MODE_CONNECTOR_Unknown, 466 DRM_MODE_CONNECTOR_Unknown, 467 DRM_MODE_CONNECTOR_HDMIA, 468 DRM_MODE_CONNECTOR_HDMIB, 469 DRM_MODE_CONNECTOR_Unknown, 470 DRM_MODE_CONNECTOR_Unknown, 471 DRM_MODE_CONNECTOR_9PinDIN, 472 DRM_MODE_CONNECTOR_DisplayPort 473 }; 474 475 static const uint16_t supported_devices_connector_object_id_convert[] = { 476 CONNECTOR_OBJECT_ID_NONE, 477 CONNECTOR_OBJECT_ID_VGA, 478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */ 479 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */ 480 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */ 481 CONNECTOR_OBJECT_ID_COMPOSITE, 482 CONNECTOR_OBJECT_ID_SVIDEO, 483 CONNECTOR_OBJECT_ID_LVDS, 484 CONNECTOR_OBJECT_ID_9PIN_DIN, 485 CONNECTOR_OBJECT_ID_9PIN_DIN, 486 CONNECTOR_OBJECT_ID_DISPLAYPORT, 487 CONNECTOR_OBJECT_ID_HDMI_TYPE_A, 488 CONNECTOR_OBJECT_ID_HDMI_TYPE_B, 489 CONNECTOR_OBJECT_ID_SVIDEO 490 }; 491 492 static const int object_connector_convert[] = { 493 DRM_MODE_CONNECTOR_Unknown, 494 DRM_MODE_CONNECTOR_DVII, 495 DRM_MODE_CONNECTOR_DVII, 496 DRM_MODE_CONNECTOR_DVID, 497 DRM_MODE_CONNECTOR_DVID, 498 DRM_MODE_CONNECTOR_VGA, 499 DRM_MODE_CONNECTOR_Composite, 500 DRM_MODE_CONNECTOR_SVIDEO, 501 DRM_MODE_CONNECTOR_Unknown, 502 DRM_MODE_CONNECTOR_Unknown, 503 DRM_MODE_CONNECTOR_9PinDIN, 504 DRM_MODE_CONNECTOR_Unknown, 505 DRM_MODE_CONNECTOR_HDMIA, 506 DRM_MODE_CONNECTOR_HDMIB, 507 DRM_MODE_CONNECTOR_LVDS, 508 DRM_MODE_CONNECTOR_9PinDIN, 509 DRM_MODE_CONNECTOR_Unknown, 510 DRM_MODE_CONNECTOR_Unknown, 511 DRM_MODE_CONNECTOR_Unknown, 512 DRM_MODE_CONNECTOR_DisplayPort, 513 DRM_MODE_CONNECTOR_eDP, 514 DRM_MODE_CONNECTOR_Unknown 515 }; 516 517 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 518 { 519 struct radeon_device *rdev = dev->dev_private; 520 struct radeon_mode_info *mode_info = &rdev->mode_info; 521 struct atom_context *ctx = mode_info->atom_context; 522 int index = GetIndexIntoMasterTable(DATA, Object_Header); 523 u16 size, data_offset; 524 u8 frev, crev; 525 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 526 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 527 ATOM_OBJECT_TABLE *router_obj; 528 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 529 ATOM_OBJECT_HEADER *obj_header; 530 int i, j, k, path_size, device_support; 531 int connector_type; 532 u16 igp_lane_info, conn_id, connector_object_id; 533 struct radeon_i2c_bus_rec ddc_bus; 534 struct radeon_router router; 535 struct radeon_gpio_rec gpio; 536 struct radeon_hpd hpd; 537 538 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 539 return false; 540 541 if (crev < 2) 542 return false; 543 544 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 545 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 546 (ctx->bios + data_offset + 547 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 548 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 549 (ctx->bios + data_offset + 550 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 551 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 552 (ctx->bios + data_offset + 553 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 554 router_obj = (ATOM_OBJECT_TABLE *) 555 (ctx->bios + data_offset + 556 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 557 device_support = le16_to_cpu(obj_header->usDeviceSupport); 558 559 path_size = 0; 560 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 561 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 562 ATOM_DISPLAY_OBJECT_PATH *path; 563 addr += path_size; 564 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 565 path_size += le16_to_cpu(path->usSize); 566 567 if (device_support & le16_to_cpu(path->usDeviceTag)) { 568 uint8_t con_obj_id, con_obj_num; 569 570 con_obj_id = 571 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 572 >> OBJECT_ID_SHIFT; 573 con_obj_num = 574 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 575 >> ENUM_ID_SHIFT; 576 577 /* TODO CV support */ 578 if (le16_to_cpu(path->usDeviceTag) == 579 ATOM_DEVICE_CV_SUPPORT) 580 continue; 581 582 /* IGP chips */ 583 if ((rdev->flags & RADEON_IS_IGP) && 584 (con_obj_id == 585 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 586 uint16_t igp_offset = 0; 587 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; 588 589 index = 590 GetIndexIntoMasterTable(DATA, 591 IntegratedSystemInfo); 592 593 if (atom_parse_data_header(ctx, index, &size, &frev, 594 &crev, &igp_offset)) { 595 596 if (crev >= 2) { 597 igp_obj = 598 (ATOM_INTEGRATED_SYSTEM_INFO_V2 599 *) (ctx->bios + igp_offset); 600 601 if (igp_obj) { 602 uint32_t slot_config, ct; 603 604 if (con_obj_num == 1) 605 slot_config = 606 igp_obj-> 607 ulDDISlot1Config; 608 else 609 slot_config = 610 igp_obj-> 611 ulDDISlot2Config; 612 613 ct = (slot_config >> 16) & 0xff; 614 connector_type = 615 object_connector_convert 616 [ct]; 617 connector_object_id = ct; 618 igp_lane_info = 619 slot_config & 0xffff; 620 } else 621 continue; 622 } else 623 continue; 624 } else { 625 igp_lane_info = 0; 626 connector_type = 627 object_connector_convert[con_obj_id]; 628 connector_object_id = con_obj_id; 629 } 630 } else { 631 igp_lane_info = 0; 632 connector_type = 633 object_connector_convert[con_obj_id]; 634 connector_object_id = con_obj_id; 635 } 636 637 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 638 continue; 639 640 router.ddc_valid = false; 641 router.cd_valid = false; 642 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 643 uint8_t grph_obj_type = 644 (le16_to_cpu(path->usGraphicObjIds[j]) & 645 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 646 647 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 648 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 649 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 650 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 651 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 652 (ctx->bios + data_offset + 653 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 654 ATOM_ENCODER_CAP_RECORD *cap_record; 655 u16 caps = 0; 656 657 while (record->ucRecordSize > 0 && 658 record->ucRecordType > 0 && 659 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 660 switch (record->ucRecordType) { 661 case ATOM_ENCODER_CAP_RECORD_TYPE: 662 cap_record =(ATOM_ENCODER_CAP_RECORD *) 663 record; 664 caps = le16_to_cpu(cap_record->usEncoderCap); 665 break; 666 } 667 record = (ATOM_COMMON_RECORD_HEADER *) 668 ((char *)record + record->ucRecordSize); 669 } 670 radeon_add_atom_encoder(dev, 671 encoder_obj, 672 le16_to_cpu 673 (path-> 674 usDeviceTag), 675 caps); 676 } 677 } 678 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 679 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 680 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 681 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 682 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 683 (ctx->bios + data_offset + 684 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 685 ATOM_I2C_RECORD *i2c_record; 686 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 687 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 688 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 689 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 690 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 691 (ctx->bios + data_offset + 692 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 693 u8 *num_dst_objs = (u8 *) 694 ((u8 *)router_src_dst_table + 1 + 695 (router_src_dst_table->ucNumberOfSrc * 2)); 696 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 697 int enum_id; 698 699 router.router_id = router_obj_id; 700 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 701 if (le16_to_cpu(path->usConnObjectId) == 702 le16_to_cpu(dst_objs[enum_id])) 703 break; 704 } 705 706 while (record->ucRecordSize > 0 && 707 record->ucRecordType > 0 && 708 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 709 switch (record->ucRecordType) { 710 case ATOM_I2C_RECORD_TYPE: 711 i2c_record = 712 (ATOM_I2C_RECORD *) 713 record; 714 i2c_config = 715 (ATOM_I2C_ID_CONFIG_ACCESS *) 716 &i2c_record->sucI2cId; 717 router.i2c_info = 718 radeon_lookup_i2c_gpio(rdev, 719 i2c_config-> 720 ucAccess); 721 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 722 break; 723 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 724 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 725 record; 726 router.ddc_valid = true; 727 router.ddc_mux_type = ddc_path->ucMuxType; 728 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 729 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 730 break; 731 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 732 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 733 record; 734 router.cd_valid = true; 735 router.cd_mux_type = cd_path->ucMuxType; 736 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 737 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 738 break; 739 } 740 record = (ATOM_COMMON_RECORD_HEADER *) 741 ((char *)record + record->ucRecordSize); 742 } 743 } 744 } 745 } 746 } 747 748 /* look up gpio for ddc, hpd */ 749 ddc_bus.valid = false; 750 hpd.hpd = RADEON_HPD_NONE; 751 if ((le16_to_cpu(path->usDeviceTag) & 752 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 753 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 754 if (le16_to_cpu(path->usConnObjectId) == 755 le16_to_cpu(con_obj->asObjects[j]. 756 usObjectID)) { 757 ATOM_COMMON_RECORD_HEADER 758 *record = 759 (ATOM_COMMON_RECORD_HEADER 760 *) 761 (ctx->bios + data_offset + 762 le16_to_cpu(con_obj-> 763 asObjects[j]. 764 usRecordOffset)); 765 ATOM_I2C_RECORD *i2c_record; 766 ATOM_HPD_INT_RECORD *hpd_record; 767 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 768 769 while (record->ucRecordSize > 0 && 770 record->ucRecordType > 0 && 771 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 772 switch (record->ucRecordType) { 773 case ATOM_I2C_RECORD_TYPE: 774 i2c_record = 775 (ATOM_I2C_RECORD *) 776 record; 777 i2c_config = 778 (ATOM_I2C_ID_CONFIG_ACCESS *) 779 &i2c_record->sucI2cId; 780 ddc_bus = radeon_lookup_i2c_gpio(rdev, 781 i2c_config-> 782 ucAccess); 783 break; 784 case ATOM_HPD_INT_RECORD_TYPE: 785 hpd_record = 786 (ATOM_HPD_INT_RECORD *) 787 record; 788 gpio = radeon_atombios_lookup_gpio(rdev, 789 hpd_record->ucHPDIntGPIOID); 790 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio); 791 hpd.plugged_state = hpd_record->ucPlugged_PinState; 792 break; 793 } 794 record = 795 (ATOM_COMMON_RECORD_HEADER 796 *) ((char *)record 797 + 798 record-> 799 ucRecordSize); 800 } 801 break; 802 } 803 } 804 } 805 806 /* needed for aux chan transactions */ 807 ddc_bus.hpd = hpd.hpd; 808 809 conn_id = le16_to_cpu(path->usConnObjectId); 810 811 if (!radeon_atom_apply_quirks 812 (dev, le16_to_cpu(path->usDeviceTag), &connector_type, 813 &ddc_bus, &conn_id, &hpd)) 814 continue; 815 816 radeon_add_atom_connector(dev, 817 conn_id, 818 le16_to_cpu(path-> 819 usDeviceTag), 820 connector_type, &ddc_bus, 821 igp_lane_info, 822 connector_object_id, 823 &hpd, 824 &router); 825 826 } 827 } 828 829 radeon_link_encoder_connector(dev); 830 return true; 831 } 832 833 static uint16_t atombios_get_connector_object_id(struct drm_device *dev, 834 int connector_type, 835 uint16_t devices) 836 { 837 struct radeon_device *rdev = dev->dev_private; 838 839 if (rdev->flags & RADEON_IS_IGP) { 840 return supported_devices_connector_object_id_convert 841 [connector_type]; 842 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) || 843 (connector_type == DRM_MODE_CONNECTOR_DVID)) && 844 (devices & ATOM_DEVICE_DFP2_SUPPORT)) { 845 struct radeon_mode_info *mode_info = &rdev->mode_info; 846 struct atom_context *ctx = mode_info->atom_context; 847 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info); 848 uint16_t size, data_offset; 849 uint8_t frev, crev; 850 ATOM_XTMDS_INFO *xtmds; 851 852 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) { 853 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset); 854 855 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) { 856 if (connector_type == DRM_MODE_CONNECTOR_DVII) 857 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 858 else 859 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 860 } else { 861 if (connector_type == DRM_MODE_CONNECTOR_DVII) 862 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 863 else 864 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 865 } 866 } else 867 return supported_devices_connector_object_id_convert 868 [connector_type]; 869 } else { 870 return supported_devices_connector_object_id_convert 871 [connector_type]; 872 } 873 } 874 875 struct bios_connector { 876 bool valid; 877 uint16_t line_mux; 878 uint16_t devices; 879 int connector_type; 880 struct radeon_i2c_bus_rec ddc_bus; 881 struct radeon_hpd hpd; 882 }; 883 884 bool radeon_get_atom_connector_info_from_supported_devices_table(struct 885 drm_device 886 *dev) 887 { 888 struct radeon_device *rdev = dev->dev_private; 889 struct radeon_mode_info *mode_info = &rdev->mode_info; 890 struct atom_context *ctx = mode_info->atom_context; 891 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); 892 uint16_t size, data_offset; 893 uint8_t frev, crev; 894 uint16_t device_support; 895 uint8_t dac; 896 union atom_supported_devices *supported_devices; 897 int i, j, max_device; 898 struct bios_connector *bios_connectors; 899 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE; 900 struct radeon_router router; 901 902 router.ddc_valid = false; 903 router.cd_valid = false; 904 905 bios_connectors = kzalloc(bc_size, GFP_KERNEL); 906 if (!bios_connectors) 907 return false; 908 909 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, 910 &data_offset)) { 911 kfree(bios_connectors); 912 return false; 913 } 914 915 supported_devices = 916 (union atom_supported_devices *)(ctx->bios + data_offset); 917 918 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); 919 920 if (frev > 1) 921 max_device = ATOM_MAX_SUPPORTED_DEVICE; 922 else 923 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO; 924 925 for (i = 0; i < max_device; i++) { 926 ATOM_CONNECTOR_INFO_I2C ci; 927 928 if (frev > 1) 929 ci = supported_devices->info_2d1.asConnInfo[i]; 930 else 931 ci = supported_devices->info.asConnInfo[i]; 932 933 bios_connectors[i].valid = false; 934 935 if (!(device_support & (1 << i))) { 936 continue; 937 } 938 939 if (i == ATOM_DEVICE_CV_INDEX) { 940 DRM_DEBUG_KMS("Skipping Component Video\n"); 941 continue; 942 } 943 944 bios_connectors[i].connector_type = 945 supported_devices_connector_convert[ci.sucConnectorInfo. 946 sbfAccess. 947 bfConnectorType]; 948 949 if (bios_connectors[i].connector_type == 950 DRM_MODE_CONNECTOR_Unknown) 951 continue; 952 953 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; 954 955 bios_connectors[i].line_mux = 956 ci.sucI2cId.ucAccess; 957 958 /* give tv unique connector ids */ 959 if (i == ATOM_DEVICE_TV1_INDEX) { 960 bios_connectors[i].ddc_bus.valid = false; 961 bios_connectors[i].line_mux = 50; 962 } else if (i == ATOM_DEVICE_TV2_INDEX) { 963 bios_connectors[i].ddc_bus.valid = false; 964 bios_connectors[i].line_mux = 51; 965 } else if (i == ATOM_DEVICE_CV_INDEX) { 966 bios_connectors[i].ddc_bus.valid = false; 967 bios_connectors[i].line_mux = 52; 968 } else 969 bios_connectors[i].ddc_bus = 970 radeon_lookup_i2c_gpio(rdev, 971 bios_connectors[i].line_mux); 972 973 if ((crev > 1) && (frev > 1)) { 974 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap; 975 switch (isb) { 976 case 0x4: 977 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 978 break; 979 case 0xa: 980 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 981 break; 982 default: 983 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 984 break; 985 } 986 } else { 987 if (i == ATOM_DEVICE_DFP1_INDEX) 988 bios_connectors[i].hpd.hpd = RADEON_HPD_1; 989 else if (i == ATOM_DEVICE_DFP2_INDEX) 990 bios_connectors[i].hpd.hpd = RADEON_HPD_2; 991 else 992 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE; 993 } 994 995 /* Always set the connector type to VGA for CRT1/CRT2. if they are 996 * shared with a DVI port, we'll pick up the DVI connector when we 997 * merge the outputs. Some bioses incorrectly list VGA ports as DVI. 998 */ 999 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) 1000 bios_connectors[i].connector_type = 1001 DRM_MODE_CONNECTOR_VGA; 1002 1003 if (!radeon_atom_apply_quirks 1004 (dev, (1 << i), &bios_connectors[i].connector_type, 1005 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux, 1006 &bios_connectors[i].hpd)) 1007 continue; 1008 1009 bios_connectors[i].valid = true; 1010 bios_connectors[i].devices = (1 << i); 1011 1012 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) 1013 radeon_add_atom_encoder(dev, 1014 radeon_get_encoder_enum(dev, 1015 (1 << i), 1016 dac), 1017 (1 << i), 1018 0); 1019 else 1020 radeon_add_legacy_encoder(dev, 1021 radeon_get_encoder_enum(dev, 1022 (1 << i), 1023 dac), 1024 (1 << i)); 1025 } 1026 1027 /* combine shared connectors */ 1028 for (i = 0; i < max_device; i++) { 1029 if (bios_connectors[i].valid) { 1030 for (j = 0; j < max_device; j++) { 1031 if (bios_connectors[j].valid && (i != j)) { 1032 if (bios_connectors[i].line_mux == 1033 bios_connectors[j].line_mux) { 1034 /* make sure not to combine LVDS */ 1035 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1036 bios_connectors[i].line_mux = 53; 1037 bios_connectors[i].ddc_bus.valid = false; 1038 continue; 1039 } 1040 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1041 bios_connectors[j].line_mux = 53; 1042 bios_connectors[j].ddc_bus.valid = false; 1043 continue; 1044 } 1045 /* combine analog and digital for DVI-I */ 1046 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1047 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) || 1048 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) && 1049 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) { 1050 bios_connectors[i].devices |= 1051 bios_connectors[j].devices; 1052 bios_connectors[i].connector_type = 1053 DRM_MODE_CONNECTOR_DVII; 1054 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) 1055 bios_connectors[i].hpd = 1056 bios_connectors[j].hpd; 1057 bios_connectors[j].valid = false; 1058 } 1059 } 1060 } 1061 } 1062 } 1063 } 1064 1065 /* add the connectors */ 1066 for (i = 0; i < max_device; i++) { 1067 if (bios_connectors[i].valid) { 1068 uint16_t connector_object_id = 1069 atombios_get_connector_object_id(dev, 1070 bios_connectors[i].connector_type, 1071 bios_connectors[i].devices); 1072 radeon_add_atom_connector(dev, 1073 bios_connectors[i].line_mux, 1074 bios_connectors[i].devices, 1075 bios_connectors[i]. 1076 connector_type, 1077 &bios_connectors[i].ddc_bus, 1078 0, 1079 connector_object_id, 1080 &bios_connectors[i].hpd, 1081 &router); 1082 } 1083 } 1084 1085 radeon_link_encoder_connector(dev); 1086 1087 kfree(bios_connectors); 1088 return true; 1089 } 1090 1091 union firmware_info { 1092 ATOM_FIRMWARE_INFO info; 1093 ATOM_FIRMWARE_INFO_V1_2 info_12; 1094 ATOM_FIRMWARE_INFO_V1_3 info_13; 1095 ATOM_FIRMWARE_INFO_V1_4 info_14; 1096 ATOM_FIRMWARE_INFO_V2_1 info_21; 1097 ATOM_FIRMWARE_INFO_V2_2 info_22; 1098 }; 1099 1100 union igp_info { 1101 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 1102 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 1103 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 1104 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 1105 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 1106 }; 1107 1108 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev) 1109 { 1110 struct radeon_mode_info *mode_info = &rdev->mode_info; 1111 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1112 union igp_info *igp_info; 1113 u8 frev, crev; 1114 u16 data_offset; 1115 1116 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1117 &frev, &crev, &data_offset)) { 1118 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1119 data_offset); 1120 rdev->clock.vco_freq = 1121 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq); 1122 } 1123 } 1124 1125 bool radeon_atom_get_clock_info(struct drm_device *dev) 1126 { 1127 struct radeon_device *rdev = dev->dev_private; 1128 struct radeon_mode_info *mode_info = &rdev->mode_info; 1129 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1130 union firmware_info *firmware_info; 1131 uint8_t frev, crev; 1132 struct radeon_pll *p1pll = &rdev->clock.p1pll; 1133 struct radeon_pll *p2pll = &rdev->clock.p2pll; 1134 struct radeon_pll *dcpll = &rdev->clock.dcpll; 1135 struct radeon_pll *spll = &rdev->clock.spll; 1136 struct radeon_pll *mpll = &rdev->clock.mpll; 1137 uint16_t data_offset; 1138 1139 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1140 &frev, &crev, &data_offset)) { 1141 firmware_info = 1142 (union firmware_info *)(mode_info->atom_context->bios + 1143 data_offset); 1144 /* pixel clocks */ 1145 p1pll->reference_freq = 1146 le16_to_cpu(firmware_info->info.usReferenceClock); 1147 p1pll->reference_div = 0; 1148 1149 if ((frev < 2) && (crev < 2)) 1150 p1pll->pll_out_min = 1151 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 1152 else 1153 p1pll->pll_out_min = 1154 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 1155 p1pll->pll_out_max = 1156 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 1157 1158 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) { 1159 p1pll->lcd_pll_out_min = 1160 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 1161 if (p1pll->lcd_pll_out_min == 0) 1162 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1163 p1pll->lcd_pll_out_max = 1164 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 1165 if (p1pll->lcd_pll_out_max == 0) 1166 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1167 } else { 1168 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 1169 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 1170 } 1171 1172 if (p1pll->pll_out_min == 0) { 1173 if (ASIC_IS_AVIVO(rdev)) 1174 p1pll->pll_out_min = 64800; 1175 else 1176 p1pll->pll_out_min = 20000; 1177 } 1178 1179 p1pll->pll_in_min = 1180 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 1181 p1pll->pll_in_max = 1182 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 1183 1184 *p2pll = *p1pll; 1185 1186 /* system clock */ 1187 if (ASIC_IS_DCE4(rdev)) 1188 spll->reference_freq = 1189 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 1190 else 1191 spll->reference_freq = 1192 le16_to_cpu(firmware_info->info.usReferenceClock); 1193 spll->reference_div = 0; 1194 1195 spll->pll_out_min = 1196 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 1197 spll->pll_out_max = 1198 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 1199 1200 /* ??? */ 1201 if (spll->pll_out_min == 0) { 1202 if (ASIC_IS_AVIVO(rdev)) 1203 spll->pll_out_min = 64800; 1204 else 1205 spll->pll_out_min = 20000; 1206 } 1207 1208 spll->pll_in_min = 1209 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 1210 spll->pll_in_max = 1211 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 1212 1213 /* memory clock */ 1214 if (ASIC_IS_DCE4(rdev)) 1215 mpll->reference_freq = 1216 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 1217 else 1218 mpll->reference_freq = 1219 le16_to_cpu(firmware_info->info.usReferenceClock); 1220 mpll->reference_div = 0; 1221 1222 mpll->pll_out_min = 1223 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 1224 mpll->pll_out_max = 1225 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 1226 1227 /* ??? */ 1228 if (mpll->pll_out_min == 0) { 1229 if (ASIC_IS_AVIVO(rdev)) 1230 mpll->pll_out_min = 64800; 1231 else 1232 mpll->pll_out_min = 20000; 1233 } 1234 1235 mpll->pll_in_min = 1236 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 1237 mpll->pll_in_max = 1238 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 1239 1240 rdev->clock.default_sclk = 1241 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 1242 rdev->clock.default_mclk = 1243 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 1244 1245 if (ASIC_IS_DCE4(rdev)) { 1246 rdev->clock.default_dispclk = 1247 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1248 if (rdev->clock.default_dispclk == 0) { 1249 if (ASIC_IS_DCE6(rdev)) 1250 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1251 else if (ASIC_IS_DCE5(rdev)) 1252 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1253 else 1254 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1255 } 1256 /* set a reasonable default for DP */ 1257 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) { 1258 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 1259 rdev->clock.default_dispclk / 100); 1260 rdev->clock.default_dispclk = 60000; 1261 } 1262 rdev->clock.dp_extclk = 1263 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1264 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1265 } 1266 *dcpll = *p1pll; 1267 1268 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 1269 if (rdev->clock.max_pixel_clock == 0) 1270 rdev->clock.max_pixel_clock = 40000; 1271 1272 /* not technically a clock, but... */ 1273 rdev->mode_info.firmware_flags = 1274 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 1275 1276 if (ASIC_IS_DCE8(rdev)) 1277 rdev->clock.vco_freq = 1278 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq); 1279 else if (ASIC_IS_DCE5(rdev)) 1280 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1281 else if (ASIC_IS_DCE41(rdev)) 1282 radeon_atombios_get_dentist_vco_freq(rdev); 1283 else 1284 rdev->clock.vco_freq = rdev->clock.current_dispclk; 1285 1286 if (rdev->clock.vco_freq == 0) 1287 rdev->clock.vco_freq = 360000; /* 3.6 GHz */ 1288 1289 return true; 1290 } 1291 1292 return false; 1293 } 1294 1295 bool radeon_atombios_sideport_present(struct radeon_device *rdev) 1296 { 1297 struct radeon_mode_info *mode_info = &rdev->mode_info; 1298 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1299 union igp_info *igp_info; 1300 u8 frev, crev; 1301 u16 data_offset; 1302 1303 /* sideport is AMD only */ 1304 if (rdev->family == CHIP_RS600) 1305 return false; 1306 1307 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1308 &frev, &crev, &data_offset)) { 1309 igp_info = (union igp_info *)(mode_info->atom_context->bios + 1310 data_offset); 1311 switch (crev) { 1312 case 1: 1313 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock)) 1314 return true; 1315 break; 1316 case 2: 1317 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock)) 1318 return true; 1319 break; 1320 default: 1321 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1322 break; 1323 } 1324 } 1325 return false; 1326 } 1327 1328 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 1329 struct radeon_encoder_int_tmds *tmds) 1330 { 1331 struct drm_device *dev = encoder->base.dev; 1332 struct radeon_device *rdev = dev->dev_private; 1333 struct radeon_mode_info *mode_info = &rdev->mode_info; 1334 int index = GetIndexIntoMasterTable(DATA, TMDS_Info); 1335 uint16_t data_offset; 1336 struct _ATOM_TMDS_INFO *tmds_info; 1337 uint8_t frev, crev; 1338 uint16_t maxfreq; 1339 int i; 1340 1341 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1342 &frev, &crev, &data_offset)) { 1343 tmds_info = 1344 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + 1345 data_offset); 1346 1347 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); 1348 for (i = 0; i < 4; i++) { 1349 tmds->tmds_pll[i].freq = 1350 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); 1351 tmds->tmds_pll[i].value = 1352 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; 1353 tmds->tmds_pll[i].value |= 1354 (tmds_info->asMiscInfo[i]. 1355 ucPLL_VCO_Gain & 0x3f) << 6; 1356 tmds->tmds_pll[i].value |= 1357 (tmds_info->asMiscInfo[i]. 1358 ucPLL_DutyCycle & 0xf) << 12; 1359 tmds->tmds_pll[i].value |= 1360 (tmds_info->asMiscInfo[i]. 1361 ucPLL_VoltageSwing & 0xf) << 16; 1362 1363 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n", 1364 tmds->tmds_pll[i].freq, 1365 tmds->tmds_pll[i].value); 1366 1367 if (maxfreq == tmds->tmds_pll[i].freq) { 1368 tmds->tmds_pll[i].freq = 0xffffffff; 1369 break; 1370 } 1371 } 1372 return true; 1373 } 1374 return false; 1375 } 1376 1377 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 1378 struct radeon_atom_ss *ss, 1379 int id) 1380 { 1381 struct radeon_mode_info *mode_info = &rdev->mode_info; 1382 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 1383 uint16_t data_offset, size; 1384 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info; 1385 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign; 1386 uint8_t frev, crev; 1387 int i, num_indices; 1388 1389 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1390 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1391 &frev, &crev, &data_offset)) { 1392 ss_info = 1393 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset); 1394 1395 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1396 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 1397 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1398 ((u8 *)&ss_info->asSS_Info[0]); 1399 for (i = 0; i < num_indices; i++) { 1400 if (ss_assign->ucSS_Id == id) { 1401 ss->percentage = 1402 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage); 1403 ss->type = ss_assign->ucSpreadSpectrumType; 1404 ss->step = ss_assign->ucSS_Step; 1405 ss->delay = ss_assign->ucSS_Delay; 1406 ss->range = ss_assign->ucSS_Range; 1407 ss->refdiv = ss_assign->ucRecommendedRef_Div; 1408 return true; 1409 } 1410 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) 1411 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); 1412 } 1413 } 1414 return false; 1415 } 1416 1417 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev, 1418 struct radeon_atom_ss *ss, 1419 int id) 1420 { 1421 struct radeon_mode_info *mode_info = &rdev->mode_info; 1422 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 1423 u16 data_offset, size; 1424 union igp_info *igp_info; 1425 u8 frev, crev; 1426 u16 percentage = 0, rate = 0; 1427 1428 /* get any igp specific overrides */ 1429 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1430 &frev, &crev, &data_offset)) { 1431 igp_info = (union igp_info *) 1432 (mode_info->atom_context->bios + data_offset); 1433 switch (crev) { 1434 case 6: 1435 switch (id) { 1436 case ASIC_INTERNAL_SS_ON_TMDS: 1437 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 1438 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 1439 break; 1440 case ASIC_INTERNAL_SS_ON_HDMI: 1441 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 1442 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 1443 break; 1444 case ASIC_INTERNAL_SS_ON_LVDS: 1445 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 1446 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 1447 break; 1448 } 1449 break; 1450 case 7: 1451 switch (id) { 1452 case ASIC_INTERNAL_SS_ON_TMDS: 1453 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 1454 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 1455 break; 1456 case ASIC_INTERNAL_SS_ON_HDMI: 1457 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 1458 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 1459 break; 1460 case ASIC_INTERNAL_SS_ON_LVDS: 1461 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 1462 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 1463 break; 1464 } 1465 break; 1466 case 8: 1467 switch (id) { 1468 case ASIC_INTERNAL_SS_ON_TMDS: 1469 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 1470 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 1471 break; 1472 case ASIC_INTERNAL_SS_ON_HDMI: 1473 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 1474 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 1475 break; 1476 case ASIC_INTERNAL_SS_ON_LVDS: 1477 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 1478 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 1479 break; 1480 } 1481 break; 1482 default: 1483 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 1484 break; 1485 } 1486 if (percentage) 1487 ss->percentage = percentage; 1488 if (rate) 1489 ss->rate = rate; 1490 } 1491 } 1492 1493 union asic_ss_info { 1494 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 1495 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 1496 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 1497 }; 1498 1499 union asic_ss_assignment { 1500 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 1501 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 1502 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 1503 }; 1504 1505 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 1506 struct radeon_atom_ss *ss, 1507 int id, u32 clock) 1508 { 1509 struct radeon_mode_info *mode_info = &rdev->mode_info; 1510 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 1511 uint16_t data_offset, size; 1512 union asic_ss_info *ss_info; 1513 union asic_ss_assignment *ss_assign; 1514 uint8_t frev, crev; 1515 int i, num_indices; 1516 1517 if (id == ASIC_INTERNAL_MEMORY_SS) { 1518 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 1519 return false; 1520 } 1521 if (id == ASIC_INTERNAL_ENGINE_SS) { 1522 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 1523 return false; 1524 } 1525 1526 memset(ss, 0, sizeof(struct radeon_atom_ss)); 1527 if (atom_parse_data_header(mode_info->atom_context, index, &size, 1528 &frev, &crev, &data_offset)) { 1529 1530 ss_info = 1531 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 1532 1533 switch (frev) { 1534 case 1: 1535 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1536 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 1537 1538 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 1539 for (i = 0; i < num_indices; i++) { 1540 if ((ss_assign->v1.ucClockIndication == id) && 1541 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 1542 ss->percentage = 1543 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 1544 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 1545 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 1546 ss->percentage_divider = 100; 1547 return true; 1548 } 1549 ss_assign = (union asic_ss_assignment *) 1550 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 1551 } 1552 break; 1553 case 2: 1554 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1555 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 1556 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 1557 for (i = 0; i < num_indices; i++) { 1558 if ((ss_assign->v2.ucClockIndication == id) && 1559 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 1560 ss->percentage = 1561 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 1562 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 1563 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 1564 ss->percentage_divider = 100; 1565 if ((crev == 2) && 1566 ((id == ASIC_INTERNAL_ENGINE_SS) || 1567 (id == ASIC_INTERNAL_MEMORY_SS))) 1568 ss->rate /= 100; 1569 return true; 1570 } 1571 ss_assign = (union asic_ss_assignment *) 1572 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 1573 } 1574 break; 1575 case 3: 1576 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 1577 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 1578 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 1579 for (i = 0; i < num_indices; i++) { 1580 if ((ss_assign->v3.ucClockIndication == id) && 1581 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 1582 ss->percentage = 1583 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 1584 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 1585 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 1586 if (ss_assign->v3.ucSpreadSpectrumMode & 1587 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 1588 ss->percentage_divider = 1000; 1589 else 1590 ss->percentage_divider = 100; 1591 if ((id == ASIC_INTERNAL_ENGINE_SS) || 1592 (id == ASIC_INTERNAL_MEMORY_SS)) 1593 ss->rate /= 100; 1594 if (rdev->flags & RADEON_IS_IGP) 1595 radeon_atombios_get_igp_ss_overrides(rdev, ss, id); 1596 return true; 1597 } 1598 ss_assign = (union asic_ss_assignment *) 1599 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 1600 } 1601 break; 1602 default: 1603 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 1604 break; 1605 } 1606 1607 } 1608 return false; 1609 } 1610 1611 union lvds_info { 1612 struct _ATOM_LVDS_INFO info; 1613 struct _ATOM_LVDS_INFO_V12 info_12; 1614 }; 1615 1616 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct 1617 radeon_encoder 1618 *encoder) 1619 { 1620 struct drm_device *dev = encoder->base.dev; 1621 struct radeon_device *rdev = dev->dev_private; 1622 struct radeon_mode_info *mode_info = &rdev->mode_info; 1623 int index = GetIndexIntoMasterTable(DATA, LVDS_Info); 1624 uint16_t data_offset, misc; 1625 union lvds_info *lvds_info; 1626 uint8_t frev, crev; 1627 struct radeon_encoder_atom_dig *lvds = NULL; 1628 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1629 1630 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1631 &frev, &crev, &data_offset)) { 1632 lvds_info = 1633 (union lvds_info *)(mode_info->atom_context->bios + data_offset); 1634 lvds = 1635 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 1636 1637 if (!lvds) 1638 return NULL; 1639 1640 lvds->native_mode.clock = 1641 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 1642 lvds->native_mode.hdisplay = 1643 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 1644 lvds->native_mode.vdisplay = 1645 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 1646 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1647 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 1648 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1649 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 1650 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1651 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 1652 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1653 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 1654 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1655 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 1656 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1657 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 1658 lvds->panel_pwr_delay = 1659 le16_to_cpu(lvds_info->info.usOffDelayInMs); 1660 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; 1661 1662 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess); 1663 if (misc & ATOM_VSYNC_POLARITY) 1664 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; 1665 if (misc & ATOM_HSYNC_POLARITY) 1666 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; 1667 if (misc & ATOM_COMPOSITESYNC) 1668 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; 1669 if (misc & ATOM_INTERLACE) 1670 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; 1671 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1672 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; 1673 1674 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); 1675 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); 1676 1677 /* set crtc values */ 1678 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1679 1680 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; 1681 1682 encoder->native_mode = lvds->native_mode; 1683 1684 if (encoder_enum == 2) 1685 lvds->linkb = true; 1686 else 1687 lvds->linkb = false; 1688 1689 /* parse the lcd record table */ 1690 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) { 1691 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record; 1692 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record; 1693 bool bad_record = false; 1694 u8 *record; 1695 1696 if ((frev == 1) && (crev < 2)) 1697 /* absolute */ 1698 record = (u8 *)(mode_info->atom_context->bios + 1699 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1700 else 1701 /* relative */ 1702 record = (u8 *)(mode_info->atom_context->bios + 1703 data_offset + 1704 le16_to_cpu(lvds_info->info.usModePatchTableOffset)); 1705 while (*record != ATOM_RECORD_END_TYPE) { 1706 switch (*record) { 1707 case LCD_MODE_PATCH_RECORD_MODE_TYPE: 1708 record += sizeof(ATOM_PATCH_RECORD_MODE); 1709 break; 1710 case LCD_RTS_RECORD_TYPE: 1711 record += sizeof(ATOM_LCD_RTS_RECORD); 1712 break; 1713 case LCD_CAP_RECORD_TYPE: 1714 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP); 1715 break; 1716 case LCD_FAKE_EDID_PATCH_RECORD_TYPE: 1717 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record; 1718 if (fake_edid_record->ucFakeEDIDLength) { 1719 struct edid *edid; 1720 int edid_size = 1721 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength); 1722 edid = kmalloc(edid_size, GFP_KERNEL); 1723 if (edid) { 1724 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1725 fake_edid_record->ucFakeEDIDLength); 1726 1727 if (drm_edid_is_valid(edid)) { 1728 rdev->mode_info.bios_hardcoded_edid = edid; 1729 rdev->mode_info.bios_hardcoded_edid_size = edid_size; 1730 } else 1731 kfree(edid); 1732 } 1733 } 1734 record += fake_edid_record->ucFakeEDIDLength ? 1735 struct_size(fake_edid_record, 1736 ucFakeEDIDString, 1737 fake_edid_record->ucFakeEDIDLength) : 1738 /* empty fake edid record must be 3 bytes long */ 1739 sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1; 1740 break; 1741 case LCD_PANEL_RESOLUTION_RECORD_TYPE: 1742 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record; 1743 lvds->native_mode.width_mm = panel_res_record->usHSize; 1744 lvds->native_mode.height_mm = panel_res_record->usVSize; 1745 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD); 1746 break; 1747 default: 1748 DRM_ERROR("Bad LCD record %d\n", *record); 1749 bad_record = true; 1750 break; 1751 } 1752 if (bad_record) 1753 break; 1754 } 1755 } 1756 } 1757 return lvds; 1758 } 1759 1760 struct radeon_encoder_primary_dac * 1761 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) 1762 { 1763 struct drm_device *dev = encoder->base.dev; 1764 struct radeon_device *rdev = dev->dev_private; 1765 struct radeon_mode_info *mode_info = &rdev->mode_info; 1766 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1767 uint16_t data_offset; 1768 struct _COMPASSIONATE_DATA *dac_info; 1769 uint8_t frev, crev; 1770 uint8_t bg, dac; 1771 struct radeon_encoder_primary_dac *p_dac = NULL; 1772 1773 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1774 &frev, &crev, &data_offset)) { 1775 dac_info = (struct _COMPASSIONATE_DATA *) 1776 (mode_info->atom_context->bios + data_offset); 1777 1778 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); 1779 1780 if (!p_dac) 1781 return NULL; 1782 1783 bg = dac_info->ucDAC1_BG_Adjustment; 1784 dac = dac_info->ucDAC1_DAC_Adjustment; 1785 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 1786 1787 } 1788 return p_dac; 1789 } 1790 1791 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 1792 struct drm_display_mode *mode) 1793 { 1794 struct radeon_mode_info *mode_info = &rdev->mode_info; 1795 ATOM_ANALOG_TV_INFO *tv_info; 1796 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2; 1797 ATOM_DTD_FORMAT *dtd_timings; 1798 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1799 u8 frev, crev; 1800 u16 data_offset, misc; 1801 1802 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL, 1803 &frev, &crev, &data_offset)) 1804 return false; 1805 1806 switch (crev) { 1807 case 1: 1808 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset); 1809 if (index >= MAX_SUPPORTED_TV_TIMING) 1810 return false; 1811 1812 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1813 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1814 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1815 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) + 1816 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1817 1818 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1819 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1820 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1821 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) + 1822 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1823 1824 mode->flags = 0; 1825 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess); 1826 if (misc & ATOM_VSYNC_POLARITY) 1827 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1828 if (misc & ATOM_HSYNC_POLARITY) 1829 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1830 if (misc & ATOM_COMPOSITESYNC) 1831 mode->flags |= DRM_MODE_FLAG_CSYNC; 1832 if (misc & ATOM_INTERLACE) 1833 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1834 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1835 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1836 1837 mode->crtc_clock = mode->clock = 1838 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1839 1840 if (index == 1) { 1841 /* PAL timings appear to have wrong values for totals */ 1842 mode->crtc_htotal -= 1; 1843 mode->crtc_vtotal -= 1; 1844 } 1845 break; 1846 case 2: 1847 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset); 1848 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2) 1849 return false; 1850 1851 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1852 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) + 1853 le16_to_cpu(dtd_timings->usHBlanking_Time); 1854 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive); 1855 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) + 1856 le16_to_cpu(dtd_timings->usHSyncOffset); 1857 mode->crtc_hsync_end = mode->crtc_hsync_start + 1858 le16_to_cpu(dtd_timings->usHSyncWidth); 1859 1860 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) + 1861 le16_to_cpu(dtd_timings->usVBlanking_Time); 1862 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive); 1863 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) + 1864 le16_to_cpu(dtd_timings->usVSyncOffset); 1865 mode->crtc_vsync_end = mode->crtc_vsync_start + 1866 le16_to_cpu(dtd_timings->usVSyncWidth); 1867 1868 mode->flags = 0; 1869 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1870 if (misc & ATOM_VSYNC_POLARITY) 1871 mode->flags |= DRM_MODE_FLAG_NVSYNC; 1872 if (misc & ATOM_HSYNC_POLARITY) 1873 mode->flags |= DRM_MODE_FLAG_NHSYNC; 1874 if (misc & ATOM_COMPOSITESYNC) 1875 mode->flags |= DRM_MODE_FLAG_CSYNC; 1876 if (misc & ATOM_INTERLACE) 1877 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1878 if (misc & ATOM_DOUBLE_CLOCK_MODE) 1879 mode->flags |= DRM_MODE_FLAG_DBLSCAN; 1880 1881 mode->crtc_clock = mode->clock = 1882 le16_to_cpu(dtd_timings->usPixClk) * 10; 1883 break; 1884 } 1885 return true; 1886 } 1887 1888 enum radeon_tv_std 1889 radeon_atombios_get_tv_info(struct radeon_device *rdev) 1890 { 1891 struct radeon_mode_info *mode_info = &rdev->mode_info; 1892 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 1893 uint16_t data_offset; 1894 uint8_t frev, crev; 1895 struct _ATOM_ANALOG_TV_INFO *tv_info; 1896 enum radeon_tv_std tv_std = TV_STD_NTSC; 1897 1898 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1899 &frev, &crev, &data_offset)) { 1900 1901 tv_info = (struct _ATOM_ANALOG_TV_INFO *) 1902 (mode_info->atom_context->bios + data_offset); 1903 1904 switch (tv_info->ucTV_BootUpDefaultStandard) { 1905 case ATOM_TV_NTSC: 1906 tv_std = TV_STD_NTSC; 1907 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 1908 break; 1909 case ATOM_TV_NTSCJ: 1910 tv_std = TV_STD_NTSC_J; 1911 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 1912 break; 1913 case ATOM_TV_PAL: 1914 tv_std = TV_STD_PAL; 1915 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 1916 break; 1917 case ATOM_TV_PALM: 1918 tv_std = TV_STD_PAL_M; 1919 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 1920 break; 1921 case ATOM_TV_PALN: 1922 tv_std = TV_STD_PAL_N; 1923 DRM_DEBUG_KMS("Default TV standard: PAL-N\n"); 1924 break; 1925 case ATOM_TV_PALCN: 1926 tv_std = TV_STD_PAL_CN; 1927 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n"); 1928 break; 1929 case ATOM_TV_PAL60: 1930 tv_std = TV_STD_PAL_60; 1931 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 1932 break; 1933 case ATOM_TV_SECAM: 1934 tv_std = TV_STD_SECAM; 1935 DRM_DEBUG_KMS("Default TV standard: SECAM\n"); 1936 break; 1937 default: 1938 tv_std = TV_STD_NTSC; 1939 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n"); 1940 break; 1941 } 1942 } 1943 return tv_std; 1944 } 1945 1946 struct radeon_encoder_tv_dac * 1947 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) 1948 { 1949 struct drm_device *dev = encoder->base.dev; 1950 struct radeon_device *rdev = dev->dev_private; 1951 struct radeon_mode_info *mode_info = &rdev->mode_info; 1952 int index = GetIndexIntoMasterTable(DATA, CompassionateData); 1953 uint16_t data_offset; 1954 struct _COMPASSIONATE_DATA *dac_info; 1955 uint8_t frev, crev; 1956 uint8_t bg, dac; 1957 struct radeon_encoder_tv_dac *tv_dac = NULL; 1958 1959 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 1960 &frev, &crev, &data_offset)) { 1961 1962 dac_info = (struct _COMPASSIONATE_DATA *) 1963 (mode_info->atom_context->bios + data_offset); 1964 1965 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1966 1967 if (!tv_dac) 1968 return NULL; 1969 1970 bg = dac_info->ucDAC2_CRT2_BG_Adjustment; 1971 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; 1972 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1973 1974 bg = dac_info->ucDAC2_PAL_BG_Adjustment; 1975 dac = dac_info->ucDAC2_PAL_DAC_Adjustment; 1976 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1977 1978 bg = dac_info->ucDAC2_NTSC_BG_Adjustment; 1979 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; 1980 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1981 1982 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev); 1983 } 1984 return tv_dac; 1985 } 1986 1987 static const char *thermal_controller_names[] = { 1988 "NONE", 1989 "lm63", 1990 "adm1032", 1991 "adm1030", 1992 "max6649", 1993 "lm63", /* lm64 */ 1994 "f75375", 1995 "asc7xxx", 1996 }; 1997 1998 static const char *pp_lib_thermal_controller_names[] = { 1999 "NONE", 2000 "lm63", 2001 "adm1032", 2002 "adm1030", 2003 "max6649", 2004 "lm63", /* lm64 */ 2005 "f75375", 2006 "RV6xx", 2007 "RV770", 2008 "adt7473", 2009 "NONE", 2010 "External GPIO", 2011 "Evergreen", 2012 "emc2103", 2013 "Sumo", 2014 "Northern Islands", 2015 "Southern Islands", 2016 "lm96163", 2017 "Sea Islands", 2018 }; 2019 2020 union power_info { 2021 struct _ATOM_POWERPLAY_INFO info; 2022 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2023 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2024 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2025 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2026 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2027 }; 2028 2029 union pplib_clock_info { 2030 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2031 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2032 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2033 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2034 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 2035 struct _ATOM_PPLIB_CI_CLOCK_INFO ci; 2036 }; 2037 2038 union pplib_power_state { 2039 struct _ATOM_PPLIB_STATE v1; 2040 struct _ATOM_PPLIB_STATE_V2 v2; 2041 }; 2042 2043 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev, 2044 int state_index, 2045 u32 misc, u32 misc2) 2046 { 2047 rdev->pm.power_state[state_index].misc = misc; 2048 rdev->pm.power_state[state_index].misc2 = misc2; 2049 /* order matters! */ 2050 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE) 2051 rdev->pm.power_state[state_index].type = 2052 POWER_STATE_TYPE_POWERSAVE; 2053 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE) 2054 rdev->pm.power_state[state_index].type = 2055 POWER_STATE_TYPE_BATTERY; 2056 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE) 2057 rdev->pm.power_state[state_index].type = 2058 POWER_STATE_TYPE_BATTERY; 2059 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN) 2060 rdev->pm.power_state[state_index].type = 2061 POWER_STATE_TYPE_BALANCED; 2062 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) { 2063 rdev->pm.power_state[state_index].type = 2064 POWER_STATE_TYPE_PERFORMANCE; 2065 rdev->pm.power_state[state_index].flags &= 2066 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2067 } 2068 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE) 2069 rdev->pm.power_state[state_index].type = 2070 POWER_STATE_TYPE_BALANCED; 2071 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) { 2072 rdev->pm.power_state[state_index].type = 2073 POWER_STATE_TYPE_DEFAULT; 2074 rdev->pm.default_power_state_index = state_index; 2075 rdev->pm.power_state[state_index].default_clock_mode = 2076 &rdev->pm.power_state[state_index].clock_info[0]; 2077 } else if (state_index == 0) { 2078 rdev->pm.power_state[state_index].clock_info[0].flags |= 2079 RADEON_PM_MODE_NO_DISPLAY; 2080 } 2081 } 2082 2083 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev) 2084 { 2085 struct radeon_mode_info *mode_info = &rdev->mode_info; 2086 u32 misc, misc2 = 0; 2087 int num_modes = 0, i; 2088 int state_index = 0; 2089 struct radeon_i2c_bus_rec i2c_bus; 2090 union power_info *power_info; 2091 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2092 u16 data_offset; 2093 u8 frev, crev; 2094 2095 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2096 &frev, &crev, &data_offset)) 2097 return state_index; 2098 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2099 2100 /* add the i2c bus for thermal/fan chip */ 2101 if ((power_info->info.ucOverdriveThermalController > 0) && 2102 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) { 2103 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2104 thermal_controller_names[power_info->info.ucOverdriveThermalController], 2105 power_info->info.ucOverdriveControllerAddress >> 1); 2106 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine); 2107 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2108 if (rdev->pm.i2c_bus) { 2109 struct i2c_board_info info = { }; 2110 const char *name = thermal_controller_names[power_info->info. 2111 ucOverdriveThermalController]; 2112 info.addr = power_info->info.ucOverdriveControllerAddress >> 1; 2113 strscpy(info.type, name, sizeof(info.type)); 2114 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2115 } 2116 } 2117 num_modes = power_info->info.ucNumOfPowerModeEntries; 2118 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK) 2119 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK; 2120 if (num_modes == 0) 2121 return state_index; 2122 rdev->pm.power_state = kcalloc(num_modes, 2123 sizeof(struct radeon_power_state), 2124 GFP_KERNEL); 2125 if (!rdev->pm.power_state) 2126 return state_index; 2127 /* last mode is usually default, array is low to high */ 2128 for (i = 0; i < num_modes; i++) { 2129 /* avoid memory leaks from invalid modes or unknown frev. */ 2130 if (!rdev->pm.power_state[state_index].clock_info) { 2131 rdev->pm.power_state[state_index].clock_info = 2132 kzalloc(sizeof(struct radeon_pm_clock_info), 2133 GFP_KERNEL); 2134 } 2135 if (!rdev->pm.power_state[state_index].clock_info) 2136 goto out; 2137 rdev->pm.power_state[state_index].num_clock_modes = 1; 2138 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2139 switch (frev) { 2140 case 1: 2141 rdev->pm.power_state[state_index].clock_info[0].mclk = 2142 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2143 rdev->pm.power_state[state_index].clock_info[0].sclk = 2144 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock); 2145 /* skip invalid modes */ 2146 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2147 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2148 continue; 2149 rdev->pm.power_state[state_index].pcie_lanes = 2150 power_info->info.asPowerPlayInfo[i].ucNumPciELanes; 2151 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo); 2152 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2153 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2154 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2155 VOLTAGE_GPIO; 2156 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2157 radeon_atombios_lookup_gpio(rdev, 2158 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex); 2159 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2160 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2161 true; 2162 else 2163 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2164 false; 2165 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2166 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2167 VOLTAGE_VDDC; 2168 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2169 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex; 2170 } 2171 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2172 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0); 2173 state_index++; 2174 break; 2175 case 2: 2176 rdev->pm.power_state[state_index].clock_info[0].mclk = 2177 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2178 rdev->pm.power_state[state_index].clock_info[0].sclk = 2179 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock); 2180 /* skip invalid modes */ 2181 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2182 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2183 continue; 2184 rdev->pm.power_state[state_index].pcie_lanes = 2185 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes; 2186 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo); 2187 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2); 2188 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2189 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2190 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2191 VOLTAGE_GPIO; 2192 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2193 radeon_atombios_lookup_gpio(rdev, 2194 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex); 2195 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2196 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2197 true; 2198 else 2199 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2200 false; 2201 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2202 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2203 VOLTAGE_VDDC; 2204 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2205 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex; 2206 } 2207 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2208 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2209 state_index++; 2210 break; 2211 case 3: 2212 rdev->pm.power_state[state_index].clock_info[0].mclk = 2213 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2214 rdev->pm.power_state[state_index].clock_info[0].sclk = 2215 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock); 2216 /* skip invalid modes */ 2217 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2218 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2219 continue; 2220 rdev->pm.power_state[state_index].pcie_lanes = 2221 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes; 2222 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo); 2223 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2); 2224 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) || 2225 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) { 2226 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2227 VOLTAGE_GPIO; 2228 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio = 2229 radeon_atombios_lookup_gpio(rdev, 2230 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex); 2231 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH) 2232 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2233 true; 2234 else 2235 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2236 false; 2237 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) { 2238 rdev->pm.power_state[state_index].clock_info[0].voltage.type = 2239 VOLTAGE_VDDC; 2240 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id = 2241 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex; 2242 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) { 2243 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled = 2244 true; 2245 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id = 2246 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex; 2247 } 2248 } 2249 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2250 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2); 2251 state_index++; 2252 break; 2253 } 2254 } 2255 out: 2256 /* free any unused clock_info allocation. */ 2257 if (state_index && state_index < num_modes) { 2258 kfree(rdev->pm.power_state[state_index].clock_info); 2259 rdev->pm.power_state[state_index].clock_info = NULL; 2260 } 2261 2262 /* last mode is usually default */ 2263 if (state_index && rdev->pm.default_power_state_index == -1) { 2264 rdev->pm.power_state[state_index - 1].type = 2265 POWER_STATE_TYPE_DEFAULT; 2266 rdev->pm.default_power_state_index = state_index - 1; 2267 rdev->pm.power_state[state_index - 1].default_clock_mode = 2268 &rdev->pm.power_state[state_index - 1].clock_info[0]; 2269 rdev->pm.power_state[state_index - 1].flags &= 2270 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2271 rdev->pm.power_state[state_index - 1].misc = 0; 2272 rdev->pm.power_state[state_index - 1].misc2 = 0; 2273 } 2274 return state_index; 2275 } 2276 2277 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev, 2278 ATOM_PPLIB_THERMALCONTROLLER *controller) 2279 { 2280 struct radeon_i2c_bus_rec i2c_bus; 2281 2282 /* add the i2c bus for thermal/fan chip */ 2283 if (controller->ucType > 0) { 2284 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) 2285 rdev->pm.no_fan = true; 2286 rdev->pm.fan_pulses_per_revolution = 2287 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 2288 if (rdev->pm.fan_pulses_per_revolution) { 2289 rdev->pm.fan_min_rpm = controller->ucFanMinRPM; 2290 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM; 2291 } 2292 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) { 2293 DRM_INFO("Internal thermal controller %s fan control\n", 2294 (controller->ucFanParameters & 2295 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2296 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX; 2297 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) { 2298 DRM_INFO("Internal thermal controller %s fan control\n", 2299 (controller->ucFanParameters & 2300 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2301 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770; 2302 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) { 2303 DRM_INFO("Internal thermal controller %s fan control\n", 2304 (controller->ucFanParameters & 2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2306 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN; 2307 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) { 2308 DRM_INFO("Internal thermal controller %s fan control\n", 2309 (controller->ucFanParameters & 2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2311 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO; 2312 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) { 2313 DRM_INFO("Internal thermal controller %s fan control\n", 2314 (controller->ucFanParameters & 2315 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2316 rdev->pm.int_thermal_type = THERMAL_TYPE_NI; 2317 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) { 2318 DRM_INFO("Internal thermal controller %s fan control\n", 2319 (controller->ucFanParameters & 2320 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2321 rdev->pm.int_thermal_type = THERMAL_TYPE_SI; 2322 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) { 2323 DRM_INFO("Internal thermal controller %s fan control\n", 2324 (controller->ucFanParameters & 2325 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2326 rdev->pm.int_thermal_type = THERMAL_TYPE_CI; 2327 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) { 2328 DRM_INFO("Internal thermal controller %s fan control\n", 2329 (controller->ucFanParameters & 2330 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2331 rdev->pm.int_thermal_type = THERMAL_TYPE_KV; 2332 } else if (controller->ucType == 2333 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) { 2334 DRM_INFO("External GPIO thermal controller %s fan control\n", 2335 (controller->ucFanParameters & 2336 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2337 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO; 2338 } else if (controller->ucType == 2339 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) { 2340 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n", 2341 (controller->ucFanParameters & 2342 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2343 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL; 2344 } else if (controller->ucType == 2345 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) { 2346 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n", 2347 (controller->ucFanParameters & 2348 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2349 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL; 2350 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) { 2351 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n", 2352 pp_lib_thermal_controller_names[controller->ucType], 2353 controller->ucI2cAddress >> 1, 2354 (controller->ucFanParameters & 2355 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2356 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL; 2357 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine); 2358 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2359 if (rdev->pm.i2c_bus) { 2360 struct i2c_board_info info = { }; 2361 const char *name = pp_lib_thermal_controller_names[controller->ucType]; 2362 info.addr = controller->ucI2cAddress >> 1; 2363 strscpy(info.type, name, sizeof(info.type)); 2364 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2365 } 2366 } else { 2367 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n", 2368 controller->ucType, 2369 controller->ucI2cAddress >> 1, 2370 (controller->ucFanParameters & 2371 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); 2372 } 2373 } 2374 } 2375 2376 void radeon_atombios_get_default_voltages(struct radeon_device *rdev, 2377 u16 *vddc, u16 *vddci, u16 *mvdd) 2378 { 2379 struct radeon_mode_info *mode_info = &rdev->mode_info; 2380 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 2381 u8 frev, crev; 2382 u16 data_offset; 2383 union firmware_info *firmware_info; 2384 2385 *vddc = 0; 2386 *vddci = 0; 2387 *mvdd = 0; 2388 2389 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2390 &frev, &crev, &data_offset)) { 2391 firmware_info = 2392 (union firmware_info *)(mode_info->atom_context->bios + 2393 data_offset); 2394 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 2395 if ((frev == 2) && (crev >= 2)) { 2396 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 2397 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 2398 } 2399 } 2400 } 2401 2402 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev, 2403 int state_index, int mode_index, 2404 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info) 2405 { 2406 int j; 2407 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2408 u32 misc2 = le16_to_cpu(non_clock_info->usClassification); 2409 u16 vddc, vddci, mvdd; 2410 2411 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 2412 2413 rdev->pm.power_state[state_index].misc = misc; 2414 rdev->pm.power_state[state_index].misc2 = misc2; 2415 rdev->pm.power_state[state_index].pcie_lanes = 2416 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> 2417 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 2418 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) { 2419 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY: 2420 rdev->pm.power_state[state_index].type = 2421 POWER_STATE_TYPE_BATTERY; 2422 break; 2423 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED: 2424 rdev->pm.power_state[state_index].type = 2425 POWER_STATE_TYPE_BALANCED; 2426 break; 2427 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE: 2428 rdev->pm.power_state[state_index].type = 2429 POWER_STATE_TYPE_PERFORMANCE; 2430 break; 2431 case ATOM_PPLIB_CLASSIFICATION_UI_NONE: 2432 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 2433 rdev->pm.power_state[state_index].type = 2434 POWER_STATE_TYPE_PERFORMANCE; 2435 break; 2436 } 2437 rdev->pm.power_state[state_index].flags = 0; 2438 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) 2439 rdev->pm.power_state[state_index].flags |= 2440 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2441 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2442 rdev->pm.power_state[state_index].type = 2443 POWER_STATE_TYPE_DEFAULT; 2444 rdev->pm.default_power_state_index = state_index; 2445 rdev->pm.power_state[state_index].default_clock_mode = 2446 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2447 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) { 2448 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2449 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2450 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2451 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage; 2452 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci; 2453 } else { 2454 u16 max_vddci = 0; 2455 2456 if (ASIC_IS_DCE4(rdev)) 2457 radeon_atom_get_max_voltage(rdev, 2458 SET_VOLTAGE_TYPE_ASIC_VDDCI, 2459 &max_vddci); 2460 /* patch the table values with the default sclk/mclk from firmware info */ 2461 for (j = 0; j < mode_index; j++) { 2462 rdev->pm.power_state[state_index].clock_info[j].mclk = 2463 rdev->clock.default_mclk; 2464 rdev->pm.power_state[state_index].clock_info[j].sclk = 2465 rdev->clock.default_sclk; 2466 if (vddc) 2467 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage = 2468 vddc; 2469 if (max_vddci) 2470 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci = 2471 max_vddci; 2472 } 2473 } 2474 } 2475 } 2476 2477 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, 2478 int state_index, int mode_index, 2479 union pplib_clock_info *clock_info) 2480 { 2481 u32 sclk, mclk; 2482 u16 vddc; 2483 2484 if (rdev->flags & RADEON_IS_IGP) { 2485 if (rdev->family >= CHIP_PALM) { 2486 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2487 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2488 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2489 } else { 2490 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); 2491 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; 2492 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2493 } 2494 } else if (rdev->family >= CHIP_BONAIRE) { 2495 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); 2496 sclk |= clock_info->ci.ucEngineClockHigh << 16; 2497 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow); 2498 mclk |= clock_info->ci.ucMemoryClockHigh << 16; 2499 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2500 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2501 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2502 VOLTAGE_NONE; 2503 } else if (rdev->family >= CHIP_TAHITI) { 2504 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 2505 sclk |= clock_info->si.ucEngineClockHigh << 16; 2506 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 2507 mclk |= clock_info->si.ucMemoryClockHigh << 16; 2508 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2509 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2510 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2511 VOLTAGE_SW; 2512 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2513 le16_to_cpu(clock_info->si.usVDDC); 2514 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2515 le16_to_cpu(clock_info->si.usVDDCI); 2516 } else if (rdev->family >= CHIP_CEDAR) { 2517 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); 2518 sclk |= clock_info->evergreen.ucEngineClockHigh << 16; 2519 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow); 2520 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16; 2521 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2522 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2523 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2524 VOLTAGE_SW; 2525 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2526 le16_to_cpu(clock_info->evergreen.usVDDC); 2527 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci = 2528 le16_to_cpu(clock_info->evergreen.usVDDCI); 2529 } else { 2530 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); 2531 sclk |= clock_info->r600.ucEngineClockHigh << 16; 2532 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow); 2533 mclk |= clock_info->r600.ucMemoryClockHigh << 16; 2534 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk; 2535 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; 2536 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type = 2537 VOLTAGE_SW; 2538 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = 2539 le16_to_cpu(clock_info->r600.usVDDC); 2540 } 2541 2542 /* patch up vddc if necessary */ 2543 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) { 2544 case ATOM_VIRTUAL_VOLTAGE_ID0: 2545 case ATOM_VIRTUAL_VOLTAGE_ID1: 2546 case ATOM_VIRTUAL_VOLTAGE_ID2: 2547 case ATOM_VIRTUAL_VOLTAGE_ID3: 2548 case ATOM_VIRTUAL_VOLTAGE_ID4: 2549 case ATOM_VIRTUAL_VOLTAGE_ID5: 2550 case ATOM_VIRTUAL_VOLTAGE_ID6: 2551 case ATOM_VIRTUAL_VOLTAGE_ID7: 2552 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, 2553 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage, 2554 &vddc) == 0) 2555 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc; 2556 break; 2557 default: 2558 break; 2559 } 2560 2561 if (rdev->flags & RADEON_IS_IGP) { 2562 /* skip invalid modes */ 2563 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) 2564 return false; 2565 } else { 2566 /* skip invalid modes */ 2567 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) || 2568 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) 2569 return false; 2570 } 2571 return true; 2572 } 2573 2574 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev) 2575 { 2576 struct radeon_mode_info *mode_info = &rdev->mode_info; 2577 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2578 union pplib_power_state *power_state; 2579 int i, j; 2580 int state_index = 0, mode_index = 0; 2581 union pplib_clock_info *clock_info; 2582 bool valid; 2583 union power_info *power_info; 2584 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2585 u16 data_offset; 2586 u8 frev, crev; 2587 2588 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2589 &frev, &crev, &data_offset)) 2590 return state_index; 2591 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2592 2593 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2594 if (power_info->pplib.ucNumStates == 0) 2595 return state_index; 2596 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates, 2597 sizeof(struct radeon_power_state), 2598 GFP_KERNEL); 2599 if (!rdev->pm.power_state) 2600 return state_index; 2601 /* first mode is usually default, followed by low to high */ 2602 for (i = 0; i < power_info->pplib.ucNumStates; i++) { 2603 mode_index = 0; 2604 power_state = (union pplib_power_state *) 2605 (mode_info->atom_context->bios + data_offset + 2606 le16_to_cpu(power_info->pplib.usStateArrayOffset) + 2607 i * power_info->pplib.ucStateEntrySize); 2608 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2609 (mode_info->atom_context->bios + data_offset + 2610 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2611 (power_state->v1.ucNonClockStateIndex * 2612 power_info->pplib.ucNonClockSize)); 2613 rdev->pm.power_state[i].clock_info = 2614 kcalloc((power_info->pplib.ucStateEntrySize - 1) ? 2615 (power_info->pplib.ucStateEntrySize - 1) : 1, 2616 sizeof(struct radeon_pm_clock_info), 2617 GFP_KERNEL); 2618 if (!rdev->pm.power_state[i].clock_info) 2619 return state_index; 2620 if (power_info->pplib.ucStateEntrySize - 1) { 2621 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2622 clock_info = (union pplib_clock_info *) 2623 (mode_info->atom_context->bios + data_offset + 2624 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2625 (power_state->v1.ucClockStateIndices[j] * 2626 power_info->pplib.ucClockInfoSize)); 2627 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2628 state_index, mode_index, 2629 clock_info); 2630 if (valid) 2631 mode_index++; 2632 } 2633 } else { 2634 rdev->pm.power_state[state_index].clock_info[0].mclk = 2635 rdev->clock.default_mclk; 2636 rdev->pm.power_state[state_index].clock_info[0].sclk = 2637 rdev->clock.default_sclk; 2638 mode_index++; 2639 } 2640 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2641 if (mode_index) { 2642 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2643 non_clock_info); 2644 state_index++; 2645 } 2646 } 2647 /* if multiple clock modes, mark the lowest as no display */ 2648 for (i = 0; i < state_index; i++) { 2649 if (rdev->pm.power_state[i].num_clock_modes > 1) 2650 rdev->pm.power_state[i].clock_info[0].flags |= 2651 RADEON_PM_MODE_NO_DISPLAY; 2652 } 2653 /* first mode is usually default */ 2654 if (rdev->pm.default_power_state_index == -1) { 2655 rdev->pm.power_state[0].type = 2656 POWER_STATE_TYPE_DEFAULT; 2657 rdev->pm.default_power_state_index = 0; 2658 rdev->pm.power_state[0].default_clock_mode = 2659 &rdev->pm.power_state[0].clock_info[0]; 2660 } 2661 return state_index; 2662 } 2663 2664 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) 2665 { 2666 struct radeon_mode_info *mode_info = &rdev->mode_info; 2667 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2668 union pplib_power_state *power_state; 2669 int i, j, non_clock_array_index, clock_array_index; 2670 int state_index = 0, mode_index = 0; 2671 union pplib_clock_info *clock_info; 2672 struct _StateArray *state_array; 2673 struct _ClockInfoArray *clock_info_array; 2674 struct _NonClockInfoArray *non_clock_info_array; 2675 bool valid; 2676 union power_info *power_info; 2677 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2678 u16 data_offset; 2679 u8 frev, crev; 2680 u8 *power_state_offset; 2681 2682 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 2683 &frev, &crev, &data_offset)) 2684 return state_index; 2685 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2686 2687 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); 2688 state_array = (struct _StateArray *) 2689 (mode_info->atom_context->bios + data_offset + 2690 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2691 clock_info_array = (struct _ClockInfoArray *) 2692 (mode_info->atom_context->bios + data_offset + 2693 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2694 non_clock_info_array = (struct _NonClockInfoArray *) 2695 (mode_info->atom_context->bios + data_offset + 2696 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2697 if (state_array->ucNumEntries == 0) 2698 return state_index; 2699 rdev->pm.power_state = kcalloc(state_array->ucNumEntries, 2700 sizeof(struct radeon_power_state), 2701 GFP_KERNEL); 2702 if (!rdev->pm.power_state) 2703 return state_index; 2704 power_state_offset = (u8 *)state_array->states; 2705 for (i = 0; i < state_array->ucNumEntries; i++) { 2706 mode_index = 0; 2707 power_state = (union pplib_power_state *)power_state_offset; 2708 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2709 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2710 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2711 rdev->pm.power_state[i].clock_info = 2712 kcalloc(power_state->v2.ucNumDPMLevels ? 2713 power_state->v2.ucNumDPMLevels : 1, 2714 sizeof(struct radeon_pm_clock_info), 2715 GFP_KERNEL); 2716 if (!rdev->pm.power_state[i].clock_info) 2717 return state_index; 2718 if (power_state->v2.ucNumDPMLevels) { 2719 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2720 clock_array_index = power_state->v2.clockInfoIndex[j]; 2721 clock_info = (union pplib_clock_info *) 2722 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2723 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2724 state_index, mode_index, 2725 clock_info); 2726 if (valid) 2727 mode_index++; 2728 } 2729 } else { 2730 rdev->pm.power_state[state_index].clock_info[0].mclk = 2731 rdev->clock.default_mclk; 2732 rdev->pm.power_state[state_index].clock_info[0].sclk = 2733 rdev->clock.default_sclk; 2734 mode_index++; 2735 } 2736 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2737 if (mode_index) { 2738 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index, 2739 non_clock_info); 2740 state_index++; 2741 } 2742 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2743 } 2744 /* if multiple clock modes, mark the lowest as no display */ 2745 for (i = 0; i < state_index; i++) { 2746 if (rdev->pm.power_state[i].num_clock_modes > 1) 2747 rdev->pm.power_state[i].clock_info[0].flags |= 2748 RADEON_PM_MODE_NO_DISPLAY; 2749 } 2750 /* first mode is usually default */ 2751 if (rdev->pm.default_power_state_index == -1) { 2752 rdev->pm.power_state[0].type = 2753 POWER_STATE_TYPE_DEFAULT; 2754 rdev->pm.default_power_state_index = 0; 2755 rdev->pm.power_state[0].default_clock_mode = 2756 &rdev->pm.power_state[0].clock_info[0]; 2757 } 2758 return state_index; 2759 } 2760 2761 void radeon_atombios_get_power_modes(struct radeon_device *rdev) 2762 { 2763 struct radeon_mode_info *mode_info = &rdev->mode_info; 2764 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2765 u16 data_offset; 2766 u8 frev, crev; 2767 int state_index = 0; 2768 2769 rdev->pm.default_power_state_index = -1; 2770 2771 if (atom_parse_data_header(mode_info->atom_context, index, NULL, 2772 &frev, &crev, &data_offset)) { 2773 switch (frev) { 2774 case 1: 2775 case 2: 2776 case 3: 2777 state_index = radeon_atombios_parse_power_table_1_3(rdev); 2778 break; 2779 case 4: 2780 case 5: 2781 state_index = radeon_atombios_parse_power_table_4_5(rdev); 2782 break; 2783 case 6: 2784 state_index = radeon_atombios_parse_power_table_6(rdev); 2785 break; 2786 default: 2787 break; 2788 } 2789 } 2790 2791 if (state_index == 0) { 2792 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2793 if (rdev->pm.power_state) { 2794 rdev->pm.power_state[0].clock_info = 2795 kcalloc(1, 2796 sizeof(struct radeon_pm_clock_info), 2797 GFP_KERNEL); 2798 if (rdev->pm.power_state[0].clock_info) { 2799 /* add the default mode */ 2800 rdev->pm.power_state[state_index].type = 2801 POWER_STATE_TYPE_DEFAULT; 2802 rdev->pm.power_state[state_index].num_clock_modes = 1; 2803 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2804 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2805 rdev->pm.power_state[state_index].default_clock_mode = 2806 &rdev->pm.power_state[state_index].clock_info[0]; 2807 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2808 rdev->pm.power_state[state_index].pcie_lanes = 16; 2809 rdev->pm.default_power_state_index = state_index; 2810 rdev->pm.power_state[state_index].flags = 0; 2811 state_index++; 2812 } 2813 } 2814 } 2815 2816 rdev->pm.num_power_states = state_index; 2817 2818 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2819 rdev->pm.current_clock_mode_index = 0; 2820 if (rdev->pm.default_power_state_index >= 0) 2821 rdev->pm.current_vddc = 2822 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 2823 else 2824 rdev->pm.current_vddc = 0; 2825 } 2826 2827 union get_clock_dividers { 2828 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 2829 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 2830 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 2831 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 2832 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 2833 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 2834 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 2835 }; 2836 2837 int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 2838 u8 clock_type, 2839 u32 clock, 2840 bool strobe_mode, 2841 struct atom_clock_dividers *dividers) 2842 { 2843 union get_clock_dividers args; 2844 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 2845 u8 frev, crev; 2846 2847 memset(&args, 0, sizeof(args)); 2848 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 2849 2850 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2851 return -EINVAL; 2852 2853 switch (crev) { 2854 case 1: 2855 /* r4xx, r5xx */ 2856 args.v1.ucAction = clock_type; 2857 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */ 2858 2859 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2860 2861 dividers->post_div = args.v1.ucPostDiv; 2862 dividers->fb_div = args.v1.ucFbDiv; 2863 dividers->enable_post_div = true; 2864 break; 2865 case 2: 2866 case 3: 2867 case 5: 2868 /* r6xx, r7xx, evergreen, ni, si */ 2869 if (rdev->family <= CHIP_RV770) { 2870 args.v2.ucAction = clock_type; 2871 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */ 2872 2873 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2874 2875 dividers->post_div = args.v2.ucPostDiv; 2876 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); 2877 dividers->ref_div = args.v2.ucAction; 2878 if (rdev->family == CHIP_RV770) { 2879 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? 2880 true : false; 2881 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; 2882 } else 2883 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2884 } else { 2885 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2886 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2887 2888 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2889 2890 dividers->post_div = args.v3.ucPostDiv; 2891 dividers->enable_post_div = (args.v3.ucCntlFlag & 2892 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2893 dividers->enable_dithen = (args.v3.ucCntlFlag & 2894 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2895 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 2896 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 2897 dividers->ref_div = args.v3.ucRefDiv; 2898 dividers->vco_mode = (args.v3.ucCntlFlag & 2899 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2900 } else { 2901 /* for SI we use ComputeMemoryClockParam for memory plls */ 2902 if (rdev->family >= CHIP_TAHITI) 2903 return -EINVAL; 2904 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 2905 if (strobe_mode) 2906 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2907 2908 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2909 2910 dividers->post_div = args.v5.ucPostDiv; 2911 dividers->enable_post_div = (args.v5.ucCntlFlag & 2912 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 2913 dividers->enable_dithen = (args.v5.ucCntlFlag & 2914 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 2915 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 2916 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 2917 dividers->ref_div = args.v5.ucRefDiv; 2918 dividers->vco_mode = (args.v5.ucCntlFlag & 2919 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2920 } 2921 } 2922 break; 2923 case 4: 2924 /* fusion */ 2925 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 2926 2927 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2928 2929 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 2930 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 2931 break; 2932 case 6: 2933 /* CI */ 2934 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 2935 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 2936 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 2937 2938 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2939 2940 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 2941 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 2942 dividers->ref_div = args.v6_out.ucPllRefDiv; 2943 dividers->post_div = args.v6_out.ucPllPostDiv; 2944 dividers->flags = args.v6_out.ucPllCntlFlag; 2945 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 2946 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 2947 break; 2948 default: 2949 return -EINVAL; 2950 } 2951 return 0; 2952 } 2953 2954 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 2955 u32 clock, 2956 bool strobe_mode, 2957 struct atom_mpll_param *mpll_param) 2958 { 2959 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 2960 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 2961 u8 frev, crev; 2962 2963 memset(&args, 0, sizeof(args)); 2964 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 2965 2966 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2967 return -EINVAL; 2968 2969 switch (frev) { 2970 case 2: 2971 switch (crev) { 2972 case 1: 2973 /* SI */ 2974 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 2975 args.ucInputFlag = 0; 2976 if (strobe_mode) 2977 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 2978 2979 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 2980 2981 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 2982 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 2983 mpll_param->post_div = args.ucPostDiv; 2984 mpll_param->dll_speed = args.ucDllSpeed; 2985 mpll_param->bwcntl = args.ucBWCntl; 2986 mpll_param->vco_mode = 2987 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 2988 mpll_param->yclk_sel = 2989 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 2990 mpll_param->qdr = 2991 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 2992 mpll_param->half_rate = 2993 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 2994 break; 2995 default: 2996 return -EINVAL; 2997 } 2998 break; 2999 default: 3000 return -EINVAL; 3001 } 3002 return 0; 3003 } 3004 3005 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) 3006 { 3007 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; 3008 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); 3009 3010 args.ucEnable = enable; 3011 3012 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3013 } 3014 3015 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev) 3016 { 3017 GET_ENGINE_CLOCK_PS_ALLOCATION args; 3018 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 3019 3020 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3021 return le32_to_cpu(args.ulReturnEngineClock); 3022 } 3023 3024 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev) 3025 { 3026 GET_MEMORY_CLOCK_PS_ALLOCATION args; 3027 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 3028 3029 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3030 return le32_to_cpu(args.ulReturnMemoryClock); 3031 } 3032 3033 void radeon_atom_set_engine_clock(struct radeon_device *rdev, 3034 uint32_t eng_clock) 3035 { 3036 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3037 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 3038 3039 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 3040 3041 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3042 } 3043 3044 void radeon_atom_set_memory_clock(struct radeon_device *rdev, 3045 uint32_t mem_clock) 3046 { 3047 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3048 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 3049 3050 if (rdev->flags & RADEON_IS_IGP) 3051 return; 3052 3053 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 3054 3055 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3056 } 3057 3058 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 3059 u32 eng_clock, u32 mem_clock) 3060 { 3061 SET_ENGINE_CLOCK_PS_ALLOCATION args; 3062 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3063 u32 tmp; 3064 3065 memset(&args, 0, sizeof(args)); 3066 3067 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 3068 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 3069 3070 args.ulTargetEngineClock = cpu_to_le32(tmp); 3071 if (mem_clock) 3072 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 3073 3074 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3075 } 3076 3077 void radeon_atom_update_memory_dll(struct radeon_device *rdev, 3078 u32 mem_clock) 3079 { 3080 u32 args; 3081 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3082 3083 args = cpu_to_le32(mem_clock); /* 10 khz */ 3084 3085 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3086 } 3087 3088 void radeon_atom_set_ac_timing(struct radeon_device *rdev, 3089 u32 mem_clock) 3090 { 3091 SET_MEMORY_CLOCK_PS_ALLOCATION args; 3092 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 3093 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24); 3094 3095 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */ 3096 3097 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3098 } 3099 3100 union set_voltage { 3101 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 3102 struct _SET_VOLTAGE_PARAMETERS v1; 3103 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 3104 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 3105 }; 3106 3107 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) 3108 { 3109 union set_voltage args; 3110 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3111 u8 frev, crev, volt_index = voltage_level; 3112 3113 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3114 return; 3115 3116 /* 0xff01 is a flag rather then an actual voltage */ 3117 if (voltage_level == 0xff01) 3118 return; 3119 3120 switch (crev) { 3121 case 1: 3122 args.v1.ucVoltageType = voltage_type; 3123 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 3124 args.v1.ucVoltageIndex = volt_index; 3125 break; 3126 case 2: 3127 args.v2.ucVoltageType = voltage_type; 3128 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 3129 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3130 break; 3131 case 3: 3132 args.v3.ucVoltageType = voltage_type; 3133 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 3134 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 3135 break; 3136 default: 3137 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3138 return; 3139 } 3140 3141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3142 } 3143 3144 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 3145 u16 voltage_id, u16 *voltage) 3146 { 3147 union set_voltage args; 3148 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3149 u8 frev, crev; 3150 3151 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3152 return -EINVAL; 3153 3154 switch (crev) { 3155 case 1: 3156 return -EINVAL; 3157 case 2: 3158 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 3159 args.v2.ucVoltageMode = 0; 3160 args.v2.usVoltageLevel = 0; 3161 3162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3163 3164 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 3165 break; 3166 case 3: 3167 args.v3.ucVoltageType = voltage_type; 3168 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 3169 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 3170 3171 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3172 3173 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 3174 break; 3175 default: 3176 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3177 return -EINVAL; 3178 } 3179 3180 return 0; 3181 } 3182 3183 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 3184 u16 *voltage, 3185 u16 leakage_idx) 3186 { 3187 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 3188 } 3189 3190 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 3191 u16 *leakage_id) 3192 { 3193 union set_voltage args; 3194 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3195 u8 frev, crev; 3196 3197 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3198 return -EINVAL; 3199 3200 switch (crev) { 3201 case 3: 3202 case 4: 3203 args.v3.ucVoltageType = 0; 3204 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 3205 args.v3.usVoltageLevel = 0; 3206 3207 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3208 3209 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 3210 break; 3211 default: 3212 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3213 return -EINVAL; 3214 } 3215 3216 return 0; 3217 } 3218 3219 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 3220 u16 *vddc, u16 *vddci, 3221 u16 virtual_voltage_id, 3222 u16 vbios_voltage_id) 3223 { 3224 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 3225 u8 frev, crev; 3226 u16 data_offset, size; 3227 int i, j; 3228 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 3229 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 3230 3231 *vddc = 0; 3232 *vddci = 0; 3233 3234 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3235 &frev, &crev, &data_offset)) 3236 return -EINVAL; 3237 3238 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 3239 (rdev->mode_info.atom_context->bios + data_offset); 3240 3241 switch (frev) { 3242 case 1: 3243 return -EINVAL; 3244 case 2: 3245 switch (crev) { 3246 case 1: 3247 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 3248 return -EINVAL; 3249 leakage_bin = (u16 *) 3250 (rdev->mode_info.atom_context->bios + data_offset + 3251 le16_to_cpu(profile->usLeakageBinArrayOffset)); 3252 vddc_id_buf = (u16 *) 3253 (rdev->mode_info.atom_context->bios + data_offset + 3254 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 3255 vddc_buf = (u16 *) 3256 (rdev->mode_info.atom_context->bios + data_offset + 3257 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 3258 vddci_id_buf = (u16 *) 3259 (rdev->mode_info.atom_context->bios + data_offset + 3260 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 3261 vddci_buf = (u16 *) 3262 (rdev->mode_info.atom_context->bios + data_offset + 3263 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 3264 3265 if (profile->ucElbVDDC_Num > 0) { 3266 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 3267 if (vddc_id_buf[i] == virtual_voltage_id) { 3268 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3269 if (vbios_voltage_id <= leakage_bin[j]) { 3270 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 3271 break; 3272 } 3273 } 3274 break; 3275 } 3276 } 3277 } 3278 if (profile->ucElbVDDCI_Num > 0) { 3279 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 3280 if (vddci_id_buf[i] == virtual_voltage_id) { 3281 for (j = 0; j < profile->ucLeakageBinNum; j++) { 3282 if (vbios_voltage_id <= leakage_bin[j]) { 3283 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 3284 break; 3285 } 3286 } 3287 break; 3288 } 3289 } 3290 } 3291 break; 3292 default: 3293 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3294 return -EINVAL; 3295 } 3296 break; 3297 default: 3298 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3299 return -EINVAL; 3300 } 3301 3302 return 0; 3303 } 3304 3305 union get_voltage_info { 3306 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 3307 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 3308 }; 3309 3310 int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 3311 u16 virtual_voltage_id, 3312 u16 *voltage) 3313 { 3314 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 3315 u32 entry_id; 3316 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 3317 union get_voltage_info args; 3318 3319 for (entry_id = 0; entry_id < count; entry_id++) { 3320 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 3321 virtual_voltage_id) 3322 break; 3323 } 3324 3325 if (entry_id >= count) 3326 return -EINVAL; 3327 3328 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 3329 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 3330 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 3331 args.in.ulSCLKFreq = 3332 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 3333 3334 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3335 3336 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 3337 3338 return 0; 3339 } 3340 3341 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 3342 u16 voltage_level, u8 voltage_type, 3343 u32 *gpio_value, u32 *gpio_mask) 3344 { 3345 union set_voltage args; 3346 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 3347 u8 frev, crev; 3348 3349 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 3350 return -EINVAL; 3351 3352 switch (crev) { 3353 case 1: 3354 return -EINVAL; 3355 case 2: 3356 args.v2.ucVoltageType = voltage_type; 3357 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK; 3358 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3359 3360 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3361 3362 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2); 3363 3364 args.v2.ucVoltageType = voltage_type; 3365 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL; 3366 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 3367 3368 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3369 3370 *gpio_value = le32_to_cpu(*(u32 *)&args.v2); 3371 break; 3372 default: 3373 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3374 return -EINVAL; 3375 } 3376 3377 return 0; 3378 } 3379 3380 union voltage_object_info { 3381 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 3382 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 3383 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 3384 }; 3385 3386 union voltage_object { 3387 struct _ATOM_VOLTAGE_OBJECT v1; 3388 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 3389 union _ATOM_VOLTAGE_OBJECT_V3 v3; 3390 }; 3391 3392 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1, 3393 u8 voltage_type) 3394 { 3395 u32 size = le16_to_cpu(v1->sHeader.usStructureSize); 3396 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]); 3397 u8 *start = (u8 *)v1; 3398 3399 while (offset < size) { 3400 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset); 3401 if (vo->ucVoltageType == voltage_type) 3402 return vo; 3403 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) + 3404 vo->asFormula.ucNumOfVoltageEntries; 3405 } 3406 return NULL; 3407 } 3408 3409 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2, 3410 u8 voltage_type) 3411 { 3412 u32 size = le16_to_cpu(v2->sHeader.usStructureSize); 3413 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); 3414 u8 *start = (u8 *)v2; 3415 3416 while (offset < size) { 3417 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); 3418 if (vo->ucVoltageType == voltage_type) 3419 return vo; 3420 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) + 3421 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY)); 3422 } 3423 return NULL; 3424 } 3425 3426 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 3427 u8 voltage_type, u8 voltage_mode) 3428 { 3429 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 3430 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 3431 u8 *start = (u8 *)v3; 3432 3433 while (offset < size) { 3434 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 3435 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 3436 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 3437 return vo; 3438 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 3439 } 3440 return NULL; 3441 } 3442 3443 bool 3444 radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 3445 u8 voltage_type, u8 voltage_mode) 3446 { 3447 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3448 u8 frev, crev; 3449 u16 data_offset, size; 3450 union voltage_object_info *voltage_info; 3451 union voltage_object *voltage_object = NULL; 3452 3453 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3454 &frev, &crev, &data_offset)) { 3455 voltage_info = (union voltage_object_info *) 3456 (rdev->mode_info.atom_context->bios + data_offset); 3457 3458 switch (frev) { 3459 case 1: 3460 case 2: 3461 switch (crev) { 3462 case 1: 3463 voltage_object = (union voltage_object *) 3464 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3465 if (voltage_object && 3466 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3467 return true; 3468 break; 3469 case 2: 3470 voltage_object = (union voltage_object *) 3471 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3472 if (voltage_object && 3473 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO)) 3474 return true; 3475 break; 3476 default: 3477 DRM_ERROR("unknown voltage object table\n"); 3478 return false; 3479 } 3480 break; 3481 case 3: 3482 switch (crev) { 3483 case 1: 3484 if (atom_lookup_voltage_object_v3(&voltage_info->v3, 3485 voltage_type, voltage_mode)) 3486 return true; 3487 break; 3488 default: 3489 DRM_ERROR("unknown voltage object table\n"); 3490 return false; 3491 } 3492 break; 3493 default: 3494 DRM_ERROR("unknown voltage object table\n"); 3495 return false; 3496 } 3497 3498 } 3499 return false; 3500 } 3501 3502 int radeon_atom_get_svi2_info(struct radeon_device *rdev, 3503 u8 voltage_type, 3504 u8 *svd_gpio_id, u8 *svc_gpio_id) 3505 { 3506 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3507 u8 frev, crev; 3508 u16 data_offset, size; 3509 union voltage_object_info *voltage_info; 3510 union voltage_object *voltage_object = NULL; 3511 3512 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3513 &frev, &crev, &data_offset)) { 3514 voltage_info = (union voltage_object_info *) 3515 (rdev->mode_info.atom_context->bios + data_offset); 3516 3517 switch (frev) { 3518 case 3: 3519 switch (crev) { 3520 case 1: 3521 voltage_object = (union voltage_object *) 3522 atom_lookup_voltage_object_v3(&voltage_info->v3, 3523 voltage_type, 3524 VOLTAGE_OBJ_SVID2); 3525 if (voltage_object) { 3526 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 3527 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 3528 } else { 3529 return -EINVAL; 3530 } 3531 break; 3532 default: 3533 DRM_ERROR("unknown voltage object table\n"); 3534 return -EINVAL; 3535 } 3536 break; 3537 default: 3538 DRM_ERROR("unknown voltage object table\n"); 3539 return -EINVAL; 3540 } 3541 3542 } 3543 return 0; 3544 } 3545 3546 int radeon_atom_get_max_voltage(struct radeon_device *rdev, 3547 u8 voltage_type, u16 *max_voltage) 3548 { 3549 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3550 u8 frev, crev; 3551 u16 data_offset, size; 3552 union voltage_object_info *voltage_info; 3553 union voltage_object *voltage_object = NULL; 3554 3555 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3556 &frev, &crev, &data_offset)) { 3557 voltage_info = (union voltage_object_info *) 3558 (rdev->mode_info.atom_context->bios + data_offset); 3559 3560 switch (crev) { 3561 case 1: 3562 voltage_object = (union voltage_object *) 3563 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3564 if (voltage_object) { 3565 ATOM_VOLTAGE_FORMULA *formula = 3566 &voltage_object->v1.asFormula; 3567 if (formula->ucFlag & 1) 3568 *max_voltage = 3569 le16_to_cpu(formula->usVoltageBaseLevel) + 3570 formula->ucNumOfVoltageEntries / 2 * 3571 le16_to_cpu(formula->usVoltageStep); 3572 else 3573 *max_voltage = 3574 le16_to_cpu(formula->usVoltageBaseLevel) + 3575 (formula->ucNumOfVoltageEntries - 1) * 3576 le16_to_cpu(formula->usVoltageStep); 3577 return 0; 3578 } 3579 break; 3580 case 2: 3581 voltage_object = (union voltage_object *) 3582 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3583 if (voltage_object) { 3584 ATOM_VOLTAGE_FORMULA_V2 *formula = 3585 &voltage_object->v2.asFormula; 3586 if (formula->ucNumOfVoltageEntries) { 3587 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *) 3588 ((u8 *)&formula->asVIDAdjustEntries[0] + 3589 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1))); 3590 *max_voltage = 3591 le16_to_cpu(lut->usVoltageValue); 3592 return 0; 3593 } 3594 } 3595 break; 3596 default: 3597 DRM_ERROR("unknown voltage object table\n"); 3598 return -EINVAL; 3599 } 3600 3601 } 3602 return -EINVAL; 3603 } 3604 3605 int radeon_atom_get_min_voltage(struct radeon_device *rdev, 3606 u8 voltage_type, u16 *min_voltage) 3607 { 3608 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3609 u8 frev, crev; 3610 u16 data_offset, size; 3611 union voltage_object_info *voltage_info; 3612 union voltage_object *voltage_object = NULL; 3613 3614 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3615 &frev, &crev, &data_offset)) { 3616 voltage_info = (union voltage_object_info *) 3617 (rdev->mode_info.atom_context->bios + data_offset); 3618 3619 switch (crev) { 3620 case 1: 3621 voltage_object = (union voltage_object *) 3622 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3623 if (voltage_object) { 3624 ATOM_VOLTAGE_FORMULA *formula = 3625 &voltage_object->v1.asFormula; 3626 *min_voltage = 3627 le16_to_cpu(formula->usVoltageBaseLevel); 3628 return 0; 3629 } 3630 break; 3631 case 2: 3632 voltage_object = (union voltage_object *) 3633 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3634 if (voltage_object) { 3635 ATOM_VOLTAGE_FORMULA_V2 *formula = 3636 &voltage_object->v2.asFormula; 3637 if (formula->ucNumOfVoltageEntries) { 3638 *min_voltage = 3639 le16_to_cpu(formula->asVIDAdjustEntries[ 3640 0 3641 ].usVoltageValue); 3642 return 0; 3643 } 3644 } 3645 break; 3646 default: 3647 DRM_ERROR("unknown voltage object table\n"); 3648 return -EINVAL; 3649 } 3650 3651 } 3652 return -EINVAL; 3653 } 3654 3655 int radeon_atom_get_voltage_step(struct radeon_device *rdev, 3656 u8 voltage_type, u16 *voltage_step) 3657 { 3658 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3659 u8 frev, crev; 3660 u16 data_offset, size; 3661 union voltage_object_info *voltage_info; 3662 union voltage_object *voltage_object = NULL; 3663 3664 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3665 &frev, &crev, &data_offset)) { 3666 voltage_info = (union voltage_object_info *) 3667 (rdev->mode_info.atom_context->bios + data_offset); 3668 3669 switch (crev) { 3670 case 1: 3671 voltage_object = (union voltage_object *) 3672 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type); 3673 if (voltage_object) { 3674 ATOM_VOLTAGE_FORMULA *formula = 3675 &voltage_object->v1.asFormula; 3676 if (formula->ucFlag & 1) 3677 *voltage_step = 3678 (le16_to_cpu(formula->usVoltageStep) + 1) / 2; 3679 else 3680 *voltage_step = 3681 le16_to_cpu(formula->usVoltageStep); 3682 return 0; 3683 } 3684 break; 3685 case 2: 3686 return -EINVAL; 3687 default: 3688 DRM_ERROR("unknown voltage object table\n"); 3689 return -EINVAL; 3690 } 3691 3692 } 3693 return -EINVAL; 3694 } 3695 3696 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 3697 u8 voltage_type, 3698 u16 nominal_voltage, 3699 u16 *true_voltage) 3700 { 3701 u16 min_voltage, max_voltage, voltage_step; 3702 3703 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage)) 3704 return -EINVAL; 3705 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage)) 3706 return -EINVAL; 3707 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step)) 3708 return -EINVAL; 3709 3710 if (nominal_voltage <= min_voltage) 3711 *true_voltage = min_voltage; 3712 else if (nominal_voltage >= max_voltage) 3713 *true_voltage = max_voltage; 3714 else 3715 *true_voltage = min_voltage + 3716 ((nominal_voltage - min_voltage) / voltage_step) * 3717 voltage_step; 3718 3719 return 0; 3720 } 3721 3722 int radeon_atom_get_voltage_table(struct radeon_device *rdev, 3723 u8 voltage_type, u8 voltage_mode, 3724 struct atom_voltage_table *voltage_table) 3725 { 3726 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 3727 u8 frev, crev; 3728 u16 data_offset, size; 3729 int i, ret; 3730 union voltage_object_info *voltage_info; 3731 union voltage_object *voltage_object = NULL; 3732 3733 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3734 &frev, &crev, &data_offset)) { 3735 voltage_info = (union voltage_object_info *) 3736 (rdev->mode_info.atom_context->bios + data_offset); 3737 3738 switch (frev) { 3739 case 1: 3740 case 2: 3741 switch (crev) { 3742 case 1: 3743 DRM_ERROR("old table version %d, %d\n", frev, crev); 3744 return -EINVAL; 3745 case 2: 3746 voltage_object = (union voltage_object *) 3747 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type); 3748 if (voltage_object) { 3749 ATOM_VOLTAGE_FORMULA_V2 *formula = 3750 &voltage_object->v2.asFormula; 3751 VOLTAGE_LUT_ENTRY *lut; 3752 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES) 3753 return -EINVAL; 3754 lut = &formula->asVIDAdjustEntries[0]; 3755 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) { 3756 voltage_table->entries[i].value = 3757 le16_to_cpu(lut->usVoltageValue); 3758 ret = radeon_atom_get_voltage_gpio_settings(rdev, 3759 voltage_table->entries[i].value, 3760 voltage_type, 3761 &voltage_table->entries[i].smio_low, 3762 &voltage_table->mask_low); 3763 if (ret) 3764 return ret; 3765 lut = (VOLTAGE_LUT_ENTRY *) 3766 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY)); 3767 } 3768 voltage_table->count = formula->ucNumOfVoltageEntries; 3769 return 0; 3770 } 3771 break; 3772 default: 3773 DRM_ERROR("unknown voltage object table\n"); 3774 return -EINVAL; 3775 } 3776 break; 3777 case 3: 3778 switch (crev) { 3779 case 1: 3780 voltage_object = (union voltage_object *) 3781 atom_lookup_voltage_object_v3(&voltage_info->v3, 3782 voltage_type, voltage_mode); 3783 if (voltage_object) { 3784 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 3785 &voltage_object->v3.asGpioVoltageObj; 3786 VOLTAGE_LUT_ENTRY_V2 *lut; 3787 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 3788 return -EINVAL; 3789 lut = &gpio->asVolGpioLut[0]; 3790 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 3791 voltage_table->entries[i].value = 3792 le16_to_cpu(lut->usVoltageValue); 3793 voltage_table->entries[i].smio_low = 3794 le32_to_cpu(lut->ulVoltageId); 3795 lut = (VOLTAGE_LUT_ENTRY_V2 *) 3796 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 3797 } 3798 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 3799 voltage_table->count = gpio->ucGpioEntryNum; 3800 voltage_table->phase_delay = gpio->ucPhaseDelay; 3801 return 0; 3802 } 3803 break; 3804 default: 3805 DRM_ERROR("unknown voltage object table\n"); 3806 return -EINVAL; 3807 } 3808 break; 3809 default: 3810 DRM_ERROR("unknown voltage object table\n"); 3811 return -EINVAL; 3812 } 3813 } 3814 return -EINVAL; 3815 } 3816 3817 union vram_info { 3818 struct _ATOM_VRAM_INFO_V3 v1_3; 3819 struct _ATOM_VRAM_INFO_V4 v1_4; 3820 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 3821 }; 3822 3823 int radeon_atom_get_memory_info(struct radeon_device *rdev, 3824 u8 module_index, struct atom_memory_info *mem_info) 3825 { 3826 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3827 u8 frev, crev, i; 3828 u16 data_offset, size; 3829 union vram_info *vram_info; 3830 3831 memset(mem_info, 0, sizeof(struct atom_memory_info)); 3832 3833 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3834 &frev, &crev, &data_offset)) { 3835 vram_info = (union vram_info *) 3836 (rdev->mode_info.atom_context->bios + data_offset); 3837 switch (frev) { 3838 case 1: 3839 switch (crev) { 3840 case 3: 3841 /* r6xx */ 3842 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) { 3843 ATOM_VRAM_MODULE_V3 *vram_module = 3844 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo; 3845 3846 for (i = 0; i < module_index; i++) { 3847 if (le16_to_cpu(vram_module->usSize) == 0) 3848 return -EINVAL; 3849 vram_module = (ATOM_VRAM_MODULE_V3 *) 3850 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize)); 3851 } 3852 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf; 3853 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0; 3854 } else 3855 return -EINVAL; 3856 break; 3857 case 4: 3858 /* r7xx, evergreen */ 3859 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3860 ATOM_VRAM_MODULE_V4 *vram_module = 3861 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3862 3863 for (i = 0; i < module_index; i++) { 3864 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3865 return -EINVAL; 3866 vram_module = (ATOM_VRAM_MODULE_V4 *) 3867 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3868 } 3869 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3870 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3871 } else 3872 return -EINVAL; 3873 break; 3874 default: 3875 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3876 return -EINVAL; 3877 } 3878 break; 3879 case 2: 3880 switch (crev) { 3881 case 1: 3882 /* ni */ 3883 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 3884 ATOM_VRAM_MODULE_V7 *vram_module = 3885 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo; 3886 3887 for (i = 0; i < module_index; i++) { 3888 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3889 return -EINVAL; 3890 vram_module = (ATOM_VRAM_MODULE_V7 *) 3891 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3892 } 3893 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf; 3894 mem_info->mem_type = vram_module->ucMemoryType & 0xf0; 3895 } else 3896 return -EINVAL; 3897 break; 3898 default: 3899 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3900 return -EINVAL; 3901 } 3902 break; 3903 default: 3904 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3905 return -EINVAL; 3906 } 3907 return 0; 3908 } 3909 return -EINVAL; 3910 } 3911 3912 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 3913 bool gddr5, u8 module_index, 3914 struct atom_memory_clock_range_table *mclk_range_table) 3915 { 3916 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3917 u8 frev, crev, i; 3918 u16 data_offset, size; 3919 union vram_info *vram_info; 3920 u32 mem_timing_size = gddr5 ? 3921 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT); 3922 3923 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table)); 3924 3925 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3926 &frev, &crev, &data_offset)) { 3927 vram_info = (union vram_info *) 3928 (rdev->mode_info.atom_context->bios + data_offset); 3929 switch (frev) { 3930 case 1: 3931 switch (crev) { 3932 case 3: 3933 DRM_ERROR("old table version %d, %d\n", frev, crev); 3934 return -EINVAL; 3935 case 4: 3936 /* r7xx, evergreen */ 3937 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) { 3938 ATOM_VRAM_MODULE_V4 *vram_module = 3939 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo; 3940 ATOM_MEMORY_TIMING_FORMAT *format; 3941 3942 for (i = 0; i < module_index; i++) { 3943 if (le16_to_cpu(vram_module->usModuleSize) == 0) 3944 return -EINVAL; 3945 vram_module = (ATOM_VRAM_MODULE_V4 *) 3946 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize)); 3947 } 3948 mclk_range_table->num_entries = (u8) 3949 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) / 3950 mem_timing_size); 3951 format = &vram_module->asMemTiming[0]; 3952 for (i = 0; i < mclk_range_table->num_entries; i++) { 3953 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange); 3954 format = (ATOM_MEMORY_TIMING_FORMAT *) 3955 ((u8 *)format + mem_timing_size); 3956 } 3957 } else 3958 return -EINVAL; 3959 break; 3960 default: 3961 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3962 return -EINVAL; 3963 } 3964 break; 3965 case 2: 3966 DRM_ERROR("new table version %d, %d\n", frev, crev); 3967 return -EINVAL; 3968 default: 3969 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 3970 return -EINVAL; 3971 } 3972 return 0; 3973 } 3974 return -EINVAL; 3975 } 3976 3977 #define MEM_ID_MASK 0xff000000 3978 #define MEM_ID_SHIFT 24 3979 #define CLOCK_RANGE_MASK 0x00ffffff 3980 #define CLOCK_RANGE_SHIFT 0 3981 #define LOW_NIBBLE_MASK 0xf 3982 #define DATA_EQU_PREV 0 3983 #define DATA_FROM_TABLE 4 3984 3985 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 3986 u8 module_index, 3987 struct atom_mc_reg_table *reg_table) 3988 { 3989 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 3990 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 3991 u32 i = 0, j; 3992 u16 data_offset, size; 3993 union vram_info *vram_info; 3994 3995 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 3996 3997 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, 3998 &frev, &crev, &data_offset)) { 3999 vram_info = (union vram_info *) 4000 (rdev->mode_info.atom_context->bios + data_offset); 4001 switch (frev) { 4002 case 1: 4003 DRM_ERROR("old table version %d, %d\n", frev, crev); 4004 return -EINVAL; 4005 case 2: 4006 switch (crev) { 4007 case 1: 4008 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 4009 ATOM_INIT_REG_BLOCK *reg_block = 4010 (ATOM_INIT_REG_BLOCK *) 4011 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 4012 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 4013 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4014 ((u8 *)reg_block + (2 * sizeof(u16)) + 4015 le16_to_cpu(reg_block->usRegIndexTblSize)); 4016 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 4017 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 4018 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 4019 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 4020 return -EINVAL; 4021 while (i < num_entries) { 4022 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 4023 break; 4024 reg_table->mc_reg_address[i].s1 = 4025 (u16)(le16_to_cpu(format->usRegIndex)); 4026 reg_table->mc_reg_address[i].pre_reg_data = 4027 (u8)(format->ucPreRegDataLength); 4028 i++; 4029 format = (ATOM_INIT_REG_INDEX_FORMAT *) 4030 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 4031 } 4032 reg_table->last = i; 4033 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 4034 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 4035 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 4036 >> MEM_ID_SHIFT); 4037 if (module_index == t_mem_id) { 4038 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 4039 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 4040 >> CLOCK_RANGE_SHIFT); 4041 for (i = 0, j = 1; i < reg_table->last; i++) { 4042 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 4043 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4044 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 4045 j++; 4046 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 4047 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 4048 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 4049 } 4050 } 4051 num_ranges++; 4052 } 4053 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 4054 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 4055 } 4056 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 4057 return -EINVAL; 4058 reg_table->num_entries = num_ranges; 4059 } else 4060 return -EINVAL; 4061 break; 4062 default: 4063 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4064 return -EINVAL; 4065 } 4066 break; 4067 default: 4068 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 4069 return -EINVAL; 4070 } 4071 return 0; 4072 } 4073 return -EINVAL; 4074 } 4075 4076 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) 4077 { 4078 struct radeon_device *rdev = dev->dev_private; 4079 uint32_t bios_2_scratch, bios_6_scratch; 4080 4081 if (rdev->family >= CHIP_R600) { 4082 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4083 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4084 } else { 4085 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4086 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4087 } 4088 4089 /* let the bios control the backlight */ 4090 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 4091 4092 /* tell the bios not to handle mode switching */ 4093 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 4094 4095 /* clear the vbios dpms state */ 4096 if (ASIC_IS_DCE4(rdev)) 4097 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 4098 4099 if (rdev->family >= CHIP_R600) { 4100 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4101 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4102 } else { 4103 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4104 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4105 } 4106 4107 } 4108 4109 void radeon_save_bios_scratch_regs(struct radeon_device *rdev) 4110 { 4111 uint32_t scratch_reg; 4112 int i; 4113 4114 if (rdev->family >= CHIP_R600) 4115 scratch_reg = R600_BIOS_0_SCRATCH; 4116 else 4117 scratch_reg = RADEON_BIOS_0_SCRATCH; 4118 4119 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4120 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4)); 4121 } 4122 4123 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev) 4124 { 4125 uint32_t scratch_reg; 4126 int i; 4127 4128 if (rdev->family >= CHIP_R600) 4129 scratch_reg = R600_BIOS_0_SCRATCH; 4130 else 4131 scratch_reg = RADEON_BIOS_0_SCRATCH; 4132 4133 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++) 4134 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]); 4135 } 4136 4137 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) 4138 { 4139 struct drm_device *dev = encoder->dev; 4140 struct radeon_device *rdev = dev->dev_private; 4141 uint32_t bios_6_scratch; 4142 4143 if (rdev->family >= CHIP_R600) 4144 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4145 else 4146 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4147 4148 if (lock) { 4149 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 4150 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 4151 } else { 4152 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 4153 bios_6_scratch |= ATOM_S6_ACC_MODE; 4154 } 4155 4156 if (rdev->family >= CHIP_R600) 4157 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4158 else 4159 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4160 } 4161 4162 /* at some point we may want to break this out into individual functions */ 4163 void 4164 radeon_atombios_connected_scratch_regs(struct drm_connector *connector, 4165 struct drm_encoder *encoder, 4166 bool connected) 4167 { 4168 struct drm_device *dev = connector->dev; 4169 struct radeon_device *rdev = dev->dev_private; 4170 struct radeon_connector *radeon_connector = 4171 to_radeon_connector(connector); 4172 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4173 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; 4174 4175 if (rdev->family >= CHIP_R600) { 4176 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 4177 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4178 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); 4179 } else { 4180 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 4181 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4182 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 4183 } 4184 4185 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 4186 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 4187 if (connected) { 4188 DRM_DEBUG_KMS("TV1 connected\n"); 4189 bios_3_scratch |= ATOM_S3_TV1_ACTIVE; 4190 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; 4191 } else { 4192 DRM_DEBUG_KMS("TV1 disconnected\n"); 4193 bios_0_scratch &= ~ATOM_S0_TV1_MASK; 4194 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; 4195 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; 4196 } 4197 } 4198 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && 4199 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { 4200 if (connected) { 4201 DRM_DEBUG_KMS("CV connected\n"); 4202 bios_3_scratch |= ATOM_S3_CV_ACTIVE; 4203 bios_6_scratch |= ATOM_S6_ACC_REQ_CV; 4204 } else { 4205 DRM_DEBUG_KMS("CV disconnected\n"); 4206 bios_0_scratch &= ~ATOM_S0_CV_MASK; 4207 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; 4208 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; 4209 } 4210 } 4211 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 4212 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 4213 if (connected) { 4214 DRM_DEBUG_KMS("LCD1 connected\n"); 4215 bios_0_scratch |= ATOM_S0_LCD1; 4216 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; 4217 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; 4218 } else { 4219 DRM_DEBUG_KMS("LCD1 disconnected\n"); 4220 bios_0_scratch &= ~ATOM_S0_LCD1; 4221 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; 4222 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; 4223 } 4224 } 4225 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 4226 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 4227 if (connected) { 4228 DRM_DEBUG_KMS("CRT1 connected\n"); 4229 bios_0_scratch |= ATOM_S0_CRT1_COLOR; 4230 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; 4231 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; 4232 } else { 4233 DRM_DEBUG_KMS("CRT1 disconnected\n"); 4234 bios_0_scratch &= ~ATOM_S0_CRT1_MASK; 4235 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; 4236 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; 4237 } 4238 } 4239 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 4240 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 4241 if (connected) { 4242 DRM_DEBUG_KMS("CRT2 connected\n"); 4243 bios_0_scratch |= ATOM_S0_CRT2_COLOR; 4244 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; 4245 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; 4246 } else { 4247 DRM_DEBUG_KMS("CRT2 disconnected\n"); 4248 bios_0_scratch &= ~ATOM_S0_CRT2_MASK; 4249 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; 4250 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; 4251 } 4252 } 4253 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 4254 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 4255 if (connected) { 4256 DRM_DEBUG_KMS("DFP1 connected\n"); 4257 bios_0_scratch |= ATOM_S0_DFP1; 4258 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; 4259 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; 4260 } else { 4261 DRM_DEBUG_KMS("DFP1 disconnected\n"); 4262 bios_0_scratch &= ~ATOM_S0_DFP1; 4263 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; 4264 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; 4265 } 4266 } 4267 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 4268 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 4269 if (connected) { 4270 DRM_DEBUG_KMS("DFP2 connected\n"); 4271 bios_0_scratch |= ATOM_S0_DFP2; 4272 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; 4273 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; 4274 } else { 4275 DRM_DEBUG_KMS("DFP2 disconnected\n"); 4276 bios_0_scratch &= ~ATOM_S0_DFP2; 4277 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; 4278 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; 4279 } 4280 } 4281 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && 4282 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { 4283 if (connected) { 4284 DRM_DEBUG_KMS("DFP3 connected\n"); 4285 bios_0_scratch |= ATOM_S0_DFP3; 4286 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; 4287 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; 4288 } else { 4289 DRM_DEBUG_KMS("DFP3 disconnected\n"); 4290 bios_0_scratch &= ~ATOM_S0_DFP3; 4291 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; 4292 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; 4293 } 4294 } 4295 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && 4296 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { 4297 if (connected) { 4298 DRM_DEBUG_KMS("DFP4 connected\n"); 4299 bios_0_scratch |= ATOM_S0_DFP4; 4300 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; 4301 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; 4302 } else { 4303 DRM_DEBUG_KMS("DFP4 disconnected\n"); 4304 bios_0_scratch &= ~ATOM_S0_DFP4; 4305 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; 4306 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; 4307 } 4308 } 4309 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && 4310 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { 4311 if (connected) { 4312 DRM_DEBUG_KMS("DFP5 connected\n"); 4313 bios_0_scratch |= ATOM_S0_DFP5; 4314 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; 4315 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; 4316 } else { 4317 DRM_DEBUG_KMS("DFP5 disconnected\n"); 4318 bios_0_scratch &= ~ATOM_S0_DFP5; 4319 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; 4320 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; 4321 } 4322 } 4323 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) && 4324 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) { 4325 if (connected) { 4326 DRM_DEBUG_KMS("DFP6 connected\n"); 4327 bios_0_scratch |= ATOM_S0_DFP6; 4328 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE; 4329 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6; 4330 } else { 4331 DRM_DEBUG_KMS("DFP6 disconnected\n"); 4332 bios_0_scratch &= ~ATOM_S0_DFP6; 4333 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE; 4334 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6; 4335 } 4336 } 4337 4338 if (rdev->family >= CHIP_R600) { 4339 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); 4340 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4341 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); 4342 } else { 4343 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 4344 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4345 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 4346 } 4347 } 4348 4349 void 4350 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 4351 { 4352 struct drm_device *dev = encoder->dev; 4353 struct radeon_device *rdev = dev->dev_private; 4354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4355 uint32_t bios_3_scratch; 4356 4357 if (ASIC_IS_DCE4(rdev)) 4358 return; 4359 4360 if (rdev->family >= CHIP_R600) 4361 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); 4362 else 4363 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); 4364 4365 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4366 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; 4367 bios_3_scratch |= (crtc << 18); 4368 } 4369 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4370 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; 4371 bios_3_scratch |= (crtc << 24); 4372 } 4373 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4374 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; 4375 bios_3_scratch |= (crtc << 16); 4376 } 4377 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4378 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; 4379 bios_3_scratch |= (crtc << 20); 4380 } 4381 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4382 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; 4383 bios_3_scratch |= (crtc << 17); 4384 } 4385 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4386 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; 4387 bios_3_scratch |= (crtc << 19); 4388 } 4389 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4390 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; 4391 bios_3_scratch |= (crtc << 23); 4392 } 4393 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4394 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; 4395 bios_3_scratch |= (crtc << 25); 4396 } 4397 4398 if (rdev->family >= CHIP_R600) 4399 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); 4400 else 4401 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); 4402 } 4403 4404 void 4405 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 4406 { 4407 struct drm_device *dev = encoder->dev; 4408 struct radeon_device *rdev = dev->dev_private; 4409 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4410 uint32_t bios_2_scratch; 4411 4412 if (ASIC_IS_DCE4(rdev)) 4413 return; 4414 4415 if (rdev->family >= CHIP_R600) 4416 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 4417 else 4418 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 4419 4420 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 4421 if (on) 4422 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; 4423 else 4424 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; 4425 } 4426 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { 4427 if (on) 4428 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; 4429 else 4430 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; 4431 } 4432 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 4433 if (on) 4434 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; 4435 else 4436 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; 4437 } 4438 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 4439 if (on) 4440 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; 4441 else 4442 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; 4443 } 4444 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 4445 if (on) 4446 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; 4447 else 4448 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; 4449 } 4450 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 4451 if (on) 4452 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; 4453 else 4454 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; 4455 } 4456 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 4457 if (on) 4458 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; 4459 else 4460 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; 4461 } 4462 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { 4463 if (on) 4464 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; 4465 else 4466 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; 4467 } 4468 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { 4469 if (on) 4470 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; 4471 else 4472 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; 4473 } 4474 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { 4475 if (on) 4476 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; 4477 else 4478 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; 4479 } 4480 4481 if (rdev->family >= CHIP_R600) 4482 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 4483 else 4484 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 4485 } 4486