1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/math64.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/phy/phy.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_of.h> 24 25 #include "rockchip_drm_drv.h" 26 #include "rockchip_drm_vop.h" 27 28 #define DSI_PHY_RSTZ 0xa0 29 #define PHY_DISFORCEPLL 0 30 #define PHY_ENFORCEPLL BIT(3) 31 #define PHY_DISABLECLK 0 32 #define PHY_ENABLECLK BIT(2) 33 #define PHY_RSTZ 0 34 #define PHY_UNRSTZ BIT(1) 35 #define PHY_SHUTDOWNZ 0 36 #define PHY_UNSHUTDOWNZ BIT(0) 37 38 #define DSI_PHY_IF_CFG 0xa4 39 #define N_LANES(n) ((((n) - 1) & 0x3) << 0) 40 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 41 42 #define DSI_PHY_STATUS 0xb0 43 #define LOCK BIT(0) 44 #define STOP_STATE_CLK_LANE BIT(2) 45 46 #define DSI_PHY_TST_CTRL0 0xb4 47 #define PHY_TESTCLK BIT(1) 48 #define PHY_UNTESTCLK 0 49 #define PHY_TESTCLR BIT(0) 50 #define PHY_UNTESTCLR 0 51 52 #define DSI_PHY_TST_CTRL1 0xb8 53 #define PHY_TESTEN BIT(16) 54 #define PHY_UNTESTEN 0 55 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 56 #define PHY_TESTDIN(n) (((n) & 0xff) << 0) 57 58 #define DSI_INT_ST0 0xbc 59 #define DSI_INT_ST1 0xc0 60 #define DSI_INT_MSK0 0xc4 61 #define DSI_INT_MSK1 0xc8 62 63 #define PHY_STATUS_TIMEOUT_US 10000 64 #define CMD_PKT_STATUS_TIMEOUT_US 20000 65 66 #define BYPASS_VCO_RANGE BIT(7) 67 #define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 68 #define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 69 #define VCO_IN_CAP_CON_LOW (0x1 << 1) 70 #define VCO_IN_CAP_CON_HIGH (0x2 << 1) 71 #define REF_BIAS_CUR_SEL BIT(0) 72 73 #define CP_CURRENT_3UA 0x1 74 #define CP_CURRENT_4_5UA 0x2 75 #define CP_CURRENT_7_5UA 0x6 76 #define CP_CURRENT_6UA 0x9 77 #define CP_CURRENT_12UA 0xb 78 #define CP_CURRENT_SEL(val) ((val) & 0xf) 79 #define CP_PROGRAM_EN BIT(7) 80 81 #define LPF_RESISTORS_15_5KOHM 0x1 82 #define LPF_RESISTORS_13KOHM 0x2 83 #define LPF_RESISTORS_11_5KOHM 0x4 84 #define LPF_RESISTORS_10_5KOHM 0x8 85 #define LPF_RESISTORS_8KOHM 0x10 86 #define LPF_PROGRAM_EN BIT(6) 87 #define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 88 89 #define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 90 91 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 92 #define LOW_PROGRAM_EN 0 93 #define HIGH_PROGRAM_EN BIT(7) 94 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 95 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 96 #define PLL_LOOP_DIV_EN BIT(5) 97 #define PLL_INPUT_DIV_EN BIT(4) 98 99 #define POWER_CONTROL BIT(6) 100 #define INTERNAL_REG_CURRENT BIT(3) 101 #define BIAS_BLOCK_ON BIT(2) 102 #define BANDGAP_ON BIT(0) 103 104 #define TER_RESISTOR_HIGH BIT(7) 105 #define TER_RESISTOR_LOW 0 106 #define LEVEL_SHIFTERS_ON BIT(6) 107 #define TER_CAL_DONE BIT(5) 108 #define SETRD_MAX (0x7 << 2) 109 #define POWER_MANAGE BIT(1) 110 #define TER_RESISTORS_ON BIT(0) 111 112 #define BIASEXTR_SEL(val) ((val) & 0x7) 113 #define BANDGAP_SEL(val) ((val) & 0x7) 114 #define TLP_PROGRAM_EN BIT(7) 115 #define THS_PRE_PROGRAM_EN BIT(7) 116 #define THS_ZERO_PROGRAM_EN BIT(6) 117 118 #define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 119 #define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 120 #define PLL_LPF_AND_CP_CONTROL 0x12 121 #define PLL_INPUT_DIVIDER_RATIO 0x17 122 #define PLL_LOOP_DIVIDER_RATIO 0x18 123 #define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 124 #define BANDGAP_AND_BIAS_CONTROL 0x20 125 #define TERMINATION_RESISTER_CONTROL 0x21 126 #define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 127 #define HS_RX_CONTROL_OF_LANE_0 0x44 128 #define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 129 #define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 130 #define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 131 #define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 132 #define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 133 #define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 134 #define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 135 #define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 136 #define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 137 #define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 138 #define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 139 140 #define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 141 #define DW_MIPI_NEEDS_GRF_CLK BIT(1) 142 143 #define PX30_GRF_PD_VO_CON1 0x0438 144 #define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 145 #define PX30_DSI_FORCERXMODE BIT(6) 146 #define PX30_DSI_TURNDISABLE BIT(5) 147 #define PX30_DSI_LCDC_SEL BIT(0) 148 149 #define RK3288_GRF_SOC_CON6 0x025c 150 #define RK3288_DSI0_LCDC_SEL BIT(6) 151 #define RK3288_DSI1_LCDC_SEL BIT(9) 152 153 #define RK3399_GRF_SOC_CON20 0x6250 154 #define RK3399_DSI0_LCDC_SEL BIT(0) 155 #define RK3399_DSI1_LCDC_SEL BIT(4) 156 157 #define RK3399_GRF_SOC_CON22 0x6258 158 #define RK3399_DSI0_TURNREQUEST (0xf << 12) 159 #define RK3399_DSI0_TURNDISABLE (0xf << 8) 160 #define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 161 #define RK3399_DSI0_FORCERXMODE (0xf << 0) 162 163 #define RK3399_GRF_SOC_CON23 0x625c 164 #define RK3399_DSI1_TURNDISABLE (0xf << 12) 165 #define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 166 #define RK3399_DSI1_FORCERXMODE (0xf << 4) 167 #define RK3399_DSI1_ENABLE (0xf << 0) 168 169 #define RK3399_GRF_SOC_CON24 0x6260 170 #define RK3399_TXRX_MASTERSLAVEZ BIT(7) 171 #define RK3399_TXRX_ENABLECLK BIT(6) 172 #define RK3399_TXRX_BASEDIR BIT(5) 173 174 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 175 176 #define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) 177 178 enum { 179 BANDGAP_97_07, 180 BANDGAP_98_05, 181 BANDGAP_99_02, 182 BANDGAP_100_00, 183 BANDGAP_93_17, 184 BANDGAP_94_15, 185 BANDGAP_95_12, 186 BANDGAP_96_10, 187 }; 188 189 enum { 190 BIASEXTR_87_1, 191 BIASEXTR_91_5, 192 BIASEXTR_95_9, 193 BIASEXTR_100, 194 BIASEXTR_105_94, 195 BIASEXTR_111_88, 196 BIASEXTR_118_8, 197 BIASEXTR_127_7, 198 }; 199 200 struct rockchip_dw_dsi_chip_data { 201 u32 reg; 202 203 u32 lcdsel_grf_reg; 204 u32 lcdsel_big; 205 u32 lcdsel_lit; 206 207 u32 enable_grf_reg; 208 u32 enable; 209 210 u32 lanecfg1_grf_reg; 211 u32 lanecfg1; 212 u32 lanecfg2_grf_reg; 213 u32 lanecfg2; 214 215 unsigned int flags; 216 unsigned int max_data_lanes; 217 }; 218 219 struct dw_mipi_dsi_rockchip { 220 struct device *dev; 221 struct drm_encoder encoder; 222 void __iomem *base; 223 224 struct regmap *grf_regmap; 225 struct clk *pllref_clk; 226 struct clk *grf_clk; 227 struct clk *phy_cfg_clk; 228 229 /* dual-channel */ 230 bool is_slave; 231 struct dw_mipi_dsi_rockchip *slave; 232 233 /* optional external dphy */ 234 struct phy *phy; 235 union phy_configure_opts phy_opts; 236 237 unsigned int lane_mbps; /* per lane */ 238 u16 input_div; 239 u16 feedback_div; 240 u32 format; 241 242 struct dw_mipi_dsi *dmd; 243 const struct rockchip_dw_dsi_chip_data *cdata; 244 struct dw_mipi_dsi_plat_data pdata; 245 int devcnt; 246 }; 247 248 struct dphy_pll_parameter_map { 249 unsigned int max_mbps; 250 u8 hsfreqrange; 251 u8 icpctrl; 252 u8 lpfctrl; 253 }; 254 255 /* The table is based on 27MHz DPHY pll reference clock. */ 256 static const struct dphy_pll_parameter_map dppa_map[] = { 257 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 258 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 259 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 260 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 261 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 262 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 263 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 264 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 265 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 266 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 267 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 268 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 269 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 270 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 271 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 272 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 273 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 274 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 275 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 276 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 277 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 278 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 279 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 280 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 281 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 282 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 283 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 284 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 285 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 286 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 287 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 288 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 289 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 290 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 291 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 292 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 293 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 294 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 295 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 296 }; 297 298 static int max_mbps_to_parameter(unsigned int max_mbps) 299 { 300 int i; 301 302 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 303 if (dppa_map[i].max_mbps >= max_mbps) 304 return i; 305 306 return -EINVAL; 307 } 308 309 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 310 { 311 writel(val, dsi->base + reg); 312 } 313 314 static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) 315 { 316 return readl(dsi->base + reg); 317 } 318 319 static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask) 320 { 321 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 322 } 323 324 static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, 325 u32 mask, u32 val) 326 { 327 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 328 } 329 330 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 331 u8 test_code, 332 u8 test_data) 333 { 334 /* 335 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 336 * is latched internally as the current test code. Test data is 337 * programmed internally by rising edge on TESTCLK. 338 */ 339 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 340 341 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 342 PHY_TESTDIN(test_code)); 343 344 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 345 346 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 347 PHY_TESTDIN(test_data)); 348 349 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 350 } 351 352 /** 353 * ns2bc - Nanoseconds to byte clock cycles 354 */ 355 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 356 { 357 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 358 } 359 360 /** 361 * ns2ui - Nanoseconds to UI time periods 362 */ 363 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 364 { 365 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 366 } 367 368 static int dw_mipi_dsi_phy_init(void *priv_data) 369 { 370 struct dw_mipi_dsi_rockchip *dsi = priv_data; 371 int ret, i, vco; 372 373 if (dsi->phy) 374 return 0; 375 376 /* 377 * Get vco from frequency(lane_mbps) 378 * vco frequency table 379 * 000 - between 80 and 200 MHz 380 * 001 - between 200 and 300 MHz 381 * 010 - between 300 and 500 MHz 382 * 011 - between 500 and 700 MHz 383 * 100 - between 700 and 900 MHz 384 * 101 - between 900 and 1100 MHz 385 * 110 - between 1100 and 1300 MHz 386 * 111 - between 1300 and 1500 MHz 387 */ 388 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 389 390 i = max_mbps_to_parameter(dsi->lane_mbps); 391 if (i < 0) { 392 DRM_DEV_ERROR(dsi->dev, 393 "failed to get parameter for %dmbps clock\n", 394 dsi->lane_mbps); 395 return i; 396 } 397 398 ret = clk_prepare_enable(dsi->phy_cfg_clk); 399 if (ret) { 400 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 401 return ret; 402 } 403 404 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 405 BYPASS_VCO_RANGE | 406 VCO_RANGE_CON_SEL(vco) | 407 VCO_IN_CAP_CON_LOW | 408 REF_BIAS_CUR_SEL); 409 410 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 411 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 412 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 413 CP_PROGRAM_EN | LPF_PROGRAM_EN | 414 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 415 416 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 417 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 418 419 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 420 INPUT_DIVIDER(dsi->input_div)); 421 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 422 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 423 LOW_PROGRAM_EN); 424 /* 425 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 426 * to make the configured LSB effective according to IP simulation 427 * and lab test results. 428 * Only in this way can we get correct mipi phy pll frequency. 429 */ 430 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 431 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 432 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 433 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 434 HIGH_PROGRAM_EN); 435 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 436 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 437 438 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 439 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 440 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 441 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 442 443 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 444 POWER_CONTROL | INTERNAL_REG_CURRENT | 445 BIAS_BLOCK_ON | BANDGAP_ON); 446 447 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 448 TER_RESISTOR_LOW | TER_CAL_DONE | 449 SETRD_MAX | TER_RESISTORS_ON); 450 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 451 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 452 SETRD_MAX | POWER_MANAGE | 453 TER_RESISTORS_ON); 454 455 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 456 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 457 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 458 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 459 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 460 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 461 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 462 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 463 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 464 BIT(5) | ns2bc(dsi, 100)); 465 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 466 BIT(5) | (ns2bc(dsi, 60) + 7)); 467 468 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 469 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 470 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 471 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 472 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 473 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 474 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 475 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 476 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 477 BIT(5) | ns2bc(dsi, 100)); 478 479 clk_disable_unprepare(dsi->phy_cfg_clk); 480 481 return ret; 482 } 483 484 static void dw_mipi_dsi_phy_power_on(void *priv_data) 485 { 486 struct dw_mipi_dsi_rockchip *dsi = priv_data; 487 int ret; 488 489 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 490 if (ret) { 491 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 492 return; 493 } 494 495 phy_configure(dsi->phy, &dsi->phy_opts); 496 phy_power_on(dsi->phy); 497 } 498 499 static void dw_mipi_dsi_phy_power_off(void *priv_data) 500 { 501 struct dw_mipi_dsi_rockchip *dsi = priv_data; 502 503 phy_power_off(dsi->phy); 504 } 505 506 static int 507 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 508 unsigned long mode_flags, u32 lanes, u32 format, 509 unsigned int *lane_mbps) 510 { 511 struct dw_mipi_dsi_rockchip *dsi = priv_data; 512 int bpp; 513 unsigned long mpclk, tmp; 514 unsigned int target_mbps = 1000; 515 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 516 unsigned long best_freq = 0; 517 unsigned long fvco_min, fvco_max, fin, fout; 518 unsigned int min_prediv, max_prediv; 519 unsigned int _prediv, uninitialized_var(best_prediv); 520 unsigned long _fbdiv, uninitialized_var(best_fbdiv); 521 unsigned long min_delta = ULONG_MAX; 522 523 dsi->format = format; 524 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 525 if (bpp < 0) { 526 DRM_DEV_ERROR(dsi->dev, 527 "failed to get bpp for pixel format %d\n", 528 dsi->format); 529 return bpp; 530 } 531 532 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 533 if (mpclk) { 534 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 535 tmp = mpclk * (bpp / lanes) * 10 / 8; 536 if (tmp < max_mbps) 537 target_mbps = tmp; 538 else 539 DRM_DEV_ERROR(dsi->dev, 540 "DPHY clock frequency is out of range\n"); 541 } 542 543 /* for external phy only a the mipi_dphy_config is necessary */ 544 if (dsi->phy) { 545 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 546 bpp, lanes, 547 &dsi->phy_opts.mipi_dphy); 548 dsi->lane_mbps = target_mbps; 549 *lane_mbps = dsi->lane_mbps; 550 551 return 0; 552 } 553 554 fin = clk_get_rate(dsi->pllref_clk); 555 fout = target_mbps * USEC_PER_SEC; 556 557 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 558 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 559 max_prediv = fin / (5 * USEC_PER_SEC); 560 561 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 562 fvco_min = 80 * USEC_PER_SEC; 563 fvco_max = 1500 * USEC_PER_SEC; 564 565 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 566 u64 tmp; 567 u32 delta; 568 /* Fvco = Fref * M / N */ 569 tmp = (u64)fout * _prediv; 570 do_div(tmp, fin); 571 _fbdiv = tmp; 572 /* 573 * Due to the use of a "by 2 pre-scaler," the range of the 574 * feedback multiplication value M is limited to even division 575 * numbers, and m must be greater than 6, not bigger than 512. 576 */ 577 if (_fbdiv < 6 || _fbdiv > 512) 578 continue; 579 580 _fbdiv += _fbdiv % 2; 581 582 tmp = (u64)_fbdiv * fin; 583 do_div(tmp, _prediv); 584 if (tmp < fvco_min || tmp > fvco_max) 585 continue; 586 587 delta = abs(fout - tmp); 588 if (delta < min_delta) { 589 best_prediv = _prediv; 590 best_fbdiv = _fbdiv; 591 min_delta = delta; 592 best_freq = tmp; 593 } 594 } 595 596 if (best_freq) { 597 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 598 *lane_mbps = dsi->lane_mbps; 599 dsi->input_div = best_prediv; 600 dsi->feedback_div = best_fbdiv; 601 } else { 602 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 603 return -EINVAL; 604 } 605 606 return 0; 607 } 608 609 struct hstt { 610 unsigned int maxfreq; 611 struct dw_mipi_dsi_dphy_timing timing; 612 }; 613 614 #define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 615 { \ 616 .maxfreq = _maxfreq, \ 617 .timing = { \ 618 .clk_lp2hs = _c_lp2hs, \ 619 .clk_hs2lp = _c_hs2lp, \ 620 .data_lp2hs = _d_lp2hs, \ 621 .data_hs2lp = _d_hs2lp, \ 622 } \ 623 } 624 625 /* Table A-3 High-Speed Transition Times */ 626 struct hstt hstt_table[] = { 627 HSTT( 90, 32, 20, 26, 13), 628 HSTT( 100, 35, 23, 28, 14), 629 HSTT( 110, 32, 22, 26, 13), 630 HSTT( 130, 31, 20, 27, 13), 631 HSTT( 140, 33, 22, 26, 14), 632 HSTT( 150, 33, 21, 26, 14), 633 HSTT( 170, 32, 20, 27, 13), 634 HSTT( 180, 36, 23, 30, 15), 635 HSTT( 200, 40, 22, 33, 15), 636 HSTT( 220, 40, 22, 33, 15), 637 HSTT( 240, 44, 24, 36, 16), 638 HSTT( 250, 48, 24, 38, 17), 639 HSTT( 270, 48, 24, 38, 17), 640 HSTT( 300, 50, 27, 41, 18), 641 HSTT( 330, 56, 28, 45, 18), 642 HSTT( 360, 59, 28, 48, 19), 643 HSTT( 400, 61, 30, 50, 20), 644 HSTT( 450, 67, 31, 55, 21), 645 HSTT( 500, 73, 31, 59, 22), 646 HSTT( 550, 79, 36, 63, 24), 647 HSTT( 600, 83, 37, 68, 25), 648 HSTT( 650, 90, 38, 73, 27), 649 HSTT( 700, 95, 40, 77, 28), 650 HSTT( 750, 102, 40, 84, 28), 651 HSTT( 800, 106, 42, 87, 30), 652 HSTT( 850, 113, 44, 93, 31), 653 HSTT( 900, 118, 47, 98, 32), 654 HSTT( 950, 124, 47, 102, 34), 655 HSTT(1000, 130, 49, 107, 35), 656 HSTT(1050, 135, 51, 111, 37), 657 HSTT(1100, 139, 51, 114, 38), 658 HSTT(1150, 146, 54, 120, 40), 659 HSTT(1200, 153, 57, 125, 41), 660 HSTT(1250, 158, 58, 130, 42), 661 HSTT(1300, 163, 58, 135, 44), 662 HSTT(1350, 168, 60, 140, 45), 663 HSTT(1400, 172, 64, 144, 47), 664 HSTT(1450, 176, 65, 148, 48), 665 HSTT(1500, 181, 66, 153, 50) 666 }; 667 668 static int 669 dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 670 struct dw_mipi_dsi_dphy_timing *timing) 671 { 672 int i; 673 674 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 675 if (lane_mbps < hstt_table[i].maxfreq) 676 break; 677 678 if (i == ARRAY_SIZE(hstt_table)) 679 i--; 680 681 *timing = hstt_table[i].timing; 682 683 return 0; 684 } 685 686 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 687 .init = dw_mipi_dsi_phy_init, 688 .power_on = dw_mipi_dsi_phy_power_on, 689 .power_off = dw_mipi_dsi_phy_power_off, 690 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 691 .get_timing = dw_mipi_dsi_phy_get_timing, 692 }; 693 694 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi, 695 int mux) 696 { 697 if (dsi->cdata->lcdsel_grf_reg) 698 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 699 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 700 701 if (dsi->cdata->lanecfg1_grf_reg) 702 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 703 dsi->cdata->lanecfg1); 704 705 if (dsi->cdata->lanecfg2_grf_reg) 706 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 707 dsi->cdata->lanecfg2); 708 709 if (dsi->cdata->enable_grf_reg) 710 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 711 dsi->cdata->enable); 712 } 713 714 static int 715 dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 716 struct drm_crtc_state *crtc_state, 717 struct drm_connector_state *conn_state) 718 { 719 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 720 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 721 722 switch (dsi->format) { 723 case MIPI_DSI_FMT_RGB888: 724 s->output_mode = ROCKCHIP_OUT_MODE_P888; 725 break; 726 case MIPI_DSI_FMT_RGB666: 727 s->output_mode = ROCKCHIP_OUT_MODE_P666; 728 break; 729 case MIPI_DSI_FMT_RGB565: 730 s->output_mode = ROCKCHIP_OUT_MODE_P565; 731 break; 732 default: 733 WARN_ON(1); 734 return -EINVAL; 735 } 736 737 s->output_type = DRM_MODE_CONNECTOR_DSI; 738 if (dsi->slave) 739 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 740 741 return 0; 742 } 743 744 static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 745 { 746 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 747 int ret, mux; 748 749 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 750 &dsi->encoder); 751 if (mux < 0) 752 return; 753 754 pm_runtime_get_sync(dsi->dev); 755 if (dsi->slave) 756 pm_runtime_get_sync(dsi->slave->dev); 757 758 /* 759 * For the RK3399, the clk of grf must be enabled before writing grf 760 * register. And for RK3288 or other soc, this grf_clk must be NULL, 761 * the clk_prepare_enable return true directly. 762 */ 763 ret = clk_prepare_enable(dsi->grf_clk); 764 if (ret) { 765 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 766 return; 767 } 768 769 dw_mipi_dsi_rockchip_config(dsi, mux); 770 if (dsi->slave) 771 dw_mipi_dsi_rockchip_config(dsi->slave, mux); 772 773 clk_disable_unprepare(dsi->grf_clk); 774 } 775 776 static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) 777 { 778 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 779 780 if (dsi->slave) 781 pm_runtime_put(dsi->slave->dev); 782 pm_runtime_put(dsi->dev); 783 } 784 785 static const struct drm_encoder_helper_funcs 786 dw_mipi_dsi_encoder_helper_funcs = { 787 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 788 .enable = dw_mipi_dsi_encoder_enable, 789 .disable = dw_mipi_dsi_encoder_disable, 790 }; 791 792 static const struct drm_encoder_funcs dw_mipi_dsi_encoder_funcs = { 793 .destroy = drm_encoder_cleanup, 794 }; 795 796 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 797 struct drm_device *drm_dev) 798 { 799 struct drm_encoder *encoder = &dsi->encoder; 800 int ret; 801 802 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 803 dsi->dev->of_node); 804 805 ret = drm_encoder_init(drm_dev, encoder, &dw_mipi_dsi_encoder_funcs, 806 DRM_MODE_ENCODER_DSI, NULL); 807 if (ret) { 808 DRM_ERROR("Failed to initialize encoder with drm\n"); 809 return ret; 810 } 811 812 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 813 814 return 0; 815 } 816 817 static struct device 818 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 819 { 820 const struct of_device_id *match; 821 struct device_node *node = NULL, *local; 822 823 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 824 825 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 826 if (!local) 827 return NULL; 828 829 while ((node = of_find_compatible_node(node, NULL, 830 match->compatible))) { 831 struct device_node *remote; 832 833 /* found ourself */ 834 if (node == dsi->dev->of_node) 835 continue; 836 837 remote = of_graph_get_remote_node(node, 1, 0); 838 if (!remote) 839 continue; 840 841 /* same display device in port1-ep0 for both */ 842 if (remote == local) { 843 struct dw_mipi_dsi_rockchip *dsi2; 844 struct platform_device *pdev; 845 846 pdev = of_find_device_by_node(node); 847 848 /* 849 * we have found the second, so will either return it 850 * or return with an error. In any case won't need the 851 * nodes anymore nor continue the loop. 852 */ 853 of_node_put(remote); 854 of_node_put(node); 855 of_node_put(local); 856 857 if (!pdev) 858 return ERR_PTR(-EPROBE_DEFER); 859 860 dsi2 = platform_get_drvdata(pdev); 861 if (!dsi2) { 862 platform_device_put(pdev); 863 return ERR_PTR(-EPROBE_DEFER); 864 } 865 866 return &pdev->dev; 867 } 868 869 of_node_put(remote); 870 } 871 872 of_node_put(local); 873 874 return NULL; 875 } 876 877 static int dw_mipi_dsi_rockchip_bind(struct device *dev, 878 struct device *master, 879 void *data) 880 { 881 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 882 struct drm_device *drm_dev = data; 883 struct device *second; 884 bool master1, master2; 885 int ret; 886 887 second = dw_mipi_dsi_rockchip_find_second(dsi); 888 if (IS_ERR(second)) 889 return PTR_ERR(second); 890 891 if (second) { 892 master1 = of_property_read_bool(dsi->dev->of_node, 893 "clock-master"); 894 master2 = of_property_read_bool(second->of_node, 895 "clock-master"); 896 897 if (master1 && master2) { 898 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 899 return -EINVAL; 900 } 901 902 if (!master1 && !master2) { 903 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 904 return -EINVAL; 905 } 906 907 /* we are the slave in dual-DSI */ 908 if (!master1) { 909 dsi->is_slave = true; 910 return 0; 911 } 912 913 dsi->slave = dev_get_drvdata(second); 914 if (!dsi->slave) { 915 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 916 return -ENODEV; 917 } 918 919 dsi->slave->is_slave = true; 920 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 921 put_device(second); 922 } 923 924 ret = clk_prepare_enable(dsi->pllref_clk); 925 if (ret) { 926 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 927 return ret; 928 } 929 930 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 931 if (ret) { 932 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 933 return ret; 934 } 935 936 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); 937 if (ret) { 938 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 939 return ret; 940 } 941 942 return 0; 943 } 944 945 static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 946 struct device *master, 947 void *data) 948 { 949 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 950 951 if (dsi->is_slave) 952 return; 953 954 dw_mipi_dsi_unbind(dsi->dmd); 955 956 clk_disable_unprepare(dsi->pllref_clk); 957 } 958 959 static const struct component_ops dw_mipi_dsi_rockchip_ops = { 960 .bind = dw_mipi_dsi_rockchip_bind, 961 .unbind = dw_mipi_dsi_rockchip_unbind, 962 }; 963 964 static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 965 struct mipi_dsi_device *device) 966 { 967 struct dw_mipi_dsi_rockchip *dsi = priv_data; 968 struct device *second; 969 int ret; 970 971 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 972 if (ret) { 973 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 974 ret); 975 return ret; 976 } 977 978 second = dw_mipi_dsi_rockchip_find_second(dsi); 979 if (IS_ERR(second)) 980 return PTR_ERR(second); 981 if (second) { 982 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 983 if (ret) { 984 DRM_DEV_ERROR(second, 985 "Failed to register component: %d\n", 986 ret); 987 return ret; 988 } 989 } 990 991 return 0; 992 } 993 994 static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 995 struct mipi_dsi_device *device) 996 { 997 struct dw_mipi_dsi_rockchip *dsi = priv_data; 998 struct device *second; 999 1000 second = dw_mipi_dsi_rockchip_find_second(dsi); 1001 if (second && !IS_ERR(second)) 1002 component_del(second, &dw_mipi_dsi_rockchip_ops); 1003 1004 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1005 1006 return 0; 1007 } 1008 1009 static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1010 .attach = dw_mipi_dsi_rockchip_host_attach, 1011 .detach = dw_mipi_dsi_rockchip_host_detach, 1012 }; 1013 1014 static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1015 { 1016 struct device *dev = &pdev->dev; 1017 struct device_node *np = dev->of_node; 1018 struct dw_mipi_dsi_rockchip *dsi; 1019 struct resource *res; 1020 const struct rockchip_dw_dsi_chip_data *cdata = 1021 of_device_get_match_data(dev); 1022 int ret, i; 1023 1024 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1025 if (!dsi) 1026 return -ENOMEM; 1027 1028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1029 dsi->base = devm_ioremap_resource(dev, res); 1030 if (IS_ERR(dsi->base)) { 1031 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1032 return PTR_ERR(dsi->base); 1033 } 1034 1035 i = 0; 1036 while (cdata[i].reg) { 1037 if (cdata[i].reg == res->start) { 1038 dsi->cdata = &cdata[i]; 1039 break; 1040 } 1041 1042 i++; 1043 } 1044 1045 if (!dsi->cdata) { 1046 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1047 return -EINVAL; 1048 } 1049 1050 /* try to get a possible external dphy */ 1051 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1052 if (IS_ERR(dsi->phy)) { 1053 ret = PTR_ERR(dsi->phy); 1054 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1055 return ret; 1056 } 1057 1058 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1059 if (IS_ERR(dsi->pllref_clk)) { 1060 if (dsi->phy) { 1061 /* 1062 * if external phy is present, pll will be 1063 * generated there. 1064 */ 1065 dsi->pllref_clk = NULL; 1066 } else { 1067 ret = PTR_ERR(dsi->pllref_clk); 1068 DRM_DEV_ERROR(dev, 1069 "Unable to get pll reference clock: %d\n", 1070 ret); 1071 return ret; 1072 } 1073 } 1074 1075 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1076 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1077 if (IS_ERR(dsi->phy_cfg_clk)) { 1078 ret = PTR_ERR(dsi->phy_cfg_clk); 1079 DRM_DEV_ERROR(dev, 1080 "Unable to get phy_cfg_clk: %d\n", ret); 1081 return ret; 1082 } 1083 } 1084 1085 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1086 dsi->grf_clk = devm_clk_get(dev, "grf"); 1087 if (IS_ERR(dsi->grf_clk)) { 1088 ret = PTR_ERR(dsi->grf_clk); 1089 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1090 return ret; 1091 } 1092 } 1093 1094 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1095 if (IS_ERR(dsi->grf_regmap)) { 1096 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n"); 1097 return PTR_ERR(dsi->grf_regmap); 1098 } 1099 1100 dsi->dev = dev; 1101 dsi->pdata.base = dsi->base; 1102 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1103 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1104 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1105 dsi->pdata.priv_data = dsi; 1106 platform_set_drvdata(pdev, dsi); 1107 1108 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1109 if (IS_ERR(dsi->dmd)) { 1110 ret = PTR_ERR(dsi->dmd); 1111 if (ret != -EPROBE_DEFER) 1112 DRM_DEV_ERROR(dev, 1113 "Failed to probe dw_mipi_dsi: %d\n", ret); 1114 goto err_clkdisable; 1115 } 1116 1117 return 0; 1118 1119 err_clkdisable: 1120 clk_disable_unprepare(dsi->pllref_clk); 1121 return ret; 1122 } 1123 1124 static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1125 { 1126 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1127 1128 if (dsi->devcnt == 0) 1129 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1130 1131 dw_mipi_dsi_remove(dsi->dmd); 1132 1133 return 0; 1134 } 1135 1136 static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1137 { 1138 .reg = 0xff450000, 1139 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1140 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1141 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1142 PX30_DSI_LCDC_SEL), 1143 1144 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1145 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1146 PX30_DSI_FORCERXMODE | 1147 PX30_DSI_FORCETXSTOPMODE), 1148 1149 .max_data_lanes = 4, 1150 }, 1151 { /* sentinel */ } 1152 }; 1153 1154 static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1155 { 1156 .reg = 0xff960000, 1157 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1158 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1159 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1160 1161 .max_data_lanes = 4, 1162 }, 1163 { 1164 .reg = 0xff964000, 1165 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1166 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1167 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1168 1169 .max_data_lanes = 4, 1170 }, 1171 { /* sentinel */ } 1172 }; 1173 1174 static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1175 { 1176 .reg = 0xff960000, 1177 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1178 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1179 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1180 RK3399_DSI0_LCDC_SEL), 1181 1182 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1183 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1184 RK3399_DSI0_TURNDISABLE | 1185 RK3399_DSI0_FORCETXSTOPMODE | 1186 RK3399_DSI0_FORCERXMODE), 1187 1188 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1189 .max_data_lanes = 4, 1190 }, 1191 { 1192 .reg = 0xff968000, 1193 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1194 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1195 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1196 RK3399_DSI1_LCDC_SEL), 1197 1198 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1199 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1200 RK3399_DSI1_FORCETXSTOPMODE | 1201 RK3399_DSI1_FORCERXMODE | 1202 RK3399_DSI1_ENABLE), 1203 1204 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1205 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1206 RK3399_TXRX_ENABLECLK, 1207 RK3399_TXRX_MASTERSLAVEZ | 1208 RK3399_TXRX_ENABLECLK | 1209 RK3399_TXRX_BASEDIR), 1210 1211 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1212 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1213 1214 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1215 .max_data_lanes = 4, 1216 }, 1217 { /* sentinel */ } 1218 }; 1219 1220 static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1221 { 1222 .compatible = "rockchip,px30-mipi-dsi", 1223 .data = &px30_chip_data, 1224 }, { 1225 .compatible = "rockchip,rk3288-mipi-dsi", 1226 .data = &rk3288_chip_data, 1227 }, { 1228 .compatible = "rockchip,rk3399-mipi-dsi", 1229 .data = &rk3399_chip_data, 1230 }, 1231 { /* sentinel */ } 1232 }; 1233 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1234 1235 struct platform_driver dw_mipi_dsi_rockchip_driver = { 1236 .probe = dw_mipi_dsi_rockchip_probe, 1237 .remove = dw_mipi_dsi_rockchip_remove, 1238 .driver = { 1239 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1240 .name = "dw-mipi-dsi-rockchip", 1241 }, 1242 }; 1243