1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> 5 * Fabien Dessenne <fabien.dessenne@st.com> 6 * for STMicroelectronics. 7 */ 8 9 #include <linux/dma-mapping.h> 10 #include <linux/seq_file.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_device.h> 14 #include <drm/drm_fb_cma_helper.h> 15 #include <drm/drm_fourcc.h> 16 #include <drm/drm_gem_cma_helper.h> 17 18 #include "sti_compositor.h" 19 #include "sti_gdp.h" 20 #include "sti_plane.h" 21 #include "sti_vtg.h" 22 23 #define ALPHASWITCH BIT(6) 24 #define ENA_COLOR_FILL BIT(8) 25 #define BIGNOTLITTLE BIT(23) 26 #define WAIT_NEXT_VSYNC BIT(31) 27 28 /* GDP color formats */ 29 #define GDP_RGB565 0x00 30 #define GDP_RGB888 0x01 31 #define GDP_RGB888_32 0x02 32 #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH) 33 #define GDP_ARGB8565 0x04 34 #define GDP_ARGB8888 0x05 35 #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH) 36 #define GDP_ARGB1555 0x06 37 #define GDP_ARGB4444 0x07 38 39 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt } 40 41 static struct gdp_format_to_str { 42 int format; 43 char name[20]; 44 } gdp_format_to_str[] = { 45 GDP2STR(RGB565), 46 GDP2STR(RGB888), 47 GDP2STR(RGB888_32), 48 GDP2STR(XBGR8888), 49 GDP2STR(ARGB8565), 50 GDP2STR(ARGB8888), 51 GDP2STR(ABGR8888), 52 GDP2STR(ARGB1555), 53 GDP2STR(ARGB4444) 54 }; 55 56 #define GAM_GDP_CTL_OFFSET 0x00 57 #define GAM_GDP_AGC_OFFSET 0x04 58 #define GAM_GDP_VPO_OFFSET 0x0C 59 #define GAM_GDP_VPS_OFFSET 0x10 60 #define GAM_GDP_PML_OFFSET 0x14 61 #define GAM_GDP_PMP_OFFSET 0x18 62 #define GAM_GDP_SIZE_OFFSET 0x1C 63 #define GAM_GDP_NVN_OFFSET 0x24 64 #define GAM_GDP_KEY1_OFFSET 0x28 65 #define GAM_GDP_KEY2_OFFSET 0x2C 66 #define GAM_GDP_PPT_OFFSET 0x34 67 #define GAM_GDP_CML_OFFSET 0x3C 68 #define GAM_GDP_MST_OFFSET 0x68 69 70 #define GAM_GDP_ALPHARANGE_255 BIT(5) 71 #define GAM_GDP_AGC_FULL_RANGE 0x00808080 72 #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0)) 73 74 #define GAM_GDP_SIZE_MAX_WIDTH 3840 75 #define GAM_GDP_SIZE_MAX_HEIGHT 2160 76 77 #define GDP_NODE_NB_BANK 2 78 #define GDP_NODE_PER_FIELD 2 79 80 struct sti_gdp_node { 81 u32 gam_gdp_ctl; 82 u32 gam_gdp_agc; 83 u32 reserved1; 84 u32 gam_gdp_vpo; 85 u32 gam_gdp_vps; 86 u32 gam_gdp_pml; 87 u32 gam_gdp_pmp; 88 u32 gam_gdp_size; 89 u32 reserved2; 90 u32 gam_gdp_nvn; 91 u32 gam_gdp_key1; 92 u32 gam_gdp_key2; 93 u32 reserved3; 94 u32 gam_gdp_ppt; 95 u32 reserved4; 96 u32 gam_gdp_cml; 97 }; 98 99 struct sti_gdp_node_list { 100 struct sti_gdp_node *top_field; 101 dma_addr_t top_field_paddr; 102 struct sti_gdp_node *btm_field; 103 dma_addr_t btm_field_paddr; 104 }; 105 106 /* 107 * STI GDP structure 108 * 109 * @sti_plane: sti_plane structure 110 * @dev: driver device 111 * @regs: gdp registers 112 * @clk_pix: pixel clock for the current gdp 113 * @clk_main_parent: gdp parent clock if main path used 114 * @clk_aux_parent: gdp parent clock if aux path used 115 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification 116 * @is_curr_top: true if the current node processed is the top field 117 * @node_list: array of node list 118 * @vtg: registered vtg 119 */ 120 struct sti_gdp { 121 struct sti_plane plane; 122 struct device *dev; 123 void __iomem *regs; 124 struct clk *clk_pix; 125 struct clk *clk_main_parent; 126 struct clk *clk_aux_parent; 127 struct notifier_block vtg_field_nb; 128 bool is_curr_top; 129 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK]; 130 struct sti_vtg *vtg; 131 }; 132 133 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane) 134 135 static const uint32_t gdp_supported_formats[] = { 136 DRM_FORMAT_XRGB8888, 137 DRM_FORMAT_XBGR8888, 138 DRM_FORMAT_ARGB8888, 139 DRM_FORMAT_ABGR8888, 140 DRM_FORMAT_ARGB4444, 141 DRM_FORMAT_ARGB1555, 142 DRM_FORMAT_RGB565, 143 DRM_FORMAT_RGB888, 144 }; 145 146 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 147 readl(gdp->regs + reg ## _OFFSET)) 148 149 static void gdp_dbg_ctl(struct seq_file *s, int val) 150 { 151 int i; 152 153 seq_puts(s, "\tColor:"); 154 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) { 155 if (gdp_format_to_str[i].format == (val & 0x1F)) { 156 seq_puts(s, gdp_format_to_str[i].name); 157 break; 158 } 159 } 160 if (i == ARRAY_SIZE(gdp_format_to_str)) 161 seq_puts(s, "<UNKNOWN>"); 162 163 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0); 164 } 165 166 static void gdp_dbg_vpo(struct seq_file *s, int val) 167 { 168 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 169 } 170 171 static void gdp_dbg_vps(struct seq_file *s, int val) 172 { 173 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF); 174 } 175 176 static void gdp_dbg_size(struct seq_file *s, int val) 177 { 178 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF); 179 } 180 181 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val) 182 { 183 void *base = NULL; 184 unsigned int i; 185 186 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 187 if (gdp->node_list[i].top_field_paddr == val) { 188 base = gdp->node_list[i].top_field; 189 break; 190 } 191 if (gdp->node_list[i].btm_field_paddr == val) { 192 base = gdp->node_list[i].btm_field; 193 break; 194 } 195 } 196 197 if (base) 198 seq_printf(s, "\tVirt @: %p", base); 199 } 200 201 static void gdp_dbg_ppt(struct seq_file *s, int val) 202 { 203 if (val & GAM_GDP_PPT_IGNORE) 204 seq_puts(s, "\tNot displayed on mixer!"); 205 } 206 207 static void gdp_dbg_mst(struct seq_file *s, int val) 208 { 209 if (val & 1) 210 seq_puts(s, "\tBUFFER UNDERFLOW!"); 211 } 212 213 static int gdp_dbg_show(struct seq_file *s, void *data) 214 { 215 struct drm_info_node *node = s->private; 216 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 217 struct drm_plane *drm_plane = &gdp->plane.drm_plane; 218 struct drm_crtc *crtc; 219 220 drm_modeset_lock(&drm_plane->mutex, NULL); 221 crtc = drm_plane->state->crtc; 222 drm_modeset_unlock(&drm_plane->mutex); 223 224 seq_printf(s, "%s: (vaddr = 0x%p)", 225 sti_plane_to_str(&gdp->plane), gdp->regs); 226 227 DBGFS_DUMP(GAM_GDP_CTL); 228 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET)); 229 DBGFS_DUMP(GAM_GDP_AGC); 230 DBGFS_DUMP(GAM_GDP_VPO); 231 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET)); 232 DBGFS_DUMP(GAM_GDP_VPS); 233 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET)); 234 DBGFS_DUMP(GAM_GDP_PML); 235 DBGFS_DUMP(GAM_GDP_PMP); 236 DBGFS_DUMP(GAM_GDP_SIZE); 237 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET)); 238 DBGFS_DUMP(GAM_GDP_NVN); 239 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 240 DBGFS_DUMP(GAM_GDP_KEY1); 241 DBGFS_DUMP(GAM_GDP_KEY2); 242 DBGFS_DUMP(GAM_GDP_PPT); 243 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET)); 244 DBGFS_DUMP(GAM_GDP_CML); 245 DBGFS_DUMP(GAM_GDP_MST); 246 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET)); 247 248 seq_puts(s, "\n\n"); 249 if (!crtc) 250 seq_puts(s, " Not connected to any DRM CRTC\n"); 251 else 252 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n", 253 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc))); 254 255 return 0; 256 } 257 258 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node) 259 { 260 seq_printf(s, "\t@:0x%p", node); 261 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl); 262 gdp_dbg_ctl(s, node->gam_gdp_ctl); 263 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc); 264 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo); 265 gdp_dbg_vpo(s, node->gam_gdp_vpo); 266 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps); 267 gdp_dbg_vps(s, node->gam_gdp_vps); 268 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml); 269 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp); 270 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size); 271 gdp_dbg_size(s, node->gam_gdp_size); 272 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn); 273 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1); 274 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2); 275 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt); 276 gdp_dbg_ppt(s, node->gam_gdp_ppt); 277 seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml); 278 } 279 280 static int gdp_node_dbg_show(struct seq_file *s, void *arg) 281 { 282 struct drm_info_node *node = s->private; 283 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data; 284 unsigned int b; 285 286 for (b = 0; b < GDP_NODE_NB_BANK; b++) { 287 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b); 288 gdp_node_dump_node(s, gdp->node_list[b].top_field); 289 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b); 290 gdp_node_dump_node(s, gdp->node_list[b].btm_field); 291 } 292 293 return 0; 294 } 295 296 static struct drm_info_list gdp0_debugfs_files[] = { 297 { "gdp0", gdp_dbg_show, 0, NULL }, 298 { "gdp0_node", gdp_node_dbg_show, 0, NULL }, 299 }; 300 301 static struct drm_info_list gdp1_debugfs_files[] = { 302 { "gdp1", gdp_dbg_show, 0, NULL }, 303 { "gdp1_node", gdp_node_dbg_show, 0, NULL }, 304 }; 305 306 static struct drm_info_list gdp2_debugfs_files[] = { 307 { "gdp2", gdp_dbg_show, 0, NULL }, 308 { "gdp2_node", gdp_node_dbg_show, 0, NULL }, 309 }; 310 311 static struct drm_info_list gdp3_debugfs_files[] = { 312 { "gdp3", gdp_dbg_show, 0, NULL }, 313 { "gdp3_node", gdp_node_dbg_show, 0, NULL }, 314 }; 315 316 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor) 317 { 318 unsigned int i; 319 struct drm_info_list *gdp_debugfs_files; 320 int nb_files; 321 322 switch (gdp->plane.desc) { 323 case STI_GDP_0: 324 gdp_debugfs_files = gdp0_debugfs_files; 325 nb_files = ARRAY_SIZE(gdp0_debugfs_files); 326 break; 327 case STI_GDP_1: 328 gdp_debugfs_files = gdp1_debugfs_files; 329 nb_files = ARRAY_SIZE(gdp1_debugfs_files); 330 break; 331 case STI_GDP_2: 332 gdp_debugfs_files = gdp2_debugfs_files; 333 nb_files = ARRAY_SIZE(gdp2_debugfs_files); 334 break; 335 case STI_GDP_3: 336 gdp_debugfs_files = gdp3_debugfs_files; 337 nb_files = ARRAY_SIZE(gdp3_debugfs_files); 338 break; 339 default: 340 return -EINVAL; 341 } 342 343 for (i = 0; i < nb_files; i++) 344 gdp_debugfs_files[i].data = gdp; 345 346 return drm_debugfs_create_files(gdp_debugfs_files, 347 nb_files, 348 minor->debugfs_root, minor); 349 } 350 351 static int sti_gdp_fourcc2format(int fourcc) 352 { 353 switch (fourcc) { 354 case DRM_FORMAT_XRGB8888: 355 return GDP_RGB888_32; 356 case DRM_FORMAT_XBGR8888: 357 return GDP_XBGR8888; 358 case DRM_FORMAT_ARGB8888: 359 return GDP_ARGB8888; 360 case DRM_FORMAT_ABGR8888: 361 return GDP_ABGR8888; 362 case DRM_FORMAT_ARGB4444: 363 return GDP_ARGB4444; 364 case DRM_FORMAT_ARGB1555: 365 return GDP_ARGB1555; 366 case DRM_FORMAT_RGB565: 367 return GDP_RGB565; 368 case DRM_FORMAT_RGB888: 369 return GDP_RGB888; 370 } 371 return -1; 372 } 373 374 static int sti_gdp_get_alpharange(int format) 375 { 376 switch (format) { 377 case GDP_ARGB8565: 378 case GDP_ARGB8888: 379 case GDP_ABGR8888: 380 return GAM_GDP_ALPHARANGE_255; 381 } 382 return 0; 383 } 384 385 /** 386 * sti_gdp_get_free_nodes 387 * @gdp: gdp pointer 388 * 389 * Look for a GDP node list that is not currently read by the HW. 390 * 391 * RETURNS: 392 * Pointer to the free GDP node list 393 */ 394 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp) 395 { 396 int hw_nvn; 397 unsigned int i; 398 399 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 400 if (!hw_nvn) 401 goto end; 402 403 for (i = 0; i < GDP_NODE_NB_BANK; i++) 404 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) && 405 (hw_nvn != gdp->node_list[i].top_field_paddr)) 406 return &gdp->node_list[i]; 407 408 /* in hazardious cases restart with the first node */ 409 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n", 410 sti_plane_to_str(&gdp->plane), hw_nvn); 411 412 end: 413 return &gdp->node_list[0]; 414 } 415 416 /** 417 * sti_gdp_get_current_nodes 418 * @gdp: gdp pointer 419 * 420 * Look for GDP nodes that are currently read by the HW. 421 * 422 * RETURNS: 423 * Pointer to the current GDP node list 424 */ 425 static 426 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp) 427 { 428 int hw_nvn; 429 unsigned int i; 430 431 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET); 432 if (!hw_nvn) 433 goto end; 434 435 for (i = 0; i < GDP_NODE_NB_BANK; i++) 436 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) || 437 (hw_nvn == gdp->node_list[i].top_field_paddr)) 438 return &gdp->node_list[i]; 439 440 end: 441 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n", 442 hw_nvn, sti_plane_to_str(&gdp->plane)); 443 444 return NULL; 445 } 446 447 /** 448 * sti_gdp_disable 449 * @gdp: gdp pointer 450 * 451 * Disable a GDP. 452 */ 453 static void sti_gdp_disable(struct sti_gdp *gdp) 454 { 455 unsigned int i; 456 457 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane)); 458 459 /* Set the nodes as 'to be ignored on mixer' */ 460 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 461 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 462 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE; 463 } 464 465 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb)) 466 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); 467 468 if (gdp->clk_pix) 469 clk_disable_unprepare(gdp->clk_pix); 470 471 gdp->plane.status = STI_PLANE_DISABLED; 472 gdp->vtg = NULL; 473 } 474 475 /** 476 * sti_gdp_field_cb 477 * @nb: notifier block 478 * @event: event message 479 * @data: private data 480 * 481 * Handle VTG top field and bottom field event. 482 * 483 * RETURNS: 484 * 0 on success. 485 */ 486 static int sti_gdp_field_cb(struct notifier_block *nb, 487 unsigned long event, void *data) 488 { 489 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb); 490 491 if (gdp->plane.status == STI_PLANE_FLUSHING) { 492 /* disable need to be synchronize on vsync event */ 493 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n", 494 sti_plane_to_str(&gdp->plane)); 495 496 sti_gdp_disable(gdp); 497 } 498 499 switch (event) { 500 case VTG_TOP_FIELD_EVENT: 501 gdp->is_curr_top = true; 502 break; 503 case VTG_BOTTOM_FIELD_EVENT: 504 gdp->is_curr_top = false; 505 break; 506 default: 507 DRM_ERROR("unsupported event: %lu\n", event); 508 break; 509 } 510 511 return 0; 512 } 513 514 static void sti_gdp_init(struct sti_gdp *gdp) 515 { 516 struct device_node *np = gdp->dev->of_node; 517 dma_addr_t dma_addr; 518 void *base; 519 unsigned int i, size; 520 521 /* Allocate all the nodes within a single memory page */ 522 size = sizeof(struct sti_gdp_node) * 523 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK; 524 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL); 525 526 if (!base) { 527 DRM_ERROR("Failed to allocate memory for GDP node\n"); 528 return; 529 } 530 memset(base, 0, size); 531 532 for (i = 0; i < GDP_NODE_NB_BANK; i++) { 533 if (dma_addr & 0xF) { 534 DRM_ERROR("Mem alignment failed\n"); 535 return; 536 } 537 gdp->node_list[i].top_field = base; 538 gdp->node_list[i].top_field_paddr = dma_addr; 539 540 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base); 541 base += sizeof(struct sti_gdp_node); 542 dma_addr += sizeof(struct sti_gdp_node); 543 544 if (dma_addr & 0xF) { 545 DRM_ERROR("Mem alignment failed\n"); 546 return; 547 } 548 gdp->node_list[i].btm_field = base; 549 gdp->node_list[i].btm_field_paddr = dma_addr; 550 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base); 551 base += sizeof(struct sti_gdp_node); 552 dma_addr += sizeof(struct sti_gdp_node); 553 } 554 555 if (of_device_is_compatible(np, "st,stih407-compositor")) { 556 /* GDP of STiH407 chip have its own pixel clock */ 557 char *clk_name; 558 559 switch (gdp->plane.desc) { 560 case STI_GDP_0: 561 clk_name = "pix_gdp1"; 562 break; 563 case STI_GDP_1: 564 clk_name = "pix_gdp2"; 565 break; 566 case STI_GDP_2: 567 clk_name = "pix_gdp3"; 568 break; 569 case STI_GDP_3: 570 clk_name = "pix_gdp4"; 571 break; 572 default: 573 DRM_ERROR("GDP id not recognized\n"); 574 return; 575 } 576 577 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name); 578 if (IS_ERR(gdp->clk_pix)) 579 DRM_ERROR("Cannot get %s clock\n", clk_name); 580 581 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent"); 582 if (IS_ERR(gdp->clk_main_parent)) 583 DRM_ERROR("Cannot get main_parent clock\n"); 584 585 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent"); 586 if (IS_ERR(gdp->clk_aux_parent)) 587 DRM_ERROR("Cannot get aux_parent clock\n"); 588 } 589 } 590 591 /** 592 * sti_gdp_get_dst 593 * @dev: device 594 * @dst: requested destination size 595 * @src: source size 596 * 597 * Return the cropped / clamped destination size 598 * 599 * RETURNS: 600 * cropped / clamped destination size 601 */ 602 static int sti_gdp_get_dst(struct device *dev, int dst, int src) 603 { 604 if (dst == src) 605 return dst; 606 607 if (dst < src) { 608 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n"); 609 return dst; 610 } 611 612 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n"); 613 return src; 614 } 615 616 static int sti_gdp_atomic_check(struct drm_plane *drm_plane, 617 struct drm_plane_state *state) 618 { 619 struct sti_plane *plane = to_sti_plane(drm_plane); 620 struct sti_gdp *gdp = to_sti_gdp(plane); 621 struct drm_crtc *crtc = state->crtc; 622 struct drm_framebuffer *fb = state->fb; 623 struct drm_crtc_state *crtc_state; 624 struct sti_mixer *mixer; 625 struct drm_display_mode *mode; 626 int dst_x, dst_y, dst_w, dst_h; 627 int src_x, src_y, src_w, src_h; 628 int format; 629 630 /* no need for further checks if the plane is being disabled */ 631 if (!crtc || !fb) 632 return 0; 633 634 mixer = to_sti_mixer(crtc); 635 crtc_state = drm_atomic_get_crtc_state(state->state, crtc); 636 mode = &crtc_state->mode; 637 dst_x = state->crtc_x; 638 dst_y = state->crtc_y; 639 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 640 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 641 /* src_x are in 16.16 format */ 642 src_x = state->src_x >> 16; 643 src_y = state->src_y >> 16; 644 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 645 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 646 647 format = sti_gdp_fourcc2format(fb->format->format); 648 if (format == -1) { 649 DRM_ERROR("Format not supported by GDP %.4s\n", 650 (char *)&fb->format->format); 651 return -EINVAL; 652 } 653 654 if (!drm_fb_cma_get_gem_obj(fb, 0)) { 655 DRM_ERROR("Can't get CMA GEM object for fb\n"); 656 return -EINVAL; 657 } 658 659 /* Set gdp clock */ 660 if (mode->clock && gdp->clk_pix) { 661 struct clk *clkp; 662 int rate = mode->clock * 1000; 663 int res; 664 665 /* 666 * According to the mixer used, the gdp pixel clock 667 * should have a different parent clock. 668 */ 669 if (mixer->id == STI_MIXER_MAIN) 670 clkp = gdp->clk_main_parent; 671 else 672 clkp = gdp->clk_aux_parent; 673 674 if (clkp) 675 clk_set_parent(gdp->clk_pix, clkp); 676 677 res = clk_set_rate(gdp->clk_pix, rate); 678 if (res < 0) { 679 DRM_ERROR("Cannot set rate (%dHz) for gdp\n", 680 rate); 681 return -EINVAL; 682 } 683 } 684 685 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", 686 crtc->base.id, sti_mixer_to_str(mixer), 687 drm_plane->base.id, sti_plane_to_str(plane)); 688 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n", 689 sti_plane_to_str(plane), 690 dst_w, dst_h, dst_x, dst_y, 691 src_w, src_h, src_x, src_y); 692 693 return 0; 694 } 695 696 static void sti_gdp_atomic_update(struct drm_plane *drm_plane, 697 struct drm_plane_state *oldstate) 698 { 699 struct drm_plane_state *state = drm_plane->state; 700 struct sti_plane *plane = to_sti_plane(drm_plane); 701 struct sti_gdp *gdp = to_sti_gdp(plane); 702 struct drm_crtc *crtc = state->crtc; 703 struct drm_framebuffer *fb = state->fb; 704 struct drm_display_mode *mode; 705 int dst_x, dst_y, dst_w, dst_h; 706 int src_x, src_y, src_w, src_h; 707 struct drm_gem_cma_object *cma_obj; 708 struct sti_gdp_node_list *list; 709 struct sti_gdp_node_list *curr_list; 710 struct sti_gdp_node *top_field, *btm_field; 711 u32 dma_updated_top; 712 u32 dma_updated_btm; 713 int format; 714 unsigned int bpp; 715 u32 ydo, xdo, yds, xds; 716 717 if (!crtc || !fb) 718 return; 719 720 if ((oldstate->fb == state->fb) && 721 (oldstate->crtc_x == state->crtc_x) && 722 (oldstate->crtc_y == state->crtc_y) && 723 (oldstate->crtc_w == state->crtc_w) && 724 (oldstate->crtc_h == state->crtc_h) && 725 (oldstate->src_x == state->src_x) && 726 (oldstate->src_y == state->src_y) && 727 (oldstate->src_w == state->src_w) && 728 (oldstate->src_h == state->src_h)) { 729 /* No change since last update, do not post cmd */ 730 DRM_DEBUG_DRIVER("No change, not posting cmd\n"); 731 plane->status = STI_PLANE_UPDATED; 732 return; 733 } 734 735 if (!gdp->vtg) { 736 struct sti_compositor *compo = dev_get_drvdata(gdp->dev); 737 struct sti_mixer *mixer = to_sti_mixer(crtc); 738 739 /* Register gdp callback */ 740 gdp->vtg = compo->vtg[mixer->id]; 741 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); 742 clk_prepare_enable(gdp->clk_pix); 743 } 744 745 mode = &crtc->mode; 746 dst_x = state->crtc_x; 747 dst_y = state->crtc_y; 748 dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x); 749 dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); 750 /* src_x are in 16.16 format */ 751 src_x = state->src_x >> 16; 752 src_y = state->src_y >> 16; 753 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH); 754 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); 755 756 list = sti_gdp_get_free_nodes(gdp); 757 top_field = list->top_field; 758 btm_field = list->btm_field; 759 760 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__, 761 sti_plane_to_str(plane), top_field, btm_field); 762 763 /* build the top field */ 764 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE; 765 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC; 766 format = sti_gdp_fourcc2format(fb->format->format); 767 top_field->gam_gdp_ctl |= format; 768 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format); 769 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE; 770 771 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 772 773 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id, 774 (char *)&fb->format->format, 775 (unsigned long)cma_obj->paddr); 776 777 /* pixel memory location */ 778 bpp = fb->format->cpp[0]; 779 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0]; 780 top_field->gam_gdp_pml += src_x * bpp; 781 top_field->gam_gdp_pml += src_y * fb->pitches[0]; 782 783 /* output parameters (clamped / cropped) */ 784 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w); 785 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); 786 ydo = sti_vtg_get_line_number(*mode, dst_y); 787 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); 788 xdo = sti_vtg_get_pixel_number(*mode, dst_x); 789 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1); 790 top_field->gam_gdp_vpo = (ydo << 16) | xdo; 791 top_field->gam_gdp_vps = (yds << 16) | xds; 792 793 /* input parameters */ 794 src_w = dst_w; 795 top_field->gam_gdp_pmp = fb->pitches[0]; 796 top_field->gam_gdp_size = src_h << 16 | src_w; 797 798 /* Same content and chained together */ 799 memcpy(btm_field, top_field, sizeof(*btm_field)); 800 top_field->gam_gdp_nvn = list->btm_field_paddr; 801 btm_field->gam_gdp_nvn = list->top_field_paddr; 802 803 /* Interlaced mode */ 804 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 805 btm_field->gam_gdp_pml = top_field->gam_gdp_pml + 806 fb->pitches[0]; 807 808 /* Update the NVN field of the 'right' field of the current GDP node 809 * (being used by the HW) with the address of the updated ('free') top 810 * field GDP node. 811 * - In interlaced mode the 'right' field is the bottom field as we 812 * update frames starting from their top field 813 * - In progressive mode, we update both bottom and top fields which 814 * are equal nodes. 815 * At the next VSYNC, the updated node list will be used by the HW. 816 */ 817 curr_list = sti_gdp_get_current_nodes(gdp); 818 dma_updated_top = list->top_field_paddr; 819 dma_updated_btm = list->btm_field_paddr; 820 821 dev_dbg(gdp->dev, "Current NVN:0x%X\n", 822 readl(gdp->regs + GAM_GDP_NVN_OFFSET)); 823 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n", 824 (unsigned long)cma_obj->paddr, 825 readl(gdp->regs + GAM_GDP_PML_OFFSET)); 826 827 if (!curr_list) { 828 /* First update or invalid node should directly write in the 829 * hw register */ 830 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n", 831 sti_plane_to_str(plane)); 832 833 writel(gdp->is_curr_top ? 834 dma_updated_btm : dma_updated_top, 835 gdp->regs + GAM_GDP_NVN_OFFSET); 836 goto end; 837 } 838 839 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 840 if (gdp->is_curr_top) { 841 /* Do not update in the middle of the frame, but 842 * postpone the update after the bottom field has 843 * been displayed */ 844 curr_list->btm_field->gam_gdp_nvn = dma_updated_top; 845 } else { 846 /* Direct update to avoid one frame delay */ 847 writel(dma_updated_top, 848 gdp->regs + GAM_GDP_NVN_OFFSET); 849 } 850 } else { 851 /* Direct update for progressive to avoid one frame delay */ 852 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET); 853 } 854 855 end: 856 sti_plane_update_fps(plane, true, false); 857 858 plane->status = STI_PLANE_UPDATED; 859 } 860 861 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane, 862 struct drm_plane_state *oldstate) 863 { 864 struct sti_plane *plane = to_sti_plane(drm_plane); 865 866 if (!oldstate->crtc) { 867 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n", 868 drm_plane->base.id); 869 return; 870 } 871 872 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n", 873 oldstate->crtc->base.id, 874 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)), 875 drm_plane->base.id, sti_plane_to_str(plane)); 876 877 plane->status = STI_PLANE_DISABLING; 878 } 879 880 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = { 881 .atomic_check = sti_gdp_atomic_check, 882 .atomic_update = sti_gdp_atomic_update, 883 .atomic_disable = sti_gdp_atomic_disable, 884 }; 885 886 static void sti_gdp_destroy(struct drm_plane *drm_plane) 887 { 888 DRM_DEBUG_DRIVER("\n"); 889 890 drm_plane_cleanup(drm_plane); 891 } 892 893 static int sti_gdp_late_register(struct drm_plane *drm_plane) 894 { 895 struct sti_plane *plane = to_sti_plane(drm_plane); 896 struct sti_gdp *gdp = to_sti_gdp(plane); 897 898 return gdp_debugfs_init(gdp, drm_plane->dev->primary); 899 } 900 901 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = { 902 .update_plane = drm_atomic_helper_update_plane, 903 .disable_plane = drm_atomic_helper_disable_plane, 904 .destroy = sti_gdp_destroy, 905 .reset = sti_plane_reset, 906 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 907 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 908 .late_register = sti_gdp_late_register, 909 }; 910 911 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev, 912 struct device *dev, int desc, 913 void __iomem *baseaddr, 914 unsigned int possible_crtcs, 915 enum drm_plane_type type) 916 { 917 struct sti_gdp *gdp; 918 int res; 919 920 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL); 921 if (!gdp) { 922 DRM_ERROR("Failed to allocate memory for GDP\n"); 923 return NULL; 924 } 925 926 gdp->dev = dev; 927 gdp->regs = baseaddr; 928 gdp->plane.desc = desc; 929 gdp->plane.status = STI_PLANE_DISABLED; 930 931 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb; 932 933 sti_gdp_init(gdp); 934 935 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane, 936 possible_crtcs, 937 &sti_gdp_plane_helpers_funcs, 938 gdp_supported_formats, 939 ARRAY_SIZE(gdp_supported_formats), 940 NULL, type, NULL); 941 if (res) { 942 DRM_ERROR("Failed to initialize universal plane\n"); 943 goto err; 944 } 945 946 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs); 947 948 sti_plane_init_property(&gdp->plane, type); 949 950 return &gdp->plane.drm_plane; 951 952 err: 953 devm_kfree(dev, gdp); 954 return NULL; 955 } 956