1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/component.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/seq_file.h> 13 14 #include <drm/drm_atomic_helper.h> 15 #include <drm/drm_bridge.h> 16 #include <drm/drm_debugfs.h> 17 #include <drm/drm_device.h> 18 #include <drm/drm_file.h> 19 #include <drm/drm_print.h> 20 #include <drm/drm_probe_helper.h> 21 22 /* HDformatter registers */ 23 #define HDA_ANA_CFG 0x0000 24 #define HDA_ANA_SCALE_CTRL_Y 0x0004 25 #define HDA_ANA_SCALE_CTRL_CB 0x0008 26 #define HDA_ANA_SCALE_CTRL_CR 0x000C 27 #define HDA_ANA_ANC_CTRL 0x0010 28 #define HDA_ANA_SRC_Y_CFG 0x0014 29 #define HDA_COEFF_Y_PH1_TAP123 0x0018 30 #define HDA_COEFF_Y_PH1_TAP456 0x001C 31 #define HDA_COEFF_Y_PH2_TAP123 0x0020 32 #define HDA_COEFF_Y_PH2_TAP456 0x0024 33 #define HDA_COEFF_Y_PH3_TAP123 0x0028 34 #define HDA_COEFF_Y_PH3_TAP456 0x002C 35 #define HDA_COEFF_Y_PH4_TAP123 0x0030 36 #define HDA_COEFF_Y_PH4_TAP456 0x0034 37 #define HDA_ANA_SRC_C_CFG 0x0040 38 #define HDA_COEFF_C_PH1_TAP123 0x0044 39 #define HDA_COEFF_C_PH1_TAP456 0x0048 40 #define HDA_COEFF_C_PH2_TAP123 0x004C 41 #define HDA_COEFF_C_PH2_TAP456 0x0050 42 #define HDA_COEFF_C_PH3_TAP123 0x0054 43 #define HDA_COEFF_C_PH3_TAP456 0x0058 44 #define HDA_COEFF_C_PH4_TAP123 0x005C 45 #define HDA_COEFF_C_PH4_TAP456 0x0060 46 #define HDA_SYNC_AWGI 0x0300 47 48 /* HDA_ANA_CFG */ 49 #define CFG_AWG_ASYNC_EN BIT(0) 50 #define CFG_AWG_ASYNC_HSYNC_MTD BIT(1) 51 #define CFG_AWG_ASYNC_VSYNC_MTD BIT(2) 52 #define CFG_AWG_SYNC_DEL BIT(3) 53 #define CFG_AWG_FLTR_MODE_SHIFT 4 54 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT) 55 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT) 56 #define CFG_AWG_FLTR_MODE_ED (1 << CFG_AWG_FLTR_MODE_SHIFT) 57 #define CFG_AWG_FLTR_MODE_HD (2 << CFG_AWG_FLTR_MODE_SHIFT) 58 #define CFG_SYNC_ON_PBPR_MASK BIT(8) 59 #define CFG_PREFILTER_EN_MASK BIT(9) 60 #define CFG_PBPR_SYNC_OFF_SHIFT 16 61 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT) 62 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */ 63 64 /* Default scaling values */ 65 #define SCALE_CTRL_Y_DFLT 0x00C50256 66 #define SCALE_CTRL_CB_DFLT 0x00DB0249 67 #define SCALE_CTRL_CR_DFLT 0x00DB0249 68 69 /* Video DACs control */ 70 #define DAC_CFG_HD_HZUVW_OFF_MASK BIT(1) 71 72 /* Upsampler values for the alternative 2X Filter */ 73 #define SAMPLER_COEF_NB 8 74 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000 75 static u32 coef_y_alt_2x[] = { 76 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000, 77 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000 78 }; 79 80 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004 81 static u32 coef_c_alt_2x[] = { 82 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000, 83 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000 84 }; 85 86 /* Upsampler values for the 4X Filter */ 87 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005 88 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004 89 static u32 coef_yc_4x[] = { 90 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24, 91 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D 92 }; 93 94 /* AWG instructions for some video modes */ 95 #define AWG_MAX_INST 64 96 97 /* 720p@50 */ 98 static u32 AWGi_720p_50[] = { 99 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 100 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 101 0x00000D8E, 0x00000104, 0x00001804, 0x00000971, 102 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5, 103 0x00000104, 0x00001AE8 104 }; 105 106 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50) 107 108 /* 720p@60 */ 109 static u32 AWGi_720p_60[] = { 110 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA, 111 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B, 112 0x00000C44, 0x00000104, 0x00001804, 0x00000971, 113 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10, 114 0x00000104, 0x00001AE8 115 }; 116 117 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60) 118 119 /* 1080p@30 */ 120 static u32 AWGi_1080p_30[] = { 121 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 122 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 123 0x00000C2A, 0x00000104, 0x00001804, 0x00000971, 124 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF, 125 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B, 126 0x00001C52 127 }; 128 129 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30) 130 131 /* 1080p@25 */ 132 static u32 AWGi_1080p_25[] = { 133 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 134 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 135 0x00000DE2, 0x00000104, 0x00001804, 0x00000971, 136 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51, 137 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B, 138 0x00001C52 139 }; 140 141 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25) 142 143 /* 1080p@24 */ 144 static u32 AWGi_1080p_24[] = { 145 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56, 146 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B, 147 0x00000E50, 0x00000104, 0x00001804, 0x00000971, 148 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76, 149 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B, 150 0x00001C52 151 }; 152 153 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24) 154 155 /* 720x480p@60 */ 156 static u32 AWGi_720x480p_60[] = { 157 0x00000904, 0x00000F18, 0x0000013B, 0x00001805, 158 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06 159 }; 160 161 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60) 162 163 /* Video mode category */ 164 enum sti_hda_vid_cat { 165 VID_SD, 166 VID_ED, 167 VID_HD_74M, 168 VID_HD_148M 169 }; 170 171 struct sti_hda_video_config { 172 struct drm_display_mode mode; 173 u32 *awg_instr; 174 int nb_instr; 175 enum sti_hda_vid_cat vid_cat; 176 }; 177 178 /* HD analog supported modes 179 * Interlaced modes may be added when supported by the whole display chain 180 */ 181 static const struct sti_hda_video_config hda_supported_modes[] = { 182 /* 1080p30 74.250Mhz */ 183 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 184 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 186 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 187 /* 1080p30 74.176Mhz */ 188 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008, 189 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 191 AWGi_1080p_30, NN_1080p_30, VID_HD_74M}, 192 /* 1080p24 74.250Mhz */ 193 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 194 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 196 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 197 /* 1080p24 74.176Mhz */ 198 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558, 199 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 201 AWGi_1080p_24, NN_1080p_24, VID_HD_74M}, 202 /* 1080p25 74.250Mhz */ 203 {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 204 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 206 AWGi_1080p_25, NN_1080p_25, VID_HD_74M}, 207 /* 720p60 74.250Mhz */ 208 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 209 1430, 1650, 0, 720, 725, 730, 750, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 211 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 212 /* 720p60 74.176Mhz */ 213 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390, 214 1430, 1650, 0, 720, 725, 730, 750, 0, 215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 216 AWGi_720p_60, NN_720p_60, VID_HD_74M}, 217 /* 720p50 74.250Mhz */ 218 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 219 1760, 1980, 0, 720, 725, 730, 750, 0, 220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)}, 221 AWGi_720p_50, NN_720p_50, VID_HD_74M}, 222 /* 720x480p60 27.027Mhz */ 223 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736, 224 798, 858, 0, 480, 489, 495, 525, 0, 225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 226 AWGi_720x480p_60, NN_720x480p_60, VID_ED}, 227 /* 720x480p60 27.000Mhz */ 228 {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 229 798, 858, 0, 480, 489, 495, 525, 0, 230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)}, 231 AWGi_720x480p_60, NN_720x480p_60, VID_ED} 232 }; 233 234 /* 235 * STI hd analog structure 236 * 237 * @dev: driver device 238 * @drm_dev: pointer to drm device 239 * @mode: current display mode selected 240 * @regs: HD analog register 241 * @video_dacs_ctrl: video DACS control register 242 * @enabled: true if HD analog is enabled else false 243 */ 244 struct sti_hda { 245 struct device dev; 246 struct drm_device *drm_dev; 247 struct drm_display_mode mode; 248 void __iomem *regs; 249 void __iomem *video_dacs_ctrl; 250 struct clk *clk_pix; 251 struct clk *clk_hddac; 252 bool enabled; 253 }; 254 255 struct sti_hda_connector { 256 struct drm_connector drm_connector; 257 struct drm_encoder *encoder; 258 struct sti_hda *hda; 259 }; 260 261 #define to_sti_hda_connector(x) \ 262 container_of(x, struct sti_hda_connector, drm_connector) 263 264 static u32 hda_read(struct sti_hda *hda, int offset) 265 { 266 return readl(hda->regs + offset); 267 } 268 269 static void hda_write(struct sti_hda *hda, u32 val, int offset) 270 { 271 writel(val, hda->regs + offset); 272 } 273 274 /** 275 * Search for a video mode in the supported modes table 276 * 277 * @mode: mode being searched 278 * @idx: index of the found mode 279 * 280 * Return true if mode is found 281 */ 282 static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx) 283 { 284 unsigned int i; 285 286 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) 287 if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) { 288 *idx = i; 289 return true; 290 } 291 return false; 292 } 293 294 /** 295 * Enable the HD DACS 296 * 297 * @hda: pointer to HD analog structure 298 * @enable: true if HD DACS need to be enabled, else false 299 */ 300 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable) 301 { 302 if (hda->video_dacs_ctrl) { 303 u32 val; 304 305 val = readl(hda->video_dacs_ctrl); 306 if (enable) 307 val &= ~DAC_CFG_HD_HZUVW_OFF_MASK; 308 else 309 val |= DAC_CFG_HD_HZUVW_OFF_MASK; 310 311 writel(val, hda->video_dacs_ctrl); 312 } 313 } 314 315 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \ 316 readl(hda->regs + reg)) 317 318 static void hda_dbg_cfg(struct seq_file *s, int val) 319 { 320 seq_puts(s, "\tAWG "); 321 seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled"); 322 } 323 324 static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg) 325 { 326 unsigned int i; 327 328 seq_puts(s, "\n\n HDA AWG microcode:"); 329 for (i = 0; i < AWG_MAX_INST; i++) { 330 if (i % 8 == 0) 331 seq_printf(s, "\n %04X:", i); 332 seq_printf(s, " %04X", readl(reg + i * 4)); 333 } 334 } 335 336 static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg) 337 { 338 u32 val = readl(reg); 339 340 seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); 341 seq_puts(s, "\tHD DACs "); 342 seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled"); 343 } 344 345 static int hda_dbg_show(struct seq_file *s, void *data) 346 { 347 struct drm_info_node *node = s->private; 348 struct sti_hda *hda = (struct sti_hda *)node->info_ent->data; 349 350 seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs); 351 DBGFS_DUMP(HDA_ANA_CFG); 352 hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG)); 353 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y); 354 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB); 355 DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR); 356 DBGFS_DUMP(HDA_ANA_ANC_CTRL); 357 DBGFS_DUMP(HDA_ANA_SRC_Y_CFG); 358 DBGFS_DUMP(HDA_ANA_SRC_C_CFG); 359 hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI); 360 if (hda->video_dacs_ctrl) 361 hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl); 362 seq_putc(s, '\n'); 363 return 0; 364 } 365 366 static struct drm_info_list hda_debugfs_files[] = { 367 { "hda", hda_dbg_show, 0, NULL }, 368 }; 369 370 static int hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor) 371 { 372 unsigned int i; 373 374 for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++) 375 hda_debugfs_files[i].data = hda; 376 377 return drm_debugfs_create_files(hda_debugfs_files, 378 ARRAY_SIZE(hda_debugfs_files), 379 minor->debugfs_root, minor); 380 } 381 382 /** 383 * Configure AWG, writing instructions 384 * 385 * @hda: pointer to HD analog structure 386 * @awg_instr: pointer to AWG instructions table 387 * @nb: nb of AWG instructions 388 */ 389 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb) 390 { 391 unsigned int i; 392 393 DRM_DEBUG_DRIVER("\n"); 394 395 for (i = 0; i < nb; i++) 396 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4); 397 for (i = nb; i < AWG_MAX_INST; i++) 398 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4); 399 } 400 401 static void sti_hda_disable(struct drm_bridge *bridge) 402 { 403 struct sti_hda *hda = bridge->driver_private; 404 u32 val; 405 406 if (!hda->enabled) 407 return; 408 409 DRM_DEBUG_DRIVER("\n"); 410 411 /* Disable HD DAC and AWG */ 412 val = hda_read(hda, HDA_ANA_CFG); 413 val &= ~CFG_AWG_ASYNC_EN; 414 hda_write(hda, val, HDA_ANA_CFG); 415 hda_write(hda, 0, HDA_ANA_ANC_CTRL); 416 417 hda_enable_hd_dacs(hda, false); 418 419 /* Disable/unprepare hda clock */ 420 clk_disable_unprepare(hda->clk_hddac); 421 clk_disable_unprepare(hda->clk_pix); 422 423 hda->enabled = false; 424 } 425 426 static void sti_hda_pre_enable(struct drm_bridge *bridge) 427 { 428 struct sti_hda *hda = bridge->driver_private; 429 u32 val, i, mode_idx; 430 u32 src_filter_y, src_filter_c; 431 u32 *coef_y, *coef_c; 432 u32 filter_mode; 433 434 DRM_DEBUG_DRIVER("\n"); 435 436 if (hda->enabled) 437 return; 438 439 /* Prepare/enable clocks */ 440 if (clk_prepare_enable(hda->clk_pix)) 441 DRM_ERROR("Failed to prepare/enable hda_pix clk\n"); 442 if (clk_prepare_enable(hda->clk_hddac)) 443 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n"); 444 445 if (!hda_get_mode_idx(hda->mode, &mode_idx)) { 446 DRM_ERROR("Undefined mode\n"); 447 return; 448 } 449 450 switch (hda_supported_modes[mode_idx].vid_cat) { 451 case VID_HD_148M: 452 DRM_ERROR("Beyond HD analog capabilities\n"); 453 return; 454 case VID_HD_74M: 455 /* HD use alternate 2x filter */ 456 filter_mode = CFG_AWG_FLTR_MODE_HD; 457 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X; 458 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X; 459 coef_y = coef_y_alt_2x; 460 coef_c = coef_c_alt_2x; 461 break; 462 case VID_ED: 463 /* ED uses 4x filter */ 464 filter_mode = CFG_AWG_FLTR_MODE_ED; 465 src_filter_y = HDA_ANA_SRC_Y_CFG_4X; 466 src_filter_c = HDA_ANA_SRC_C_CFG_4X; 467 coef_y = coef_yc_4x; 468 coef_c = coef_yc_4x; 469 break; 470 case VID_SD: 471 DRM_ERROR("Not supported\n"); 472 return; 473 default: 474 DRM_ERROR("Undefined resolution\n"); 475 return; 476 } 477 DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx); 478 479 /* Enable HD Video DACs */ 480 hda_enable_hd_dacs(hda, true); 481 482 /* Configure scaler */ 483 hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y); 484 hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB); 485 hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR); 486 487 /* Configure sampler */ 488 hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG); 489 hda_write(hda, src_filter_c, HDA_ANA_SRC_C_CFG); 490 for (i = 0; i < SAMPLER_COEF_NB; i++) { 491 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4); 492 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4); 493 } 494 495 /* Configure main HDFormatter */ 496 val = 0; 497 val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ? 498 0 : CFG_AWG_ASYNC_VSYNC_MTD; 499 val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT); 500 val |= filter_mode; 501 hda_write(hda, val, HDA_ANA_CFG); 502 503 /* Configure AWG */ 504 sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr, 505 hda_supported_modes[mode_idx].nb_instr); 506 507 /* Enable AWG */ 508 val = hda_read(hda, HDA_ANA_CFG); 509 val |= CFG_AWG_ASYNC_EN; 510 hda_write(hda, val, HDA_ANA_CFG); 511 512 hda->enabled = true; 513 } 514 515 static void sti_hda_set_mode(struct drm_bridge *bridge, 516 const struct drm_display_mode *mode, 517 const struct drm_display_mode *adjusted_mode) 518 { 519 struct sti_hda *hda = bridge->driver_private; 520 u32 mode_idx; 521 int hddac_rate; 522 int ret; 523 524 DRM_DEBUG_DRIVER("\n"); 525 526 memcpy(&hda->mode, mode, sizeof(struct drm_display_mode)); 527 528 if (!hda_get_mode_idx(hda->mode, &mode_idx)) { 529 DRM_ERROR("Undefined mode\n"); 530 return; 531 } 532 533 switch (hda_supported_modes[mode_idx].vid_cat) { 534 case VID_HD_74M: 535 /* HD use alternate 2x filter */ 536 hddac_rate = mode->clock * 1000 * 2; 537 break; 538 case VID_ED: 539 /* ED uses 4x filter */ 540 hddac_rate = mode->clock * 1000 * 4; 541 break; 542 default: 543 DRM_ERROR("Undefined mode\n"); 544 return; 545 } 546 547 /* HD DAC = 148.5Mhz or 108 Mhz */ 548 ret = clk_set_rate(hda->clk_hddac, hddac_rate); 549 if (ret < 0) 550 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n", 551 hddac_rate); 552 553 /* HDformatter clock = compositor clock */ 554 ret = clk_set_rate(hda->clk_pix, mode->clock * 1000); 555 if (ret < 0) 556 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n", 557 mode->clock * 1000); 558 } 559 560 static void sti_hda_bridge_nope(struct drm_bridge *bridge) 561 { 562 /* do nothing */ 563 } 564 565 static const struct drm_bridge_funcs sti_hda_bridge_funcs = { 566 .pre_enable = sti_hda_pre_enable, 567 .enable = sti_hda_bridge_nope, 568 .disable = sti_hda_disable, 569 .post_disable = sti_hda_bridge_nope, 570 .mode_set = sti_hda_set_mode, 571 }; 572 573 static int sti_hda_connector_get_modes(struct drm_connector *connector) 574 { 575 unsigned int i; 576 int count = 0; 577 struct sti_hda_connector *hda_connector 578 = to_sti_hda_connector(connector); 579 struct sti_hda *hda = hda_connector->hda; 580 581 DRM_DEBUG_DRIVER("\n"); 582 583 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) { 584 struct drm_display_mode *mode = 585 drm_mode_duplicate(hda->drm_dev, 586 &hda_supported_modes[i].mode); 587 if (!mode) 588 continue; 589 mode->vrefresh = drm_mode_vrefresh(mode); 590 591 /* the first mode is the preferred mode */ 592 if (i == 0) 593 mode->type |= DRM_MODE_TYPE_PREFERRED; 594 595 drm_mode_probed_add(connector, mode); 596 count++; 597 } 598 599 return count; 600 } 601 602 #define CLK_TOLERANCE_HZ 50 603 604 static int sti_hda_connector_mode_valid(struct drm_connector *connector, 605 struct drm_display_mode *mode) 606 { 607 int target = mode->clock * 1000; 608 int target_min = target - CLK_TOLERANCE_HZ; 609 int target_max = target + CLK_TOLERANCE_HZ; 610 int result; 611 int idx; 612 struct sti_hda_connector *hda_connector 613 = to_sti_hda_connector(connector); 614 struct sti_hda *hda = hda_connector->hda; 615 616 if (!hda_get_mode_idx(*mode, &idx)) { 617 return MODE_BAD; 618 } else { 619 result = clk_round_rate(hda->clk_pix, target); 620 621 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", 622 target, result); 623 624 if ((result < target_min) || (result > target_max)) { 625 DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n", 626 target); 627 return MODE_BAD; 628 } 629 } 630 631 return MODE_OK; 632 } 633 634 static const 635 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = { 636 .get_modes = sti_hda_connector_get_modes, 637 .mode_valid = sti_hda_connector_mode_valid, 638 }; 639 640 static int sti_hda_late_register(struct drm_connector *connector) 641 { 642 struct sti_hda_connector *hda_connector 643 = to_sti_hda_connector(connector); 644 struct sti_hda *hda = hda_connector->hda; 645 646 if (hda_debugfs_init(hda, hda->drm_dev->primary)) { 647 DRM_ERROR("HDA debugfs setup failed\n"); 648 return -EINVAL; 649 } 650 651 return 0; 652 } 653 654 static const struct drm_connector_funcs sti_hda_connector_funcs = { 655 .fill_modes = drm_helper_probe_single_connector_modes, 656 .destroy = drm_connector_cleanup, 657 .reset = drm_atomic_helper_connector_reset, 658 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 659 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 660 .late_register = sti_hda_late_register, 661 }; 662 663 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev) 664 { 665 struct drm_encoder *encoder; 666 667 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 668 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC) 669 return encoder; 670 } 671 672 return NULL; 673 } 674 675 static int sti_hda_bind(struct device *dev, struct device *master, void *data) 676 { 677 struct sti_hda *hda = dev_get_drvdata(dev); 678 struct drm_device *drm_dev = data; 679 struct drm_encoder *encoder; 680 struct sti_hda_connector *connector; 681 struct drm_connector *drm_connector; 682 struct drm_bridge *bridge; 683 int err; 684 685 /* Set the drm device handle */ 686 hda->drm_dev = drm_dev; 687 688 encoder = sti_hda_find_encoder(drm_dev); 689 if (!encoder) 690 return -ENOMEM; 691 692 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); 693 if (!connector) 694 return -ENOMEM; 695 696 connector->hda = hda; 697 698 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); 699 if (!bridge) 700 return -ENOMEM; 701 702 bridge->driver_private = hda; 703 bridge->funcs = &sti_hda_bridge_funcs; 704 drm_bridge_attach(encoder, bridge, NULL); 705 706 connector->encoder = encoder; 707 708 drm_connector = (struct drm_connector *)connector; 709 710 drm_connector->polled = DRM_CONNECTOR_POLL_HPD; 711 712 drm_connector_init(drm_dev, drm_connector, 713 &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component); 714 drm_connector_helper_add(drm_connector, 715 &sti_hda_connector_helper_funcs); 716 717 err = drm_connector_attach_encoder(drm_connector, encoder); 718 if (err) { 719 DRM_ERROR("Failed to attach a connector to a encoder\n"); 720 goto err_sysfs; 721 } 722 723 /* force to disable hd dacs at startup */ 724 hda_enable_hd_dacs(hda, false); 725 726 return 0; 727 728 err_sysfs: 729 return -EINVAL; 730 } 731 732 static void sti_hda_unbind(struct device *dev, 733 struct device *master, void *data) 734 { 735 } 736 737 static const struct component_ops sti_hda_ops = { 738 .bind = sti_hda_bind, 739 .unbind = sti_hda_unbind, 740 }; 741 742 static int sti_hda_probe(struct platform_device *pdev) 743 { 744 struct device *dev = &pdev->dev; 745 struct sti_hda *hda; 746 struct resource *res; 747 748 DRM_INFO("%s\n", __func__); 749 750 hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL); 751 if (!hda) 752 return -ENOMEM; 753 754 hda->dev = pdev->dev; 755 756 /* Get resources */ 757 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg"); 758 if (!res) { 759 DRM_ERROR("Invalid hda resource\n"); 760 return -ENOMEM; 761 } 762 hda->regs = devm_ioremap(dev, res->start, resource_size(res)); 763 if (!hda->regs) 764 return -ENOMEM; 765 766 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 767 "video-dacs-ctrl"); 768 if (res) { 769 hda->video_dacs_ctrl = devm_ioremap(dev, res->start, 770 resource_size(res)); 771 if (!hda->video_dacs_ctrl) 772 return -ENOMEM; 773 } else { 774 /* If no existing video-dacs-ctrl resource continue the probe */ 775 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n"); 776 hda->video_dacs_ctrl = NULL; 777 } 778 779 /* Get clock resources */ 780 hda->clk_pix = devm_clk_get(dev, "pix"); 781 if (IS_ERR(hda->clk_pix)) { 782 DRM_ERROR("Cannot get hda_pix clock\n"); 783 return PTR_ERR(hda->clk_pix); 784 } 785 786 hda->clk_hddac = devm_clk_get(dev, "hddac"); 787 if (IS_ERR(hda->clk_hddac)) { 788 DRM_ERROR("Cannot get hda_hddac clock\n"); 789 return PTR_ERR(hda->clk_hddac); 790 } 791 792 platform_set_drvdata(pdev, hda); 793 794 return component_add(&pdev->dev, &sti_hda_ops); 795 } 796 797 static int sti_hda_remove(struct platform_device *pdev) 798 { 799 component_del(&pdev->dev, &sti_hda_ops); 800 return 0; 801 } 802 803 static const struct of_device_id hda_of_match[] = { 804 { .compatible = "st,stih416-hda", }, 805 { .compatible = "st,stih407-hda", }, 806 { /* end node */ } 807 }; 808 MODULE_DEVICE_TABLE(of, hda_of_match); 809 810 struct platform_driver sti_hda_driver = { 811 .driver = { 812 .name = "sti-hda", 813 .owner = THIS_MODULE, 814 .of_match_table = hda_of_match, 815 }, 816 .probe = sti_hda_probe, 817 .remove = sti_hda_remove, 818 }; 819 820 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 821 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 822 MODULE_LICENSE("GPL"); 823