1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regulator/consumer.h> 15 16 #include <video/mipi_display.h> 17 18 #include <drm/bridge/dw_mipi_dsi.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_print.h> 21 22 #define HWVER_130 0x31333000 /* IP version 1.30 */ 23 #define HWVER_131 0x31333100 /* IP version 1.31 */ 24 25 /* DSI digital registers & bit definitions */ 26 #define DSI_VERSION 0x00 27 #define VERSION GENMASK(31, 8) 28 29 /* DSI wrapper registers & bit definitions */ 30 /* Note: registers are named as in the Reference Manual */ 31 #define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */ 32 #define WCFGR_DSIM BIT(0) /* DSI Mode */ 33 #define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */ 34 35 #define DSI_WCR 0x0404 /* Wrapper Control Reg */ 36 #define WCR_DSIEN BIT(3) /* DSI ENable */ 37 38 #define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */ 39 #define WISR_PLLLS BIT(8) /* PLL Lock Status */ 40 #define WISR_RRS BIT(12) /* Regulator Ready Status */ 41 42 #define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */ 43 #define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */ 44 #define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ 45 46 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */ 47 #define WRPCR_PLLEN BIT(0) /* PLL ENable */ 48 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */ 49 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */ 50 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */ 51 #define WRPCR_REGEN BIT(24) /* REGulator ENable */ 52 #define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ 53 #define IDF_MIN 1 54 #define IDF_MAX 7 55 #define NDIV_MIN 10 56 #define NDIV_MAX 125 57 #define ODF_MIN 1 58 #define ODF_MAX 8 59 60 /* dsi color format coding according to the datasheet */ 61 enum dsi_color { 62 DSI_RGB565_CONF1, 63 DSI_RGB565_CONF2, 64 DSI_RGB565_CONF3, 65 DSI_RGB666_CONF1, 66 DSI_RGB666_CONF2, 67 DSI_RGB888, 68 }; 69 70 #define LANE_MIN_KBPS 31250 71 #define LANE_MAX_KBPS 500000 72 73 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */ 74 #define SLEEP_US 1000 75 #define TIMEOUT_US 200000 76 77 struct dw_mipi_dsi_stm { 78 void __iomem *base; 79 struct clk *pllref_clk; 80 struct dw_mipi_dsi *dsi; 81 u32 hw_version; 82 int lane_min_kbps; 83 int lane_max_kbps; 84 struct regulator *vdd_supply; 85 }; 86 87 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) 88 { 89 writel(val, dsi->base + reg); 90 } 91 92 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) 93 { 94 return readl(dsi->base + reg); 95 } 96 97 static inline void dsi_set(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 98 { 99 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 100 } 101 102 static inline void dsi_clear(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 mask) 103 { 104 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); 105 } 106 107 static inline void dsi_update_bits(struct dw_mipi_dsi_stm *dsi, u32 reg, 108 u32 mask, u32 val) 109 { 110 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 111 } 112 113 static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt) 114 { 115 switch (fmt) { 116 case MIPI_DSI_FMT_RGB888: 117 return DSI_RGB888; 118 case MIPI_DSI_FMT_RGB666: 119 return DSI_RGB666_CONF2; 120 case MIPI_DSI_FMT_RGB666_PACKED: 121 return DSI_RGB666_CONF1; 122 case MIPI_DSI_FMT_RGB565: 123 return DSI_RGB565_CONF1; 124 default: 125 DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n"); 126 } 127 return DSI_RGB888; 128 } 129 130 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) 131 { 132 int divisor = idf * odf; 133 134 /* prevent from division by 0 */ 135 if (!divisor) 136 return 0; 137 138 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); 139 } 140 141 static int dsi_pll_get_params(struct dw_mipi_dsi_stm *dsi, 142 int clkin_khz, int clkout_khz, 143 int *idf, int *ndiv, int *odf) 144 { 145 int i, o, n, n_min, n_max; 146 int fvco_min, fvco_max, delta, best_delta; /* all in khz */ 147 148 /* Early checks preventing division by 0 & odd results */ 149 if (clkin_khz <= 0 || clkout_khz <= 0) 150 return -EINVAL; 151 152 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX; 153 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN; 154 155 best_delta = 1000000; /* big started value (1000000khz) */ 156 157 for (i = IDF_MIN; i <= IDF_MAX; i++) { 158 /* Compute ndiv range according to Fvco */ 159 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1; 160 n_max = (fvco_max * i) / (2 * clkin_khz); 161 162 /* No need to continue idf loop if we reach ndiv max */ 163 if (n_min >= NDIV_MAX) 164 break; 165 166 /* Clamp ndiv to valid values */ 167 if (n_min < NDIV_MIN) 168 n_min = NDIV_MIN; 169 if (n_max > NDIV_MAX) 170 n_max = NDIV_MAX; 171 172 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) { 173 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz); 174 /* Check ndiv according to vco range */ 175 if (n < n_min || n > n_max) 176 continue; 177 /* Check if new delta is better & saves parameters */ 178 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - 179 clkout_khz; 180 if (delta < 0) 181 delta = -delta; 182 if (delta < best_delta) { 183 *idf = i; 184 *ndiv = n; 185 *odf = o; 186 best_delta = delta; 187 } 188 /* fast return in case of "perfect result" */ 189 if (!delta) 190 return 0; 191 } 192 } 193 194 return 0; 195 } 196 197 static int dw_mipi_dsi_phy_init(void *priv_data) 198 { 199 struct dw_mipi_dsi_stm *dsi = priv_data; 200 u32 val; 201 int ret; 202 203 /* Enable the regulator */ 204 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); 205 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, 206 SLEEP_US, TIMEOUT_US); 207 if (ret) 208 DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n"); 209 210 /* Enable the DSI PLL & wait for its lock */ 211 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); 212 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, 213 SLEEP_US, TIMEOUT_US); 214 if (ret) 215 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n"); 216 217 return 0; 218 } 219 220 static void dw_mipi_dsi_phy_power_on(void *priv_data) 221 { 222 struct dw_mipi_dsi_stm *dsi = priv_data; 223 224 DRM_DEBUG_DRIVER("\n"); 225 226 /* Enable the DSI wrapper */ 227 dsi_set(dsi, DSI_WCR, WCR_DSIEN); 228 } 229 230 static void dw_mipi_dsi_phy_power_off(void *priv_data) 231 { 232 struct dw_mipi_dsi_stm *dsi = priv_data; 233 234 DRM_DEBUG_DRIVER("\n"); 235 236 /* Disable the DSI wrapper */ 237 dsi_clear(dsi, DSI_WCR, WCR_DSIEN); 238 } 239 240 static int 241 dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 242 unsigned long mode_flags, u32 lanes, u32 format, 243 unsigned int *lane_mbps) 244 { 245 struct dw_mipi_dsi_stm *dsi = priv_data; 246 unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; 247 int ret, bpp; 248 u32 val; 249 250 /* Update lane capabilities according to hw version */ 251 dsi->lane_min_kbps = LANE_MIN_KBPS; 252 dsi->lane_max_kbps = LANE_MAX_KBPS; 253 if (dsi->hw_version == HWVER_131) { 254 dsi->lane_min_kbps *= 2; 255 dsi->lane_max_kbps *= 2; 256 } 257 258 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000); 259 260 /* Compute requested pll out */ 261 bpp = mipi_dsi_pixel_format_to_bpp(format); 262 pll_out_khz = mode->clock * bpp / lanes; 263 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ 264 pll_out_khz = (pll_out_khz * 12) / 10; 265 if (pll_out_khz > dsi->lane_max_kbps) { 266 pll_out_khz = dsi->lane_max_kbps; 267 DRM_WARN("Warning max phy mbps is used\n"); 268 } 269 if (pll_out_khz < dsi->lane_min_kbps) { 270 pll_out_khz = dsi->lane_min_kbps; 271 DRM_WARN("Warning min phy mbps is used\n"); 272 } 273 274 /* Compute best pll parameters */ 275 idf = 0; 276 ndiv = 0; 277 odf = 0; 278 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, 279 &idf, &ndiv, &odf); 280 if (ret) 281 DRM_WARN("Warning dsi_pll_get_params(): bad params\n"); 282 283 /* Get the adjusted pll out value */ 284 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); 285 286 /* Set the PLL division factors */ 287 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, 288 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); 289 290 /* Compute uix4 & set the bit period in high-speed mode */ 291 val = 4000000 / pll_out_khz; 292 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); 293 294 /* Select video mode by resetting DSIM bit */ 295 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); 296 297 /* Select the color coding */ 298 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, 299 dsi_color_from_mipi(format) << 1); 300 301 *lane_mbps = pll_out_khz / 1000; 302 303 DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 304 pll_in_khz, pll_out_khz, *lane_mbps); 305 306 return 0; 307 } 308 309 static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_stm_phy_ops = { 310 .init = dw_mipi_dsi_phy_init, 311 .power_on = dw_mipi_dsi_phy_power_on, 312 .power_off = dw_mipi_dsi_phy_power_off, 313 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 314 }; 315 316 static struct dw_mipi_dsi_plat_data dw_mipi_dsi_stm_plat_data = { 317 .max_data_lanes = 2, 318 .phy_ops = &dw_mipi_dsi_stm_phy_ops, 319 }; 320 321 static const struct of_device_id dw_mipi_dsi_stm_dt_ids[] = { 322 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, }, 323 { }, 324 }; 325 MODULE_DEVICE_TABLE(of, dw_mipi_dsi_stm_dt_ids); 326 327 static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) 328 { 329 struct device *dev = &pdev->dev; 330 struct dw_mipi_dsi_stm *dsi; 331 struct clk *pclk; 332 struct resource *res; 333 int ret; 334 335 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 336 if (!dsi) 337 return -ENOMEM; 338 339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 340 dsi->base = devm_ioremap_resource(dev, res); 341 if (IS_ERR(dsi->base)) { 342 ret = PTR_ERR(dsi->base); 343 DRM_ERROR("Unable to get dsi registers %d\n", ret); 344 return ret; 345 } 346 347 dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi"); 348 if (IS_ERR(dsi->vdd_supply)) { 349 ret = PTR_ERR(dsi->vdd_supply); 350 if (ret != -EPROBE_DEFER) 351 DRM_ERROR("Failed to request regulator: %d\n", ret); 352 return ret; 353 } 354 355 ret = regulator_enable(dsi->vdd_supply); 356 if (ret) { 357 DRM_ERROR("Failed to enable regulator: %d\n", ret); 358 return ret; 359 } 360 361 dsi->pllref_clk = devm_clk_get(dev, "ref"); 362 if (IS_ERR(dsi->pllref_clk)) { 363 ret = PTR_ERR(dsi->pllref_clk); 364 DRM_ERROR("Unable to get pll reference clock: %d\n", ret); 365 goto err_clk_get; 366 } 367 368 ret = clk_prepare_enable(dsi->pllref_clk); 369 if (ret) { 370 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret); 371 goto err_clk_get; 372 } 373 374 pclk = devm_clk_get(dev, "pclk"); 375 if (IS_ERR(pclk)) { 376 ret = PTR_ERR(pclk); 377 DRM_ERROR("Unable to get peripheral clock: %d\n", ret); 378 goto err_dsi_probe; 379 } 380 381 ret = clk_prepare_enable(pclk); 382 if (ret) { 383 DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__); 384 goto err_dsi_probe; 385 } 386 387 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 388 clk_disable_unprepare(pclk); 389 390 if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) { 391 ret = -ENODEV; 392 DRM_ERROR("bad dsi hardware version\n"); 393 goto err_dsi_probe; 394 } 395 396 dw_mipi_dsi_stm_plat_data.base = dsi->base; 397 dw_mipi_dsi_stm_plat_data.priv_data = dsi; 398 399 platform_set_drvdata(pdev, dsi); 400 401 dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); 402 if (IS_ERR(dsi->dsi)) { 403 ret = PTR_ERR(dsi->dsi); 404 DRM_ERROR("Failed to initialize mipi dsi host: %d\n", ret); 405 goto err_dsi_probe; 406 } 407 408 return 0; 409 410 err_dsi_probe: 411 clk_disable_unprepare(dsi->pllref_clk); 412 err_clk_get: 413 regulator_disable(dsi->vdd_supply); 414 415 return ret; 416 } 417 418 static int dw_mipi_dsi_stm_remove(struct platform_device *pdev) 419 { 420 struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev); 421 422 dw_mipi_dsi_remove(dsi->dsi); 423 clk_disable_unprepare(dsi->pllref_clk); 424 regulator_disable(dsi->vdd_supply); 425 426 return 0; 427 } 428 429 static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev) 430 { 431 struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 432 433 DRM_DEBUG_DRIVER("\n"); 434 435 clk_disable_unprepare(dsi->pllref_clk); 436 regulator_disable(dsi->vdd_supply); 437 438 return 0; 439 } 440 441 static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev) 442 { 443 struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; 444 int ret; 445 446 DRM_DEBUG_DRIVER("\n"); 447 448 ret = regulator_enable(dsi->vdd_supply); 449 if (ret) { 450 DRM_ERROR("Failed to enable regulator: %d\n", ret); 451 return ret; 452 } 453 454 ret = clk_prepare_enable(dsi->pllref_clk); 455 if (ret) { 456 regulator_disable(dsi->vdd_supply); 457 DRM_ERROR("Failed to enable pllref_clk: %d\n", ret); 458 return ret; 459 } 460 461 return 0; 462 } 463 464 static const struct dev_pm_ops dw_mipi_dsi_stm_pm_ops = { 465 SET_SYSTEM_SLEEP_PM_OPS(dw_mipi_dsi_stm_suspend, 466 dw_mipi_dsi_stm_resume) 467 }; 468 469 static struct platform_driver dw_mipi_dsi_stm_driver = { 470 .probe = dw_mipi_dsi_stm_probe, 471 .remove = dw_mipi_dsi_stm_remove, 472 .driver = { 473 .of_match_table = dw_mipi_dsi_stm_dt_ids, 474 .name = "stm32-display-dsi", 475 .pm = &dw_mipi_dsi_stm_pm_ops, 476 }, 477 }; 478 479 module_platform_driver(dw_mipi_dsi_stm_driver); 480 481 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 482 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 483 MODULE_DESCRIPTION("STMicroelectronics DW MIPI DSI host controller driver"); 484 MODULE_LICENSE("GPL v2"); 485