1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/dma-mapping.h> 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/cc_platform.h> 32 33 #include <drm/drm_aperture.h> 34 #include <drm/drm_drv.h> 35 #include <drm/drm_gem_ttm_helper.h> 36 #include <drm/drm_ioctl.h> 37 #include <drm/drm_module.h> 38 #include <drm/drm_sysfs.h> 39 #include <drm/ttm/ttm_bo_driver.h> 40 #include <drm/ttm/ttm_range_manager.h> 41 #include <drm/ttm/ttm_placement.h> 42 #include <generated/utsrelease.h> 43 44 #include "ttm_object.h" 45 #include "vmwgfx_binding.h" 46 #include "vmwgfx_devcaps.h" 47 #include "vmwgfx_drv.h" 48 #include "vmwgfx_mksstat.h" 49 50 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 51 52 #define VMW_MIN_INITIAL_WIDTH 800 53 #define VMW_MIN_INITIAL_HEIGHT 600 54 55 /* 56 * Fully encoded drm commands. Might move to vmw_drm.h 57 */ 58 59 #define DRM_IOCTL_VMW_GET_PARAM \ 60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 61 struct drm_vmw_getparam_arg) 62 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 64 union drm_vmw_alloc_dmabuf_arg) 65 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 67 struct drm_vmw_unref_dmabuf_arg) 68 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 70 struct drm_vmw_cursor_bypass_arg) 71 72 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 74 struct drm_vmw_control_stream_arg) 75 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 77 struct drm_vmw_stream_arg) 78 #define DRM_IOCTL_VMW_UNREF_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 80 struct drm_vmw_stream_arg) 81 82 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 84 struct drm_vmw_context_arg) 85 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 87 struct drm_vmw_context_arg) 88 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 90 union drm_vmw_surface_create_arg) 91 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 93 struct drm_vmw_surface_arg) 94 #define DRM_IOCTL_VMW_REF_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 96 union drm_vmw_surface_reference_arg) 97 #define DRM_IOCTL_VMW_EXECBUF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 99 struct drm_vmw_execbuf_arg) 100 #define DRM_IOCTL_VMW_GET_3D_CAP \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 102 struct drm_vmw_get_3d_cap_arg) 103 #define DRM_IOCTL_VMW_FENCE_WAIT \ 104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 105 struct drm_vmw_fence_wait_arg) 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 108 struct drm_vmw_fence_signaled_arg) 109 #define DRM_IOCTL_VMW_FENCE_UNREF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 111 struct drm_vmw_fence_arg) 112 #define DRM_IOCTL_VMW_FENCE_EVENT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 114 struct drm_vmw_fence_event_arg) 115 #define DRM_IOCTL_VMW_PRESENT \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 117 struct drm_vmw_present_arg) 118 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 120 struct drm_vmw_present_readback_arg) 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 123 struct drm_vmw_update_layout_arg) 124 #define DRM_IOCTL_VMW_CREATE_SHADER \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 126 struct drm_vmw_shader_create_arg) 127 #define DRM_IOCTL_VMW_UNREF_SHADER \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 129 struct drm_vmw_shader_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 132 union drm_vmw_gb_surface_create_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 135 union drm_vmw_gb_surface_reference_arg) 136 #define DRM_IOCTL_VMW_SYNCCPU \ 137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 138 struct drm_vmw_synccpu_arg) 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 141 struct drm_vmw_context_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 144 union drm_vmw_gb_surface_create_ext_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 147 union drm_vmw_gb_surface_reference_ext_arg) 148 #define DRM_IOCTL_VMW_MSG \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 150 struct drm_vmw_msg_arg) 151 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 152 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 153 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 155 struct drm_vmw_mksstat_add_arg) 156 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 157 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 158 struct drm_vmw_mksstat_remove_arg) 159 160 /* 161 * Ioctl definitions. 162 */ 163 164 static const struct drm_ioctl_desc vmw_ioctls[] = { 165 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 166 DRM_RENDER_ALLOW), 167 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 168 DRM_RENDER_ALLOW), 169 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 170 DRM_RENDER_ALLOW), 171 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 172 vmw_kms_cursor_bypass_ioctl, 173 DRM_MASTER), 174 175 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 176 DRM_MASTER), 177 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 178 DRM_MASTER), 179 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 180 DRM_MASTER), 181 182 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 183 DRM_RENDER_ALLOW), 184 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 185 DRM_RENDER_ALLOW), 186 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 187 DRM_RENDER_ALLOW), 188 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 189 DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 191 DRM_RENDER_ALLOW), 192 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 193 DRM_RENDER_ALLOW), 194 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 195 DRM_RENDER_ALLOW), 196 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 197 vmw_fence_obj_signaled_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 200 DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 202 DRM_RENDER_ALLOW), 203 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 204 DRM_RENDER_ALLOW), 205 206 /* these allow direct access to the framebuffers mark as master only */ 207 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 208 DRM_MASTER | DRM_AUTH), 209 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 210 vmw_present_readback_ioctl, 211 DRM_MASTER | DRM_AUTH), 212 /* 213 * The permissions of the below ioctl are overridden in 214 * vmw_generic_ioctl(). We require either 215 * DRM_MASTER or capable(CAP_SYS_ADMIN). 216 */ 217 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 218 vmw_kms_update_layout_ioctl, 219 DRM_RENDER_ALLOW), 220 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 221 vmw_shader_define_ioctl, 222 DRM_RENDER_ALLOW), 223 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 224 vmw_shader_destroy_ioctl, 225 DRM_RENDER_ALLOW), 226 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 227 vmw_gb_surface_define_ioctl, 228 DRM_RENDER_ALLOW), 229 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 230 vmw_gb_surface_reference_ioctl, 231 DRM_RENDER_ALLOW), 232 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 233 vmw_user_bo_synccpu_ioctl, 234 DRM_RENDER_ALLOW), 235 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 236 vmw_extended_context_define_ioctl, 237 DRM_RENDER_ALLOW), 238 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 239 vmw_gb_surface_define_ext_ioctl, 240 DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 242 vmw_gb_surface_reference_ext_ioctl, 243 DRM_RENDER_ALLOW), 244 DRM_IOCTL_DEF_DRV(VMW_MSG, 245 vmw_msg_ioctl, 246 DRM_RENDER_ALLOW), 247 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 248 vmw_mksstat_reset_ioctl, 249 DRM_RENDER_ALLOW), 250 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 251 vmw_mksstat_add_ioctl, 252 DRM_RENDER_ALLOW), 253 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 254 vmw_mksstat_remove_ioctl, 255 DRM_RENDER_ALLOW), 256 }; 257 258 static const struct pci_device_id vmw_pci_id_list[] = { 259 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 260 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 261 { } 262 }; 263 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 264 265 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 266 static int vmw_restrict_iommu; 267 static int vmw_force_coherent; 268 static int vmw_restrict_dma_mask; 269 static int vmw_assume_16bpp; 270 271 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 272 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 273 void *ptr); 274 275 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 276 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 277 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 278 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 279 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 280 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 281 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 282 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 283 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 284 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 285 286 287 struct bitmap_name { 288 uint32 value; 289 const char *name; 290 }; 291 292 static const struct bitmap_name cap1_names[] = { 293 { SVGA_CAP_RECT_COPY, "rect copy" }, 294 { SVGA_CAP_CURSOR, "cursor" }, 295 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 296 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 297 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 298 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 299 { SVGA_CAP_3D, "3D" }, 300 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 301 { SVGA_CAP_MULTIMON, "multimon" }, 302 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 303 { SVGA_CAP_IRQMASK, "irq mask" }, 304 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 305 { SVGA_CAP_GMR, "gmr" }, 306 { SVGA_CAP_TRACES, "traces" }, 307 { SVGA_CAP_GMR2, "gmr2" }, 308 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 309 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 310 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 311 { SVGA_CAP_GBOBJECTS, "gbobject" }, 312 { SVGA_CAP_DX, "dx" }, 313 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 314 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 315 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 316 }; 317 318 319 static const struct bitmap_name cap2_names[] = { 320 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 321 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 322 { SVGA_CAP2_DX2, "dx2" }, 323 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 324 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 325 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 326 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 327 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 328 { SVGA_CAP2_MSHINT, "mshint" }, 329 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 330 { SVGA_CAP2_DX3, "dx3" }, 331 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 332 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 333 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 334 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 335 { SVGA_CAP2_LO_STAGING, "lo staging" }, 336 }; 337 338 static void vmw_print_bitmap(struct drm_device *drm, 339 const char *prefix, uint32_t bitmap, 340 const struct bitmap_name *bnames, 341 uint32_t num_names) 342 { 343 char buf[512]; 344 uint32_t i; 345 uint32_t offset = 0; 346 for (i = 0; i < num_names; ++i) { 347 if ((bitmap & bnames[i].value) != 0) { 348 offset += snprintf(buf + offset, 349 ARRAY_SIZE(buf) - offset, 350 "%s, ", bnames[i].name); 351 bitmap &= ~bnames[i].value; 352 } 353 } 354 355 drm_info(drm, "%s: %s\n", prefix, buf); 356 if (bitmap != 0) 357 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 358 } 359 360 361 static void vmw_print_sm_type(struct vmw_private *dev_priv) 362 { 363 static const char *names[] = { 364 [VMW_SM_LEGACY] = "Legacy", 365 [VMW_SM_4] = "SM4", 366 [VMW_SM_4_1] = "SM4_1", 367 [VMW_SM_5] = "SM_5", 368 [VMW_SM_5_1X] = "SM_5_1X", 369 [VMW_SM_MAX] = "Invalid" 370 }; 371 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 372 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 373 names[dev_priv->sm_type]); 374 } 375 376 /** 377 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 378 * 379 * @dev_priv: A device private structure. 380 * 381 * This function creates a small buffer object that holds the query 382 * result for dummy queries emitted as query barriers. 383 * The function will then map the first page and initialize a pending 384 * occlusion query result structure, Finally it will unmap the buffer. 385 * No interruptible waits are done within this function. 386 * 387 * Returns an error if bo creation or initialization fails. 388 */ 389 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 390 { 391 int ret; 392 struct vmw_buffer_object *vbo; 393 struct ttm_bo_kmap_obj map; 394 volatile SVGA3dQueryResult *result; 395 bool dummy; 396 397 /* 398 * Create the vbo as pinned, so that a tryreserve will 399 * immediately succeed. This is because we're the only 400 * user of the bo currently. 401 */ 402 ret = vmw_bo_create(dev_priv, PAGE_SIZE, 403 &vmw_sys_placement, false, true, 404 &vmw_bo_bo_free, &vbo); 405 if (unlikely(ret != 0)) 406 return ret; 407 408 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 409 BUG_ON(ret != 0); 410 vmw_bo_pin_reserved(vbo, true); 411 412 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 413 if (likely(ret == 0)) { 414 result = ttm_kmap_obj_virtual(&map, &dummy); 415 result->totalSize = sizeof(*result); 416 result->state = SVGA3D_QUERYSTATE_PENDING; 417 result->result32 = 0xff; 418 ttm_bo_kunmap(&map); 419 } 420 vmw_bo_pin_reserved(vbo, false); 421 ttm_bo_unreserve(&vbo->base); 422 423 if (unlikely(ret != 0)) { 424 DRM_ERROR("Dummy query buffer map failed.\n"); 425 vmw_bo_unreference(&vbo); 426 } else 427 dev_priv->dummy_query_bo = vbo; 428 429 return ret; 430 } 431 432 static int vmw_device_init(struct vmw_private *dev_priv) 433 { 434 bool uses_fb_traces = false; 435 436 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 437 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 438 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 439 440 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 441 SVGA_REG_ENABLE_HIDE); 442 443 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 444 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 445 446 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 447 dev_priv->fifo = vmw_fifo_create(dev_priv); 448 if (IS_ERR(dev_priv->fifo)) { 449 int err = PTR_ERR(dev_priv->fifo); 450 dev_priv->fifo = NULL; 451 return err; 452 } else if (!dev_priv->fifo) { 453 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 454 } 455 456 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 457 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 458 return 0; 459 } 460 461 static void vmw_device_fini(struct vmw_private *vmw) 462 { 463 /* 464 * Legacy sync 465 */ 466 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 467 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 468 ; 469 470 vmw->last_read_seqno = vmw_fence_read(vmw); 471 472 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 473 vmw->config_done_state); 474 vmw_write(vmw, SVGA_REG_ENABLE, 475 vmw->enable_state); 476 vmw_write(vmw, SVGA_REG_TRACES, 477 vmw->traces_state); 478 479 vmw_fifo_destroy(vmw); 480 } 481 482 /** 483 * vmw_request_device_late - Perform late device setup 484 * 485 * @dev_priv: Pointer to device private. 486 * 487 * This function performs setup of otables and enables large command 488 * buffer submission. These tasks are split out to a separate function 489 * because it reverts vmw_release_device_early and is intended to be used 490 * by an error path in the hibernation code. 491 */ 492 static int vmw_request_device_late(struct vmw_private *dev_priv) 493 { 494 int ret; 495 496 if (dev_priv->has_mob) { 497 ret = vmw_otables_setup(dev_priv); 498 if (unlikely(ret != 0)) { 499 DRM_ERROR("Unable to initialize " 500 "guest Memory OBjects.\n"); 501 return ret; 502 } 503 } 504 505 if (dev_priv->cman) { 506 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 507 if (ret) { 508 struct vmw_cmdbuf_man *man = dev_priv->cman; 509 510 dev_priv->cman = NULL; 511 vmw_cmdbuf_man_destroy(man); 512 } 513 } 514 515 return 0; 516 } 517 518 static int vmw_request_device(struct vmw_private *dev_priv) 519 { 520 int ret; 521 522 ret = vmw_device_init(dev_priv); 523 if (unlikely(ret != 0)) { 524 DRM_ERROR("Unable to initialize the device.\n"); 525 return ret; 526 } 527 vmw_fence_fifo_up(dev_priv->fman); 528 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 529 if (IS_ERR(dev_priv->cman)) { 530 dev_priv->cman = NULL; 531 dev_priv->sm_type = VMW_SM_LEGACY; 532 } 533 534 ret = vmw_request_device_late(dev_priv); 535 if (ret) 536 goto out_no_mob; 537 538 ret = vmw_dummy_query_bo_create(dev_priv); 539 if (unlikely(ret != 0)) 540 goto out_no_query_bo; 541 542 return 0; 543 544 out_no_query_bo: 545 if (dev_priv->cman) 546 vmw_cmdbuf_remove_pool(dev_priv->cman); 547 if (dev_priv->has_mob) { 548 struct ttm_resource_manager *man; 549 550 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 551 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 552 vmw_otables_takedown(dev_priv); 553 } 554 if (dev_priv->cman) 555 vmw_cmdbuf_man_destroy(dev_priv->cman); 556 out_no_mob: 557 vmw_fence_fifo_down(dev_priv->fman); 558 vmw_device_fini(dev_priv); 559 return ret; 560 } 561 562 /** 563 * vmw_release_device_early - Early part of fifo takedown. 564 * 565 * @dev_priv: Pointer to device private struct. 566 * 567 * This is the first part of command submission takedown, to be called before 568 * buffer management is taken down. 569 */ 570 static void vmw_release_device_early(struct vmw_private *dev_priv) 571 { 572 /* 573 * Previous destructions should've released 574 * the pinned bo. 575 */ 576 577 BUG_ON(dev_priv->pinned_bo != NULL); 578 579 vmw_bo_unreference(&dev_priv->dummy_query_bo); 580 if (dev_priv->cman) 581 vmw_cmdbuf_remove_pool(dev_priv->cman); 582 583 if (dev_priv->has_mob) { 584 struct ttm_resource_manager *man; 585 586 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 587 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 588 vmw_otables_takedown(dev_priv); 589 } 590 } 591 592 /** 593 * vmw_release_device_late - Late part of fifo takedown. 594 * 595 * @dev_priv: Pointer to device private struct. 596 * 597 * This is the last part of the command submission takedown, to be called when 598 * command submission is no longer needed. It may wait on pending fences. 599 */ 600 static void vmw_release_device_late(struct vmw_private *dev_priv) 601 { 602 vmw_fence_fifo_down(dev_priv->fman); 603 if (dev_priv->cman) 604 vmw_cmdbuf_man_destroy(dev_priv->cman); 605 606 vmw_device_fini(dev_priv); 607 } 608 609 /* 610 * Sets the initial_[width|height] fields on the given vmw_private. 611 * 612 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 613 * clamping the value to fb_max_[width|height] fields and the 614 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 615 * If the values appear to be invalid, set them to 616 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 617 */ 618 static void vmw_get_initial_size(struct vmw_private *dev_priv) 619 { 620 uint32_t width; 621 uint32_t height; 622 623 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 624 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 625 626 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 627 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 628 629 if (width > dev_priv->fb_max_width || 630 height > dev_priv->fb_max_height) { 631 632 /* 633 * This is a host error and shouldn't occur. 634 */ 635 636 width = VMW_MIN_INITIAL_WIDTH; 637 height = VMW_MIN_INITIAL_HEIGHT; 638 } 639 640 dev_priv->initial_width = width; 641 dev_priv->initial_height = height; 642 } 643 644 /** 645 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 646 * system. 647 * 648 * @dev_priv: Pointer to a struct vmw_private 649 * 650 * This functions tries to determine what actions need to be taken by the 651 * driver to make system pages visible to the device. 652 * If this function decides that DMA is not possible, it returns -EINVAL. 653 * The driver may then try to disable features of the device that require 654 * DMA. 655 */ 656 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 657 { 658 static const char *names[vmw_dma_map_max] = { 659 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 660 [vmw_dma_map_populate] = "Caching DMA mappings.", 661 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 662 663 /* TTM currently doesn't fully support SEV encryption. */ 664 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 665 return -EINVAL; 666 667 if (vmw_force_coherent) 668 dev_priv->map_mode = vmw_dma_alloc_coherent; 669 else if (vmw_restrict_iommu) 670 dev_priv->map_mode = vmw_dma_map_bind; 671 else 672 dev_priv->map_mode = vmw_dma_map_populate; 673 674 drm_info(&dev_priv->drm, 675 "DMA map mode: %s\n", names[dev_priv->map_mode]); 676 return 0; 677 } 678 679 /** 680 * vmw_dma_masks - set required page- and dma masks 681 * 682 * @dev_priv: Pointer to struct drm-device 683 * 684 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 685 * restriction also for 64-bit systems. 686 */ 687 static int vmw_dma_masks(struct vmw_private *dev_priv) 688 { 689 struct drm_device *dev = &dev_priv->drm; 690 int ret = 0; 691 692 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 693 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 694 drm_info(&dev_priv->drm, 695 "Restricting DMA addresses to 44 bits.\n"); 696 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 697 } 698 699 return ret; 700 } 701 702 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 703 { 704 int ret; 705 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 706 dev_priv->vram_size >> PAGE_SHIFT); 707 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 708 return ret; 709 } 710 711 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 712 { 713 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 714 } 715 716 static int vmw_setup_pci_resources(struct vmw_private *dev, 717 u32 pci_id) 718 { 719 resource_size_t rmmio_start; 720 resource_size_t rmmio_size; 721 resource_size_t fifo_start; 722 resource_size_t fifo_size; 723 int ret; 724 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 725 726 pci_set_master(pdev); 727 728 ret = pci_request_regions(pdev, "vmwgfx probe"); 729 if (ret) 730 return ret; 731 732 dev->pci_id = pci_id; 733 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 734 rmmio_start = pci_resource_start(pdev, 0); 735 rmmio_size = pci_resource_len(pdev, 0); 736 dev->vram_start = pci_resource_start(pdev, 2); 737 dev->vram_size = pci_resource_len(pdev, 2); 738 739 drm_info(&dev->drm, 740 "Register MMIO at 0x%pa size is %llu kiB\n", 741 &rmmio_start, (uint64_t)rmmio_size / 1024); 742 dev->rmmio = devm_ioremap(dev->drm.dev, 743 rmmio_start, 744 rmmio_size); 745 if (!dev->rmmio) { 746 drm_err(&dev->drm, 747 "Failed mapping registers mmio memory.\n"); 748 pci_release_regions(pdev); 749 return -ENOMEM; 750 } 751 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 752 dev->io_start = pci_resource_start(pdev, 0); 753 dev->vram_start = pci_resource_start(pdev, 1); 754 dev->vram_size = pci_resource_len(pdev, 1); 755 fifo_start = pci_resource_start(pdev, 2); 756 fifo_size = pci_resource_len(pdev, 2); 757 758 drm_info(&dev->drm, 759 "FIFO at %pa size is %llu kiB\n", 760 &fifo_start, (uint64_t)fifo_size / 1024); 761 dev->fifo_mem = devm_memremap(dev->drm.dev, 762 fifo_start, 763 fifo_size, 764 MEMREMAP_WB); 765 766 if (IS_ERR(dev->fifo_mem)) { 767 drm_err(&dev->drm, 768 "Failed mapping FIFO memory.\n"); 769 pci_release_regions(pdev); 770 return PTR_ERR(dev->fifo_mem); 771 } 772 } else { 773 pci_release_regions(pdev); 774 return -EINVAL; 775 } 776 777 /* 778 * This is approximate size of the vram, the exact size will only 779 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 780 * size will be equal to or bigger than the size reported by 781 * SVGA_REG_VRAM_SIZE. 782 */ 783 drm_info(&dev->drm, 784 "VRAM at %pa size is %llu kiB\n", 785 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 786 787 return 0; 788 } 789 790 static int vmw_detect_version(struct vmw_private *dev) 791 { 792 uint32_t svga_id; 793 794 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 795 SVGA_ID_3 : SVGA_ID_2); 796 svga_id = vmw_read(dev, SVGA_REG_ID); 797 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 798 drm_err(&dev->drm, 799 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 800 svga_id, dev->pci_id); 801 return -ENOSYS; 802 } 803 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 804 drm_info(&dev->drm, 805 "Running on SVGA version %d.\n", (svga_id & 0xff)); 806 return 0; 807 } 808 809 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 810 { 811 int ret; 812 enum vmw_res_type i; 813 bool refuse_dma = false; 814 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 815 816 dev_priv->drm.dev_private = dev_priv; 817 818 mutex_init(&dev_priv->cmdbuf_mutex); 819 mutex_init(&dev_priv->binding_mutex); 820 spin_lock_init(&dev_priv->resource_lock); 821 spin_lock_init(&dev_priv->hw_lock); 822 spin_lock_init(&dev_priv->waiter_lock); 823 spin_lock_init(&dev_priv->cursor_lock); 824 825 ret = vmw_setup_pci_resources(dev_priv, pci_id); 826 if (ret) 827 return ret; 828 ret = vmw_detect_version(dev_priv); 829 if (ret) 830 goto out_no_pci_or_version; 831 832 833 for (i = vmw_res_context; i < vmw_res_max; ++i) { 834 idr_init_base(&dev_priv->res_idr[i], 1); 835 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 836 } 837 838 init_waitqueue_head(&dev_priv->fence_queue); 839 init_waitqueue_head(&dev_priv->fifo_queue); 840 dev_priv->fence_queue_waiters = 0; 841 dev_priv->fifo_queue_waiters = 0; 842 843 dev_priv->used_memory_size = 0; 844 845 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 846 847 dev_priv->enable_fb = enable_fbdev; 848 849 850 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 851 852 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 853 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 854 } 855 856 857 ret = vmw_dma_select_mode(dev_priv); 858 if (unlikely(ret != 0)) { 859 drm_info(&dev_priv->drm, 860 "Restricting capabilities since DMA not available.\n"); 861 refuse_dma = true; 862 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 863 drm_info(&dev_priv->drm, 864 "Disabling 3D acceleration.\n"); 865 } 866 867 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 868 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 869 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 870 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 871 872 vmw_get_initial_size(dev_priv); 873 874 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 875 dev_priv->max_gmr_ids = 876 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 877 dev_priv->max_gmr_pages = 878 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 879 dev_priv->memory_size = 880 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 881 dev_priv->memory_size -= dev_priv->vram_size; 882 } else { 883 /* 884 * An arbitrary limit of 512MiB on surface 885 * memory. But all HWV8 hardware supports GMR2. 886 */ 887 dev_priv->memory_size = 512*1024*1024; 888 } 889 dev_priv->max_mob_pages = 0; 890 dev_priv->max_mob_size = 0; 891 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 892 uint64_t mem_size; 893 894 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 895 mem_size = vmw_read(dev_priv, 896 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 897 else 898 mem_size = 899 vmw_read(dev_priv, 900 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 901 902 /* 903 * Workaround for low memory 2D VMs to compensate for the 904 * allocation taken by fbdev 905 */ 906 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 907 mem_size *= 3; 908 909 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 910 dev_priv->max_primary_mem = 911 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 912 dev_priv->max_mob_size = 913 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 914 dev_priv->stdu_max_width = 915 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 916 dev_priv->stdu_max_height = 917 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 918 919 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 920 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 921 dev_priv->texture_max_width = vmw_read(dev_priv, 922 SVGA_REG_DEV_CAP); 923 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 924 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 925 dev_priv->texture_max_height = vmw_read(dev_priv, 926 SVGA_REG_DEV_CAP); 927 } else { 928 dev_priv->texture_max_width = 8192; 929 dev_priv->texture_max_height = 8192; 930 dev_priv->max_primary_mem = dev_priv->vram_size; 931 } 932 drm_info(&dev_priv->drm, 933 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 934 (u64)dev_priv->vram_size / 1024, 935 (u64)dev_priv->fifo_mem_size / 1024, 936 dev_priv->memory_size / 1024); 937 938 drm_info(&dev_priv->drm, 939 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 940 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 941 942 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 943 dev_priv->capabilities, 944 cap1_names, ARRAY_SIZE(cap1_names)); 945 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 946 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 947 dev_priv->capabilities2, 948 cap2_names, ARRAY_SIZE(cap2_names)); 949 950 ret = vmw_dma_masks(dev_priv); 951 if (unlikely(ret != 0)) 952 goto out_err0; 953 954 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 955 956 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 957 drm_info(&dev_priv->drm, 958 "Max GMR ids is %u\n", 959 (unsigned)dev_priv->max_gmr_ids); 960 drm_info(&dev_priv->drm, 961 "Max number of GMR pages is %u\n", 962 (unsigned)dev_priv->max_gmr_pages); 963 } 964 drm_info(&dev_priv->drm, 965 "Maximum display memory size is %llu kiB\n", 966 (uint64_t)dev_priv->max_primary_mem / 1024); 967 968 /* Need mmio memory to check for fifo pitchlock cap. */ 969 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 970 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 971 !vmw_fifo_have_pitchlock(dev_priv)) { 972 ret = -ENOSYS; 973 DRM_ERROR("Hardware has no pitchlock\n"); 974 goto out_err0; 975 } 976 977 dev_priv->tdev = ttm_object_device_init(12, &vmw_prime_dmabuf_ops); 978 979 if (unlikely(dev_priv->tdev == NULL)) { 980 drm_err(&dev_priv->drm, 981 "Unable to initialize TTM object management.\n"); 982 ret = -ENOMEM; 983 goto out_err0; 984 } 985 986 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 987 ret = vmw_irq_install(&dev_priv->drm, pdev->irq); 988 if (ret != 0) { 989 drm_err(&dev_priv->drm, 990 "Failed installing irq: %d\n", ret); 991 goto out_no_irq; 992 } 993 } 994 995 dev_priv->fman = vmw_fence_manager_init(dev_priv); 996 if (unlikely(dev_priv->fman == NULL)) { 997 ret = -ENOMEM; 998 goto out_no_fman; 999 } 1000 1001 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1002 dev_priv->drm.dev, 1003 dev_priv->drm.anon_inode->i_mapping, 1004 dev_priv->drm.vma_offset_manager, 1005 dev_priv->map_mode == vmw_dma_alloc_coherent, 1006 false); 1007 if (unlikely(ret != 0)) { 1008 drm_err(&dev_priv->drm, 1009 "Failed initializing TTM buffer object driver.\n"); 1010 goto out_no_bdev; 1011 } 1012 1013 /* 1014 * Enable VRAM, but initially don't use it until SVGA is enabled and 1015 * unhidden. 1016 */ 1017 1018 ret = vmw_vram_manager_init(dev_priv); 1019 if (unlikely(ret != 0)) { 1020 drm_err(&dev_priv->drm, 1021 "Failed initializing memory manager for VRAM.\n"); 1022 goto out_no_vram; 1023 } 1024 1025 ret = vmw_devcaps_create(dev_priv); 1026 if (unlikely(ret != 0)) { 1027 drm_err(&dev_priv->drm, 1028 "Failed initializing device caps.\n"); 1029 goto out_no_vram; 1030 } 1031 1032 /* 1033 * "Guest Memory Regions" is an aperture like feature with 1034 * one slot per bo. There is an upper limit of the number of 1035 * slots as well as the bo size. 1036 */ 1037 dev_priv->has_gmr = true; 1038 /* TODO: This is most likely not correct */ 1039 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1040 refuse_dma || 1041 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1042 drm_info(&dev_priv->drm, 1043 "No GMR memory available. " 1044 "Graphics memory resources are very limited.\n"); 1045 dev_priv->has_gmr = false; 1046 } 1047 1048 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1049 dev_priv->has_mob = true; 1050 1051 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1052 drm_info(&dev_priv->drm, 1053 "No MOB memory available. " 1054 "3D will be disabled.\n"); 1055 dev_priv->has_mob = false; 1056 } 1057 if (vmw_sys_man_init(dev_priv) != 0) { 1058 drm_info(&dev_priv->drm, 1059 "No MOB page table memory available. " 1060 "3D will be disabled.\n"); 1061 dev_priv->has_mob = false; 1062 } 1063 } 1064 1065 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1066 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1067 dev_priv->sm_type = VMW_SM_4; 1068 } 1069 1070 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1071 if (has_sm4_context(dev_priv) && 1072 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1073 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1074 dev_priv->sm_type = VMW_SM_4_1; 1075 if (has_sm4_1_context(dev_priv) && 1076 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1077 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1078 dev_priv->sm_type = VMW_SM_5; 1079 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1080 dev_priv->sm_type = VMW_SM_5_1X; 1081 } 1082 } 1083 } 1084 1085 ret = vmw_kms_init(dev_priv); 1086 if (unlikely(ret != 0)) 1087 goto out_no_kms; 1088 vmw_overlay_init(dev_priv); 1089 1090 ret = vmw_request_device(dev_priv); 1091 if (ret) 1092 goto out_no_fifo; 1093 1094 vmw_print_sm_type(dev_priv); 1095 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1096 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1097 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1098 1099 if (dev_priv->enable_fb) { 1100 vmw_fifo_resource_inc(dev_priv); 1101 vmw_svga_enable(dev_priv); 1102 vmw_fb_init(dev_priv); 1103 } 1104 1105 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1106 register_pm_notifier(&dev_priv->pm_nb); 1107 1108 return 0; 1109 1110 out_no_fifo: 1111 vmw_overlay_close(dev_priv); 1112 vmw_kms_close(dev_priv); 1113 out_no_kms: 1114 if (dev_priv->has_mob) { 1115 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1116 vmw_sys_man_fini(dev_priv); 1117 } 1118 if (dev_priv->has_gmr) 1119 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1120 vmw_devcaps_destroy(dev_priv); 1121 vmw_vram_manager_fini(dev_priv); 1122 out_no_vram: 1123 ttm_device_fini(&dev_priv->bdev); 1124 out_no_bdev: 1125 vmw_fence_manager_takedown(dev_priv->fman); 1126 out_no_fman: 1127 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1128 vmw_irq_uninstall(&dev_priv->drm); 1129 out_no_irq: 1130 ttm_object_device_release(&dev_priv->tdev); 1131 out_err0: 1132 for (i = vmw_res_context; i < vmw_res_max; ++i) 1133 idr_destroy(&dev_priv->res_idr[i]); 1134 1135 if (dev_priv->ctx.staged_bindings) 1136 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1137 out_no_pci_or_version: 1138 pci_release_regions(pdev); 1139 return ret; 1140 } 1141 1142 static void vmw_driver_unload(struct drm_device *dev) 1143 { 1144 struct vmw_private *dev_priv = vmw_priv(dev); 1145 struct pci_dev *pdev = to_pci_dev(dev->dev); 1146 enum vmw_res_type i; 1147 1148 unregister_pm_notifier(&dev_priv->pm_nb); 1149 1150 if (dev_priv->ctx.res_ht_initialized) 1151 vmwgfx_ht_remove(&dev_priv->ctx.res_ht); 1152 vfree(dev_priv->ctx.cmd_bounce); 1153 if (dev_priv->enable_fb) { 1154 vmw_fb_off(dev_priv); 1155 vmw_fb_close(dev_priv); 1156 vmw_fifo_resource_dec(dev_priv); 1157 vmw_svga_disable(dev_priv); 1158 } 1159 1160 vmw_kms_close(dev_priv); 1161 vmw_overlay_close(dev_priv); 1162 1163 if (dev_priv->has_gmr) 1164 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1165 1166 vmw_release_device_early(dev_priv); 1167 if (dev_priv->has_mob) { 1168 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1169 vmw_sys_man_fini(dev_priv); 1170 } 1171 vmw_devcaps_destroy(dev_priv); 1172 vmw_vram_manager_fini(dev_priv); 1173 ttm_device_fini(&dev_priv->bdev); 1174 vmw_release_device_late(dev_priv); 1175 vmw_fence_manager_takedown(dev_priv->fman); 1176 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1177 vmw_irq_uninstall(&dev_priv->drm); 1178 1179 ttm_object_device_release(&dev_priv->tdev); 1180 if (dev_priv->ctx.staged_bindings) 1181 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1182 1183 for (i = vmw_res_context; i < vmw_res_max; ++i) 1184 idr_destroy(&dev_priv->res_idr[i]); 1185 1186 vmw_mksstat_remove_all(dev_priv); 1187 1188 pci_release_regions(pdev); 1189 } 1190 1191 static void vmw_postclose(struct drm_device *dev, 1192 struct drm_file *file_priv) 1193 { 1194 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1195 1196 ttm_object_file_release(&vmw_fp->tfile); 1197 kfree(vmw_fp); 1198 } 1199 1200 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1201 { 1202 struct vmw_private *dev_priv = vmw_priv(dev); 1203 struct vmw_fpriv *vmw_fp; 1204 int ret = -ENOMEM; 1205 1206 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1207 if (unlikely(!vmw_fp)) 1208 return ret; 1209 1210 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1211 if (unlikely(vmw_fp->tfile == NULL)) 1212 goto out_no_tfile; 1213 1214 file_priv->driver_priv = vmw_fp; 1215 1216 return 0; 1217 1218 out_no_tfile: 1219 kfree(vmw_fp); 1220 return ret; 1221 } 1222 1223 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1224 unsigned long arg, 1225 long (*ioctl_func)(struct file *, unsigned int, 1226 unsigned long)) 1227 { 1228 struct drm_file *file_priv = filp->private_data; 1229 struct drm_device *dev = file_priv->minor->dev; 1230 unsigned int nr = DRM_IOCTL_NR(cmd); 1231 unsigned int flags; 1232 1233 /* 1234 * Do extra checking on driver private ioctls. 1235 */ 1236 1237 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1238 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1239 const struct drm_ioctl_desc *ioctl = 1240 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1241 1242 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1243 return ioctl_func(filp, cmd, arg); 1244 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1245 if (!drm_is_current_master(file_priv) && 1246 !capable(CAP_SYS_ADMIN)) 1247 return -EACCES; 1248 } 1249 1250 if (unlikely(ioctl->cmd != cmd)) 1251 goto out_io_encoding; 1252 1253 flags = ioctl->flags; 1254 } else if (!drm_ioctl_flags(nr, &flags)) 1255 return -EINVAL; 1256 1257 return ioctl_func(filp, cmd, arg); 1258 1259 out_io_encoding: 1260 DRM_ERROR("Invalid command format, ioctl %d\n", 1261 nr - DRM_COMMAND_BASE); 1262 1263 return -EINVAL; 1264 } 1265 1266 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1267 unsigned long arg) 1268 { 1269 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1270 } 1271 1272 #ifdef CONFIG_COMPAT 1273 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1274 unsigned long arg) 1275 { 1276 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1277 } 1278 #endif 1279 1280 static void vmw_master_set(struct drm_device *dev, 1281 struct drm_file *file_priv, 1282 bool from_open) 1283 { 1284 /* 1285 * Inform a new master that the layout may have changed while 1286 * it was gone. 1287 */ 1288 if (!from_open) 1289 drm_sysfs_hotplug_event(dev); 1290 } 1291 1292 static void vmw_master_drop(struct drm_device *dev, 1293 struct drm_file *file_priv) 1294 { 1295 struct vmw_private *dev_priv = vmw_priv(dev); 1296 1297 vmw_kms_legacy_hotspot_clear(dev_priv); 1298 if (!dev_priv->enable_fb) 1299 vmw_svga_disable(dev_priv); 1300 } 1301 1302 /** 1303 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1304 * 1305 * @dev_priv: Pointer to device private struct. 1306 * Needs the reservation sem to be held in non-exclusive mode. 1307 */ 1308 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1309 { 1310 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1311 1312 if (!ttm_resource_manager_used(man)) { 1313 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1314 ttm_resource_manager_set_used(man, true); 1315 } 1316 } 1317 1318 /** 1319 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1320 * 1321 * @dev_priv: Pointer to device private struct. 1322 */ 1323 void vmw_svga_enable(struct vmw_private *dev_priv) 1324 { 1325 __vmw_svga_enable(dev_priv); 1326 } 1327 1328 /** 1329 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1330 * 1331 * @dev_priv: Pointer to device private struct. 1332 * Needs the reservation sem to be held in exclusive mode. 1333 * Will not empty VRAM. VRAM must be emptied by caller. 1334 */ 1335 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1336 { 1337 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1338 1339 if (ttm_resource_manager_used(man)) { 1340 ttm_resource_manager_set_used(man, false); 1341 vmw_write(dev_priv, SVGA_REG_ENABLE, 1342 SVGA_REG_ENABLE_HIDE | 1343 SVGA_REG_ENABLE_ENABLE); 1344 } 1345 } 1346 1347 /** 1348 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1349 * running. 1350 * 1351 * @dev_priv: Pointer to device private struct. 1352 * Will empty VRAM. 1353 */ 1354 void vmw_svga_disable(struct vmw_private *dev_priv) 1355 { 1356 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1357 /* 1358 * Disabling SVGA will turn off device modesetting capabilities, so 1359 * notify KMS about that so that it doesn't cache atomic state that 1360 * isn't valid anymore, for example crtcs turned on. 1361 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1362 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1363 * end up with lock order reversal. Thus, a master may actually perform 1364 * a new modeset just after we call vmw_kms_lost_device() and race with 1365 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1366 * to be inconsistent with the device, causing modesetting problems. 1367 * 1368 */ 1369 vmw_kms_lost_device(&dev_priv->drm); 1370 if (ttm_resource_manager_used(man)) { 1371 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1372 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1373 ttm_resource_manager_set_used(man, false); 1374 vmw_write(dev_priv, SVGA_REG_ENABLE, 1375 SVGA_REG_ENABLE_HIDE | 1376 SVGA_REG_ENABLE_ENABLE); 1377 } 1378 } 1379 1380 static void vmw_remove(struct pci_dev *pdev) 1381 { 1382 struct drm_device *dev = pci_get_drvdata(pdev); 1383 1384 drm_dev_unregister(dev); 1385 vmw_driver_unload(dev); 1386 } 1387 1388 static unsigned long 1389 vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1390 unsigned long len, unsigned long pgoff, 1391 unsigned long flags) 1392 { 1393 struct drm_file *file_priv = file->private_data; 1394 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1395 1396 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1397 dev_priv->drm.vma_offset_manager); 1398 } 1399 1400 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1401 void *ptr) 1402 { 1403 struct vmw_private *dev_priv = 1404 container_of(nb, struct vmw_private, pm_nb); 1405 1406 switch (val) { 1407 case PM_HIBERNATION_PREPARE: 1408 /* 1409 * Take the reservation sem in write mode, which will make sure 1410 * there are no other processes holding a buffer object 1411 * reservation, meaning we should be able to evict all buffer 1412 * objects if needed. 1413 * Once user-space processes have been frozen, we can release 1414 * the lock again. 1415 */ 1416 dev_priv->suspend_locked = true; 1417 break; 1418 case PM_POST_HIBERNATION: 1419 case PM_POST_RESTORE: 1420 if (READ_ONCE(dev_priv->suspend_locked)) { 1421 dev_priv->suspend_locked = false; 1422 } 1423 break; 1424 default: 1425 break; 1426 } 1427 return 0; 1428 } 1429 1430 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1431 { 1432 struct drm_device *dev = pci_get_drvdata(pdev); 1433 struct vmw_private *dev_priv = vmw_priv(dev); 1434 1435 if (dev_priv->refuse_hibernation) 1436 return -EBUSY; 1437 1438 pci_save_state(pdev); 1439 pci_disable_device(pdev); 1440 pci_set_power_state(pdev, PCI_D3hot); 1441 return 0; 1442 } 1443 1444 static int vmw_pci_resume(struct pci_dev *pdev) 1445 { 1446 pci_set_power_state(pdev, PCI_D0); 1447 pci_restore_state(pdev); 1448 return pci_enable_device(pdev); 1449 } 1450 1451 static int vmw_pm_suspend(struct device *kdev) 1452 { 1453 struct pci_dev *pdev = to_pci_dev(kdev); 1454 struct pm_message dummy; 1455 1456 dummy.event = 0; 1457 1458 return vmw_pci_suspend(pdev, dummy); 1459 } 1460 1461 static int vmw_pm_resume(struct device *kdev) 1462 { 1463 struct pci_dev *pdev = to_pci_dev(kdev); 1464 1465 return vmw_pci_resume(pdev); 1466 } 1467 1468 static int vmw_pm_freeze(struct device *kdev) 1469 { 1470 struct pci_dev *pdev = to_pci_dev(kdev); 1471 struct drm_device *dev = pci_get_drvdata(pdev); 1472 struct vmw_private *dev_priv = vmw_priv(dev); 1473 struct ttm_operation_ctx ctx = { 1474 .interruptible = false, 1475 .no_wait_gpu = false 1476 }; 1477 int ret; 1478 1479 /* 1480 * No user-space processes should be running now. 1481 */ 1482 ret = vmw_kms_suspend(&dev_priv->drm); 1483 if (ret) { 1484 DRM_ERROR("Failed to freeze modesetting.\n"); 1485 return ret; 1486 } 1487 if (dev_priv->enable_fb) 1488 vmw_fb_off(dev_priv); 1489 1490 vmw_execbuf_release_pinned_bo(dev_priv); 1491 vmw_resource_evict_all(dev_priv); 1492 vmw_release_device_early(dev_priv); 1493 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1494 if (dev_priv->enable_fb) 1495 vmw_fifo_resource_dec(dev_priv); 1496 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1497 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1498 if (dev_priv->enable_fb) 1499 vmw_fifo_resource_inc(dev_priv); 1500 WARN_ON(vmw_request_device_late(dev_priv)); 1501 dev_priv->suspend_locked = false; 1502 if (dev_priv->suspend_state) 1503 vmw_kms_resume(dev); 1504 if (dev_priv->enable_fb) 1505 vmw_fb_on(dev_priv); 1506 return -EBUSY; 1507 } 1508 1509 vmw_fence_fifo_down(dev_priv->fman); 1510 __vmw_svga_disable(dev_priv); 1511 1512 vmw_release_device_late(dev_priv); 1513 return 0; 1514 } 1515 1516 static int vmw_pm_restore(struct device *kdev) 1517 { 1518 struct pci_dev *pdev = to_pci_dev(kdev); 1519 struct drm_device *dev = pci_get_drvdata(pdev); 1520 struct vmw_private *dev_priv = vmw_priv(dev); 1521 int ret; 1522 1523 vmw_detect_version(dev_priv); 1524 1525 if (dev_priv->enable_fb) 1526 vmw_fifo_resource_inc(dev_priv); 1527 1528 ret = vmw_request_device(dev_priv); 1529 if (ret) 1530 return ret; 1531 1532 if (dev_priv->enable_fb) 1533 __vmw_svga_enable(dev_priv); 1534 1535 vmw_fence_fifo_up(dev_priv->fman); 1536 dev_priv->suspend_locked = false; 1537 if (dev_priv->suspend_state) 1538 vmw_kms_resume(&dev_priv->drm); 1539 1540 if (dev_priv->enable_fb) 1541 vmw_fb_on(dev_priv); 1542 1543 return 0; 1544 } 1545 1546 static const struct dev_pm_ops vmw_pm_ops = { 1547 .freeze = vmw_pm_freeze, 1548 .thaw = vmw_pm_restore, 1549 .restore = vmw_pm_restore, 1550 .suspend = vmw_pm_suspend, 1551 .resume = vmw_pm_resume, 1552 }; 1553 1554 static const struct file_operations vmwgfx_driver_fops = { 1555 .owner = THIS_MODULE, 1556 .open = drm_open, 1557 .release = drm_release, 1558 .unlocked_ioctl = vmw_unlocked_ioctl, 1559 .mmap = vmw_mmap, 1560 .poll = drm_poll, 1561 .read = drm_read, 1562 #if defined(CONFIG_COMPAT) 1563 .compat_ioctl = vmw_compat_ioctl, 1564 #endif 1565 .llseek = noop_llseek, 1566 .get_unmapped_area = vmw_get_unmapped_area, 1567 }; 1568 1569 static const struct drm_driver driver = { 1570 .driver_features = 1571 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM, 1572 .ioctls = vmw_ioctls, 1573 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1574 .master_set = vmw_master_set, 1575 .master_drop = vmw_master_drop, 1576 .open = vmw_driver_open, 1577 .postclose = vmw_postclose, 1578 1579 .dumb_create = vmw_dumb_create, 1580 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1581 1582 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1583 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1584 1585 .fops = &vmwgfx_driver_fops, 1586 .name = VMWGFX_DRIVER_NAME, 1587 .desc = VMWGFX_DRIVER_DESC, 1588 .date = VMWGFX_DRIVER_DATE, 1589 .major = VMWGFX_DRIVER_MAJOR, 1590 .minor = VMWGFX_DRIVER_MINOR, 1591 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1592 }; 1593 1594 static struct pci_driver vmw_pci_driver = { 1595 .name = VMWGFX_DRIVER_NAME, 1596 .id_table = vmw_pci_id_list, 1597 .probe = vmw_probe, 1598 .remove = vmw_remove, 1599 .driver = { 1600 .pm = &vmw_pm_ops 1601 } 1602 }; 1603 1604 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1605 { 1606 struct vmw_private *vmw; 1607 int ret; 1608 1609 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1610 if (ret) 1611 goto out_error; 1612 1613 ret = pcim_enable_device(pdev); 1614 if (ret) 1615 goto out_error; 1616 1617 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1618 struct vmw_private, drm); 1619 if (IS_ERR(vmw)) { 1620 ret = PTR_ERR(vmw); 1621 goto out_error; 1622 } 1623 1624 pci_set_drvdata(pdev, &vmw->drm); 1625 1626 ret = vmw_driver_load(vmw, ent->device); 1627 if (ret) 1628 goto out_error; 1629 1630 ret = drm_dev_register(&vmw->drm, 0); 1631 if (ret) 1632 goto out_unload; 1633 1634 vmw_debugfs_gem_init(vmw); 1635 1636 return 0; 1637 out_unload: 1638 vmw_driver_unload(&vmw->drm); 1639 out_error: 1640 return ret; 1641 } 1642 1643 drm_module_pci_driver(vmw_pci_driver); 1644 1645 MODULE_AUTHOR("VMware Inc. and others"); 1646 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1647 MODULE_LICENSE("GPL and additional rights"); 1648 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1649 __stringify(VMWGFX_DRIVER_MINOR) "." 1650 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1651 "0"); 1652