1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/module.h> 31 32 #include <drm/drm_drv.h> 33 #include <drm/drm_ioctl.h> 34 #include <drm/drm_pci.h> 35 #include <drm/drm_sysfs.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_module.h> 38 #include <drm/ttm/ttm_placement.h> 39 40 #include "ttm_object.h" 41 #include "vmwgfx_binding.h" 42 #include "vmwgfx_drv.h" 43 44 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 45 #define VMWGFX_CHIP_SVGAII 0 46 #define VMW_FB_RESERVATION 0 47 48 #define VMW_MIN_INITIAL_WIDTH 800 49 #define VMW_MIN_INITIAL_HEIGHT 600 50 51 #ifndef VMWGFX_GIT_VERSION 52 #define VMWGFX_GIT_VERSION "Unknown" 53 #endif 54 55 #define VMWGFX_REPO "In Tree" 56 57 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 58 59 60 /** 61 * Fully encoded drm commands. Might move to vmw_drm.h 62 */ 63 64 #define DRM_IOCTL_VMW_GET_PARAM \ 65 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 66 struct drm_vmw_getparam_arg) 67 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 69 union drm_vmw_alloc_dmabuf_arg) 70 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 72 struct drm_vmw_unref_dmabuf_arg) 73 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 75 struct drm_vmw_cursor_bypass_arg) 76 77 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 79 struct drm_vmw_control_stream_arg) 80 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 82 struct drm_vmw_stream_arg) 83 #define DRM_IOCTL_VMW_UNREF_STREAM \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 85 struct drm_vmw_stream_arg) 86 87 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 88 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 89 struct drm_vmw_context_arg) 90 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 92 struct drm_vmw_context_arg) 93 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 95 union drm_vmw_surface_create_arg) 96 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 98 struct drm_vmw_surface_arg) 99 #define DRM_IOCTL_VMW_REF_SURFACE \ 100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 101 union drm_vmw_surface_reference_arg) 102 #define DRM_IOCTL_VMW_EXECBUF \ 103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 104 struct drm_vmw_execbuf_arg) 105 #define DRM_IOCTL_VMW_GET_3D_CAP \ 106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 107 struct drm_vmw_get_3d_cap_arg) 108 #define DRM_IOCTL_VMW_FENCE_WAIT \ 109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 110 struct drm_vmw_fence_wait_arg) 111 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 113 struct drm_vmw_fence_signaled_arg) 114 #define DRM_IOCTL_VMW_FENCE_UNREF \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 116 struct drm_vmw_fence_arg) 117 #define DRM_IOCTL_VMW_FENCE_EVENT \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 119 struct drm_vmw_fence_event_arg) 120 #define DRM_IOCTL_VMW_PRESENT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 122 struct drm_vmw_present_arg) 123 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 125 struct drm_vmw_present_readback_arg) 126 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 128 struct drm_vmw_update_layout_arg) 129 #define DRM_IOCTL_VMW_CREATE_SHADER \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 131 struct drm_vmw_shader_create_arg) 132 #define DRM_IOCTL_VMW_UNREF_SHADER \ 133 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 134 struct drm_vmw_shader_arg) 135 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 136 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 137 union drm_vmw_gb_surface_create_arg) 138 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 140 union drm_vmw_gb_surface_reference_arg) 141 #define DRM_IOCTL_VMW_SYNCCPU \ 142 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 143 struct drm_vmw_synccpu_arg) 144 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 146 struct drm_vmw_context_arg) 147 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 149 union drm_vmw_gb_surface_create_ext_arg) 150 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 152 union drm_vmw_gb_surface_reference_ext_arg) 153 154 /** 155 * The core DRM version of this macro doesn't account for 156 * DRM_COMMAND_BASE. 157 */ 158 159 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 160 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 161 162 /** 163 * Ioctl definitions. 164 */ 165 166 static const struct drm_ioctl_desc vmw_ioctls[] = { 167 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 168 DRM_AUTH | DRM_RENDER_ALLOW), 169 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 170 DRM_AUTH | DRM_RENDER_ALLOW), 171 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 172 DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 174 vmw_kms_cursor_bypass_ioctl, 175 DRM_MASTER), 176 177 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 178 DRM_MASTER), 179 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 180 DRM_MASTER), 181 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 182 DRM_MASTER), 183 184 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 185 DRM_AUTH | DRM_RENDER_ALLOW), 186 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 187 DRM_RENDER_ALLOW), 188 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 189 DRM_AUTH | DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 191 DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 193 DRM_AUTH | DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, DRM_AUTH | 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 199 vmw_fence_obj_signaled_ioctl, 200 DRM_RENDER_ALLOW), 201 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 202 DRM_RENDER_ALLOW), 203 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 204 DRM_AUTH | DRM_RENDER_ALLOW), 205 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 206 DRM_AUTH | DRM_RENDER_ALLOW), 207 208 /* these allow direct access to the framebuffers mark as master only */ 209 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 210 DRM_MASTER | DRM_AUTH), 211 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 212 vmw_present_readback_ioctl, 213 DRM_MASTER | DRM_AUTH), 214 /* 215 * The permissions of the below ioctl are overridden in 216 * vmw_generic_ioctl(). We require either 217 * DRM_MASTER or capable(CAP_SYS_ADMIN). 218 */ 219 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 220 vmw_kms_update_layout_ioctl, 221 DRM_RENDER_ALLOW), 222 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 223 vmw_shader_define_ioctl, 224 DRM_AUTH | DRM_RENDER_ALLOW), 225 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 226 vmw_shader_destroy_ioctl, 227 DRM_RENDER_ALLOW), 228 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 229 vmw_gb_surface_define_ioctl, 230 DRM_AUTH | DRM_RENDER_ALLOW), 231 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 232 vmw_gb_surface_reference_ioctl, 233 DRM_AUTH | DRM_RENDER_ALLOW), 234 VMW_IOCTL_DEF(VMW_SYNCCPU, 235 vmw_user_bo_synccpu_ioctl, 236 DRM_RENDER_ALLOW), 237 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 238 vmw_extended_context_define_ioctl, 239 DRM_AUTH | DRM_RENDER_ALLOW), 240 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 241 vmw_gb_surface_define_ext_ioctl, 242 DRM_AUTH | DRM_RENDER_ALLOW), 243 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 244 vmw_gb_surface_reference_ext_ioctl, 245 DRM_AUTH | DRM_RENDER_ALLOW), 246 }; 247 248 static const struct pci_device_id vmw_pci_id_list[] = { 249 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 250 {0, 0, 0} 251 }; 252 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 253 254 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 255 static int vmw_force_iommu; 256 static int vmw_restrict_iommu; 257 static int vmw_force_coherent; 258 static int vmw_restrict_dma_mask; 259 static int vmw_assume_16bpp; 260 261 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 262 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 263 void *ptr); 264 265 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 266 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 267 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 268 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 269 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 270 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 271 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 272 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 273 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 274 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 275 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 276 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 277 278 279 static void vmw_print_capabilities2(uint32_t capabilities2) 280 { 281 DRM_INFO("Capabilities2:\n"); 282 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 283 DRM_INFO(" Grow oTable.\n"); 284 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 285 DRM_INFO(" IntraSurface copy.\n"); 286 } 287 288 static void vmw_print_capabilities(uint32_t capabilities) 289 { 290 DRM_INFO("Capabilities:\n"); 291 if (capabilities & SVGA_CAP_RECT_COPY) 292 DRM_INFO(" Rect copy.\n"); 293 if (capabilities & SVGA_CAP_CURSOR) 294 DRM_INFO(" Cursor.\n"); 295 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 296 DRM_INFO(" Cursor bypass.\n"); 297 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 298 DRM_INFO(" Cursor bypass 2.\n"); 299 if (capabilities & SVGA_CAP_8BIT_EMULATION) 300 DRM_INFO(" 8bit emulation.\n"); 301 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 302 DRM_INFO(" Alpha cursor.\n"); 303 if (capabilities & SVGA_CAP_3D) 304 DRM_INFO(" 3D.\n"); 305 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 306 DRM_INFO(" Extended Fifo.\n"); 307 if (capabilities & SVGA_CAP_MULTIMON) 308 DRM_INFO(" Multimon.\n"); 309 if (capabilities & SVGA_CAP_PITCHLOCK) 310 DRM_INFO(" Pitchlock.\n"); 311 if (capabilities & SVGA_CAP_IRQMASK) 312 DRM_INFO(" Irq mask.\n"); 313 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 314 DRM_INFO(" Display Topology.\n"); 315 if (capabilities & SVGA_CAP_GMR) 316 DRM_INFO(" GMR.\n"); 317 if (capabilities & SVGA_CAP_TRACES) 318 DRM_INFO(" Traces.\n"); 319 if (capabilities & SVGA_CAP_GMR2) 320 DRM_INFO(" GMR2.\n"); 321 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 322 DRM_INFO(" Screen Object 2.\n"); 323 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 324 DRM_INFO(" Command Buffers.\n"); 325 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 326 DRM_INFO(" Command Buffers 2.\n"); 327 if (capabilities & SVGA_CAP_GBOBJECTS) 328 DRM_INFO(" Guest Backed Resources.\n"); 329 if (capabilities & SVGA_CAP_DX) 330 DRM_INFO(" DX Features.\n"); 331 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 332 DRM_INFO(" HP Command Queue.\n"); 333 } 334 335 /** 336 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 337 * 338 * @dev_priv: A device private structure. 339 * 340 * This function creates a small buffer object that holds the query 341 * result for dummy queries emitted as query barriers. 342 * The function will then map the first page and initialize a pending 343 * occlusion query result structure, Finally it will unmap the buffer. 344 * No interruptible waits are done within this function. 345 * 346 * Returns an error if bo creation or initialization fails. 347 */ 348 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 349 { 350 int ret; 351 struct vmw_buffer_object *vbo; 352 struct ttm_bo_kmap_obj map; 353 volatile SVGA3dQueryResult *result; 354 bool dummy; 355 356 /* 357 * Create the vbo as pinned, so that a tryreserve will 358 * immediately succeed. This is because we're the only 359 * user of the bo currently. 360 */ 361 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 362 if (!vbo) 363 return -ENOMEM; 364 365 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 366 &vmw_sys_ne_placement, false, 367 &vmw_bo_bo_free); 368 if (unlikely(ret != 0)) 369 return ret; 370 371 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 372 BUG_ON(ret != 0); 373 vmw_bo_pin_reserved(vbo, true); 374 375 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 376 if (likely(ret == 0)) { 377 result = ttm_kmap_obj_virtual(&map, &dummy); 378 result->totalSize = sizeof(*result); 379 result->state = SVGA3D_QUERYSTATE_PENDING; 380 result->result32 = 0xff; 381 ttm_bo_kunmap(&map); 382 } 383 vmw_bo_pin_reserved(vbo, false); 384 ttm_bo_unreserve(&vbo->base); 385 386 if (unlikely(ret != 0)) { 387 DRM_ERROR("Dummy query buffer map failed.\n"); 388 vmw_bo_unreference(&vbo); 389 } else 390 dev_priv->dummy_query_bo = vbo; 391 392 return ret; 393 } 394 395 /** 396 * vmw_request_device_late - Perform late device setup 397 * 398 * @dev_priv: Pointer to device private. 399 * 400 * This function performs setup of otables and enables large command 401 * buffer submission. These tasks are split out to a separate function 402 * because it reverts vmw_release_device_early and is intended to be used 403 * by an error path in the hibernation code. 404 */ 405 static int vmw_request_device_late(struct vmw_private *dev_priv) 406 { 407 int ret; 408 409 if (dev_priv->has_mob) { 410 ret = vmw_otables_setup(dev_priv); 411 if (unlikely(ret != 0)) { 412 DRM_ERROR("Unable to initialize " 413 "guest Memory OBjects.\n"); 414 return ret; 415 } 416 } 417 418 if (dev_priv->cman) { 419 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 420 256*4096, 2*4096); 421 if (ret) { 422 struct vmw_cmdbuf_man *man = dev_priv->cman; 423 424 dev_priv->cman = NULL; 425 vmw_cmdbuf_man_destroy(man); 426 } 427 } 428 429 return 0; 430 } 431 432 static int vmw_request_device(struct vmw_private *dev_priv) 433 { 434 int ret; 435 436 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 437 if (unlikely(ret != 0)) { 438 DRM_ERROR("Unable to initialize FIFO.\n"); 439 return ret; 440 } 441 vmw_fence_fifo_up(dev_priv->fman); 442 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 443 if (IS_ERR(dev_priv->cman)) { 444 dev_priv->cman = NULL; 445 dev_priv->has_dx = false; 446 } 447 448 ret = vmw_request_device_late(dev_priv); 449 if (ret) 450 goto out_no_mob; 451 452 ret = vmw_dummy_query_bo_create(dev_priv); 453 if (unlikely(ret != 0)) 454 goto out_no_query_bo; 455 456 return 0; 457 458 out_no_query_bo: 459 if (dev_priv->cman) 460 vmw_cmdbuf_remove_pool(dev_priv->cman); 461 if (dev_priv->has_mob) { 462 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 463 vmw_otables_takedown(dev_priv); 464 } 465 if (dev_priv->cman) 466 vmw_cmdbuf_man_destroy(dev_priv->cman); 467 out_no_mob: 468 vmw_fence_fifo_down(dev_priv->fman); 469 vmw_fifo_release(dev_priv, &dev_priv->fifo); 470 return ret; 471 } 472 473 /** 474 * vmw_release_device_early - Early part of fifo takedown. 475 * 476 * @dev_priv: Pointer to device private struct. 477 * 478 * This is the first part of command submission takedown, to be called before 479 * buffer management is taken down. 480 */ 481 static void vmw_release_device_early(struct vmw_private *dev_priv) 482 { 483 /* 484 * Previous destructions should've released 485 * the pinned bo. 486 */ 487 488 BUG_ON(dev_priv->pinned_bo != NULL); 489 490 vmw_bo_unreference(&dev_priv->dummy_query_bo); 491 if (dev_priv->cman) 492 vmw_cmdbuf_remove_pool(dev_priv->cman); 493 494 if (dev_priv->has_mob) { 495 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 496 vmw_otables_takedown(dev_priv); 497 } 498 } 499 500 /** 501 * vmw_release_device_late - Late part of fifo takedown. 502 * 503 * @dev_priv: Pointer to device private struct. 504 * 505 * This is the last part of the command submission takedown, to be called when 506 * command submission is no longer needed. It may wait on pending fences. 507 */ 508 static void vmw_release_device_late(struct vmw_private *dev_priv) 509 { 510 vmw_fence_fifo_down(dev_priv->fman); 511 if (dev_priv->cman) 512 vmw_cmdbuf_man_destroy(dev_priv->cman); 513 514 vmw_fifo_release(dev_priv, &dev_priv->fifo); 515 } 516 517 /** 518 * Sets the initial_[width|height] fields on the given vmw_private. 519 * 520 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 521 * clamping the value to fb_max_[width|height] fields and the 522 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 523 * If the values appear to be invalid, set them to 524 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 525 */ 526 static void vmw_get_initial_size(struct vmw_private *dev_priv) 527 { 528 uint32_t width; 529 uint32_t height; 530 531 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 532 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 533 534 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 535 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 536 537 if (width > dev_priv->fb_max_width || 538 height > dev_priv->fb_max_height) { 539 540 /* 541 * This is a host error and shouldn't occur. 542 */ 543 544 width = VMW_MIN_INITIAL_WIDTH; 545 height = VMW_MIN_INITIAL_HEIGHT; 546 } 547 548 dev_priv->initial_width = width; 549 dev_priv->initial_height = height; 550 } 551 552 /** 553 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 554 * system. 555 * 556 * @dev_priv: Pointer to a struct vmw_private 557 * 558 * This functions tries to determine what actions need to be taken by the 559 * driver to make system pages visible to the device. 560 * If this function decides that DMA is not possible, it returns -EINVAL. 561 * The driver may then try to disable features of the device that require 562 * DMA. 563 */ 564 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 565 { 566 static const char *names[vmw_dma_map_max] = { 567 [vmw_dma_phys] = "Using physical TTM page addresses.", 568 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 569 [vmw_dma_map_populate] = "Caching DMA mappings.", 570 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 571 572 if (vmw_force_coherent) 573 dev_priv->map_mode = vmw_dma_alloc_coherent; 574 else if (vmw_restrict_iommu) 575 dev_priv->map_mode = vmw_dma_map_bind; 576 else 577 dev_priv->map_mode = vmw_dma_map_populate; 578 579 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 580 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 581 return -EINVAL; 582 583 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 584 return 0; 585 } 586 587 /** 588 * vmw_dma_masks - set required page- and dma masks 589 * 590 * @dev: Pointer to struct drm-device 591 * 592 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 593 * restriction also for 64-bit systems. 594 */ 595 static int vmw_dma_masks(struct vmw_private *dev_priv) 596 { 597 struct drm_device *dev = dev_priv->dev; 598 int ret = 0; 599 600 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 601 if (dev_priv->map_mode != vmw_dma_phys && 602 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 603 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 604 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 605 } 606 607 return ret; 608 } 609 610 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 611 { 612 struct vmw_private *dev_priv; 613 int ret; 614 uint32_t svga_id; 615 enum vmw_res_type i; 616 bool refuse_dma = false; 617 char host_log[100] = {0}; 618 619 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 620 if (unlikely(!dev_priv)) { 621 DRM_ERROR("Failed allocating a device private struct.\n"); 622 return -ENOMEM; 623 } 624 625 pci_set_master(dev->pdev); 626 627 dev_priv->dev = dev; 628 dev_priv->vmw_chipset = chipset; 629 dev_priv->last_read_seqno = (uint32_t) -100; 630 mutex_init(&dev_priv->cmdbuf_mutex); 631 mutex_init(&dev_priv->release_mutex); 632 mutex_init(&dev_priv->binding_mutex); 633 mutex_init(&dev_priv->global_kms_state_mutex); 634 ttm_lock_init(&dev_priv->reservation_sem); 635 spin_lock_init(&dev_priv->resource_lock); 636 spin_lock_init(&dev_priv->hw_lock); 637 spin_lock_init(&dev_priv->waiter_lock); 638 spin_lock_init(&dev_priv->cap_lock); 639 spin_lock_init(&dev_priv->svga_lock); 640 spin_lock_init(&dev_priv->cursor_lock); 641 642 for (i = vmw_res_context; i < vmw_res_max; ++i) { 643 idr_init(&dev_priv->res_idr[i]); 644 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 645 } 646 647 init_waitqueue_head(&dev_priv->fence_queue); 648 init_waitqueue_head(&dev_priv->fifo_queue); 649 dev_priv->fence_queue_waiters = 0; 650 dev_priv->fifo_queue_waiters = 0; 651 652 dev_priv->used_memory_size = 0; 653 654 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 655 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 656 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 657 658 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 659 660 dev_priv->enable_fb = enable_fbdev; 661 662 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 663 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 664 if (svga_id != SVGA_ID_2) { 665 ret = -ENOSYS; 666 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 667 goto out_err0; 668 } 669 670 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 671 672 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 673 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 674 } 675 676 677 ret = vmw_dma_select_mode(dev_priv); 678 if (unlikely(ret != 0)) { 679 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 680 refuse_dma = true; 681 } 682 683 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 684 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 685 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 686 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 687 688 vmw_get_initial_size(dev_priv); 689 690 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 691 dev_priv->max_gmr_ids = 692 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 693 dev_priv->max_gmr_pages = 694 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 695 dev_priv->memory_size = 696 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 697 dev_priv->memory_size -= dev_priv->vram_size; 698 } else { 699 /* 700 * An arbitrary limit of 512MiB on surface 701 * memory. But all HWV8 hardware supports GMR2. 702 */ 703 dev_priv->memory_size = 512*1024*1024; 704 } 705 dev_priv->max_mob_pages = 0; 706 dev_priv->max_mob_size = 0; 707 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 708 uint64_t mem_size = 709 vmw_read(dev_priv, 710 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 711 712 /* 713 * Workaround for low memory 2D VMs to compensate for the 714 * allocation taken by fbdev 715 */ 716 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 717 mem_size *= 3; 718 719 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 720 dev_priv->prim_bb_mem = 721 vmw_read(dev_priv, 722 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 723 dev_priv->max_mob_size = 724 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 725 dev_priv->stdu_max_width = 726 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 727 dev_priv->stdu_max_height = 728 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 729 730 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 731 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 732 dev_priv->texture_max_width = vmw_read(dev_priv, 733 SVGA_REG_DEV_CAP); 734 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 735 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 736 dev_priv->texture_max_height = vmw_read(dev_priv, 737 SVGA_REG_DEV_CAP); 738 } else { 739 dev_priv->texture_max_width = 8192; 740 dev_priv->texture_max_height = 8192; 741 dev_priv->prim_bb_mem = dev_priv->vram_size; 742 } 743 744 vmw_print_capabilities(dev_priv->capabilities); 745 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 746 vmw_print_capabilities2(dev_priv->capabilities2); 747 748 ret = vmw_dma_masks(dev_priv); 749 if (unlikely(ret != 0)) 750 goto out_err0; 751 752 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 753 SCATTERLIST_MAX_SEGMENT)); 754 755 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 756 DRM_INFO("Max GMR ids is %u\n", 757 (unsigned)dev_priv->max_gmr_ids); 758 DRM_INFO("Max number of GMR pages is %u\n", 759 (unsigned)dev_priv->max_gmr_pages); 760 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 761 (unsigned)dev_priv->memory_size / 1024); 762 } 763 DRM_INFO("Maximum display memory size is %u kiB\n", 764 dev_priv->prim_bb_mem / 1024); 765 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 766 dev_priv->vram_start, dev_priv->vram_size / 1024); 767 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 768 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 769 770 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 771 dev_priv->mmio_size, MEMREMAP_WB); 772 773 if (unlikely(dev_priv->mmio_virt == NULL)) { 774 ret = -ENOMEM; 775 DRM_ERROR("Failed mapping MMIO.\n"); 776 goto out_err0; 777 } 778 779 /* Need mmio memory to check for fifo pitchlock cap. */ 780 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 781 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 782 !vmw_fifo_have_pitchlock(dev_priv)) { 783 ret = -ENOSYS; 784 DRM_ERROR("Hardware has no pitchlock\n"); 785 goto out_err4; 786 } 787 788 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 789 &vmw_prime_dmabuf_ops); 790 791 if (unlikely(dev_priv->tdev == NULL)) { 792 DRM_ERROR("Unable to initialize TTM object management.\n"); 793 ret = -ENOMEM; 794 goto out_err4; 795 } 796 797 dev->dev_private = dev_priv; 798 799 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 800 dev_priv->stealth = (ret != 0); 801 if (dev_priv->stealth) { 802 /** 803 * Request at least the mmio PCI resource. 804 */ 805 806 DRM_INFO("It appears like vesafb is loaded. " 807 "Ignore above error if any.\n"); 808 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 809 if (unlikely(ret != 0)) { 810 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 811 goto out_no_device; 812 } 813 } 814 815 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 816 ret = vmw_irq_install(dev, dev->pdev->irq); 817 if (ret != 0) { 818 DRM_ERROR("Failed installing irq: %d\n", ret); 819 goto out_no_irq; 820 } 821 } 822 823 dev_priv->fman = vmw_fence_manager_init(dev_priv); 824 if (unlikely(dev_priv->fman == NULL)) { 825 ret = -ENOMEM; 826 goto out_no_fman; 827 } 828 829 drm_vma_offset_manager_init(&dev_priv->vma_manager, 830 DRM_FILE_PAGE_OFFSET_START, 831 DRM_FILE_PAGE_OFFSET_SIZE); 832 ret = ttm_bo_device_init(&dev_priv->bdev, 833 &vmw_bo_driver, 834 dev->anon_inode->i_mapping, 835 &dev_priv->vma_manager, 836 false); 837 if (unlikely(ret != 0)) { 838 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 839 goto out_no_bdev; 840 } 841 842 /* 843 * Enable VRAM, but initially don't use it until SVGA is enabled and 844 * unhidden. 845 */ 846 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 847 (dev_priv->vram_size >> PAGE_SHIFT)); 848 if (unlikely(ret != 0)) { 849 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 850 goto out_no_vram; 851 } 852 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 853 854 dev_priv->has_gmr = true; 855 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 856 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 857 VMW_PL_GMR) != 0) { 858 DRM_INFO("No GMR memory available. " 859 "Graphics memory resources are very limited.\n"); 860 dev_priv->has_gmr = false; 861 } 862 863 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 864 dev_priv->has_mob = true; 865 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 866 VMW_PL_MOB) != 0) { 867 DRM_INFO("No MOB memory available. " 868 "3D will be disabled.\n"); 869 dev_priv->has_mob = false; 870 } 871 } 872 873 if (dev_priv->has_mob) { 874 spin_lock(&dev_priv->cap_lock); 875 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 876 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 877 spin_unlock(&dev_priv->cap_lock); 878 } 879 880 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 881 ret = vmw_kms_init(dev_priv); 882 if (unlikely(ret != 0)) 883 goto out_no_kms; 884 vmw_overlay_init(dev_priv); 885 886 ret = vmw_request_device(dev_priv); 887 if (ret) 888 goto out_no_fifo; 889 890 if (dev_priv->has_dx) { 891 /* 892 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 893 * support 894 */ 895 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 896 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 897 SVGA3D_DEVCAP_SM41); 898 dev_priv->has_sm4_1 = vmw_read(dev_priv, 899 SVGA_REG_DEV_CAP); 900 } 901 } 902 903 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 904 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 905 ? "yes." : "no."); 906 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 907 908 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 909 VMWGFX_REPO, VMWGFX_GIT_VERSION); 910 vmw_host_log(host_log); 911 912 memset(host_log, 0, sizeof(host_log)); 913 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 914 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 915 VMWGFX_DRIVER_PATCHLEVEL); 916 vmw_host_log(host_log); 917 918 if (dev_priv->enable_fb) { 919 vmw_fifo_resource_inc(dev_priv); 920 vmw_svga_enable(dev_priv); 921 vmw_fb_init(dev_priv); 922 } 923 924 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 925 register_pm_notifier(&dev_priv->pm_nb); 926 927 return 0; 928 929 out_no_fifo: 930 vmw_overlay_close(dev_priv); 931 vmw_kms_close(dev_priv); 932 out_no_kms: 933 if (dev_priv->has_mob) 934 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 935 if (dev_priv->has_gmr) 936 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 937 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 938 out_no_vram: 939 (void)ttm_bo_device_release(&dev_priv->bdev); 940 out_no_bdev: 941 vmw_fence_manager_takedown(dev_priv->fman); 942 out_no_fman: 943 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 944 vmw_irq_uninstall(dev_priv->dev); 945 out_no_irq: 946 if (dev_priv->stealth) 947 pci_release_region(dev->pdev, 2); 948 else 949 pci_release_regions(dev->pdev); 950 out_no_device: 951 ttm_object_device_release(&dev_priv->tdev); 952 out_err4: 953 memunmap(dev_priv->mmio_virt); 954 out_err0: 955 for (i = vmw_res_context; i < vmw_res_max; ++i) 956 idr_destroy(&dev_priv->res_idr[i]); 957 958 if (dev_priv->ctx.staged_bindings) 959 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 960 kfree(dev_priv); 961 return ret; 962 } 963 964 static void vmw_driver_unload(struct drm_device *dev) 965 { 966 struct vmw_private *dev_priv = vmw_priv(dev); 967 enum vmw_res_type i; 968 969 unregister_pm_notifier(&dev_priv->pm_nb); 970 971 if (dev_priv->ctx.res_ht_initialized) 972 drm_ht_remove(&dev_priv->ctx.res_ht); 973 vfree(dev_priv->ctx.cmd_bounce); 974 if (dev_priv->enable_fb) { 975 vmw_fb_off(dev_priv); 976 vmw_fb_close(dev_priv); 977 vmw_fifo_resource_dec(dev_priv); 978 vmw_svga_disable(dev_priv); 979 } 980 981 vmw_kms_close(dev_priv); 982 vmw_overlay_close(dev_priv); 983 984 if (dev_priv->has_gmr) 985 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 986 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 987 988 vmw_release_device_early(dev_priv); 989 if (dev_priv->has_mob) 990 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 991 (void) ttm_bo_device_release(&dev_priv->bdev); 992 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 993 vmw_release_device_late(dev_priv); 994 vmw_fence_manager_takedown(dev_priv->fman); 995 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 996 vmw_irq_uninstall(dev_priv->dev); 997 if (dev_priv->stealth) 998 pci_release_region(dev->pdev, 2); 999 else 1000 pci_release_regions(dev->pdev); 1001 1002 ttm_object_device_release(&dev_priv->tdev); 1003 memunmap(dev_priv->mmio_virt); 1004 if (dev_priv->ctx.staged_bindings) 1005 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1006 1007 for (i = vmw_res_context; i < vmw_res_max; ++i) 1008 idr_destroy(&dev_priv->res_idr[i]); 1009 1010 kfree(dev_priv); 1011 } 1012 1013 static void vmw_postclose(struct drm_device *dev, 1014 struct drm_file *file_priv) 1015 { 1016 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1017 1018 ttm_object_file_release(&vmw_fp->tfile); 1019 kfree(vmw_fp); 1020 } 1021 1022 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1023 { 1024 struct vmw_private *dev_priv = vmw_priv(dev); 1025 struct vmw_fpriv *vmw_fp; 1026 int ret = -ENOMEM; 1027 1028 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1029 if (unlikely(!vmw_fp)) 1030 return ret; 1031 1032 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1033 if (unlikely(vmw_fp->tfile == NULL)) 1034 goto out_no_tfile; 1035 1036 file_priv->driver_priv = vmw_fp; 1037 1038 return 0; 1039 1040 out_no_tfile: 1041 kfree(vmw_fp); 1042 return ret; 1043 } 1044 1045 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1046 unsigned long arg, 1047 long (*ioctl_func)(struct file *, unsigned int, 1048 unsigned long)) 1049 { 1050 struct drm_file *file_priv = filp->private_data; 1051 struct drm_device *dev = file_priv->minor->dev; 1052 unsigned int nr = DRM_IOCTL_NR(cmd); 1053 unsigned int flags; 1054 1055 /* 1056 * Do extra checking on driver private ioctls. 1057 */ 1058 1059 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1060 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1061 const struct drm_ioctl_desc *ioctl = 1062 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1063 1064 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1065 return ioctl_func(filp, cmd, arg); 1066 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1067 if (!drm_is_current_master(file_priv) && 1068 !capable(CAP_SYS_ADMIN)) 1069 return -EACCES; 1070 } 1071 1072 if (unlikely(ioctl->cmd != cmd)) 1073 goto out_io_encoding; 1074 1075 flags = ioctl->flags; 1076 } else if (!drm_ioctl_flags(nr, &flags)) 1077 return -EINVAL; 1078 1079 return ioctl_func(filp, cmd, arg); 1080 1081 out_io_encoding: 1082 DRM_ERROR("Invalid command format, ioctl %d\n", 1083 nr - DRM_COMMAND_BASE); 1084 1085 return -EINVAL; 1086 } 1087 1088 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1089 unsigned long arg) 1090 { 1091 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1092 } 1093 1094 #ifdef CONFIG_COMPAT 1095 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1096 unsigned long arg) 1097 { 1098 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1099 } 1100 #endif 1101 1102 static int vmw_master_set(struct drm_device *dev, 1103 struct drm_file *file_priv, 1104 bool from_open) 1105 { 1106 /* 1107 * Inform a new master that the layout may have changed while 1108 * it was gone. 1109 */ 1110 if (!from_open) 1111 drm_sysfs_hotplug_event(dev); 1112 1113 return 0; 1114 } 1115 1116 static void vmw_master_drop(struct drm_device *dev, 1117 struct drm_file *file_priv) 1118 { 1119 struct vmw_private *dev_priv = vmw_priv(dev); 1120 1121 vmw_kms_legacy_hotspot_clear(dev_priv); 1122 if (!dev_priv->enable_fb) 1123 vmw_svga_disable(dev_priv); 1124 } 1125 1126 /** 1127 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1128 * 1129 * @dev_priv: Pointer to device private struct. 1130 * Needs the reservation sem to be held in non-exclusive mode. 1131 */ 1132 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1133 { 1134 spin_lock(&dev_priv->svga_lock); 1135 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1136 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1137 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1138 } 1139 spin_unlock(&dev_priv->svga_lock); 1140 } 1141 1142 /** 1143 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1144 * 1145 * @dev_priv: Pointer to device private struct. 1146 */ 1147 void vmw_svga_enable(struct vmw_private *dev_priv) 1148 { 1149 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1150 __vmw_svga_enable(dev_priv); 1151 ttm_read_unlock(&dev_priv->reservation_sem); 1152 } 1153 1154 /** 1155 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1156 * 1157 * @dev_priv: Pointer to device private struct. 1158 * Needs the reservation sem to be held in exclusive mode. 1159 * Will not empty VRAM. VRAM must be emptied by caller. 1160 */ 1161 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1162 { 1163 spin_lock(&dev_priv->svga_lock); 1164 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1165 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1166 vmw_write(dev_priv, SVGA_REG_ENABLE, 1167 SVGA_REG_ENABLE_HIDE | 1168 SVGA_REG_ENABLE_ENABLE); 1169 } 1170 spin_unlock(&dev_priv->svga_lock); 1171 } 1172 1173 /** 1174 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1175 * running. 1176 * 1177 * @dev_priv: Pointer to device private struct. 1178 * Will empty VRAM. 1179 */ 1180 void vmw_svga_disable(struct vmw_private *dev_priv) 1181 { 1182 /* 1183 * Disabling SVGA will turn off device modesetting capabilities, so 1184 * notify KMS about that so that it doesn't cache atomic state that 1185 * isn't valid anymore, for example crtcs turned on. 1186 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1187 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1188 * end up with lock order reversal. Thus, a master may actually perform 1189 * a new modeset just after we call vmw_kms_lost_device() and race with 1190 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1191 * to be inconsistent with the device, causing modesetting problems. 1192 * 1193 */ 1194 vmw_kms_lost_device(dev_priv->dev); 1195 ttm_write_lock(&dev_priv->reservation_sem, false); 1196 spin_lock(&dev_priv->svga_lock); 1197 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1198 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1199 spin_unlock(&dev_priv->svga_lock); 1200 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1201 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1202 vmw_write(dev_priv, SVGA_REG_ENABLE, 1203 SVGA_REG_ENABLE_HIDE | 1204 SVGA_REG_ENABLE_ENABLE); 1205 } else 1206 spin_unlock(&dev_priv->svga_lock); 1207 ttm_write_unlock(&dev_priv->reservation_sem); 1208 } 1209 1210 static void vmw_remove(struct pci_dev *pdev) 1211 { 1212 struct drm_device *dev = pci_get_drvdata(pdev); 1213 1214 pci_disable_device(pdev); 1215 drm_put_dev(dev); 1216 } 1217 1218 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1219 void *ptr) 1220 { 1221 struct vmw_private *dev_priv = 1222 container_of(nb, struct vmw_private, pm_nb); 1223 1224 switch (val) { 1225 case PM_HIBERNATION_PREPARE: 1226 /* 1227 * Take the reservation sem in write mode, which will make sure 1228 * there are no other processes holding a buffer object 1229 * reservation, meaning we should be able to evict all buffer 1230 * objects if needed. 1231 * Once user-space processes have been frozen, we can release 1232 * the lock again. 1233 */ 1234 ttm_suspend_lock(&dev_priv->reservation_sem); 1235 dev_priv->suspend_locked = true; 1236 break; 1237 case PM_POST_HIBERNATION: 1238 case PM_POST_RESTORE: 1239 if (READ_ONCE(dev_priv->suspend_locked)) { 1240 dev_priv->suspend_locked = false; 1241 ttm_suspend_unlock(&dev_priv->reservation_sem); 1242 } 1243 break; 1244 default: 1245 break; 1246 } 1247 return 0; 1248 } 1249 1250 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1251 { 1252 struct drm_device *dev = pci_get_drvdata(pdev); 1253 struct vmw_private *dev_priv = vmw_priv(dev); 1254 1255 if (dev_priv->refuse_hibernation) 1256 return -EBUSY; 1257 1258 pci_save_state(pdev); 1259 pci_disable_device(pdev); 1260 pci_set_power_state(pdev, PCI_D3hot); 1261 return 0; 1262 } 1263 1264 static int vmw_pci_resume(struct pci_dev *pdev) 1265 { 1266 pci_set_power_state(pdev, PCI_D0); 1267 pci_restore_state(pdev); 1268 return pci_enable_device(pdev); 1269 } 1270 1271 static int vmw_pm_suspend(struct device *kdev) 1272 { 1273 struct pci_dev *pdev = to_pci_dev(kdev); 1274 struct pm_message dummy; 1275 1276 dummy.event = 0; 1277 1278 return vmw_pci_suspend(pdev, dummy); 1279 } 1280 1281 static int vmw_pm_resume(struct device *kdev) 1282 { 1283 struct pci_dev *pdev = to_pci_dev(kdev); 1284 1285 return vmw_pci_resume(pdev); 1286 } 1287 1288 static int vmw_pm_freeze(struct device *kdev) 1289 { 1290 struct pci_dev *pdev = to_pci_dev(kdev); 1291 struct drm_device *dev = pci_get_drvdata(pdev); 1292 struct vmw_private *dev_priv = vmw_priv(dev); 1293 int ret; 1294 1295 /* 1296 * Unlock for vmw_kms_suspend. 1297 * No user-space processes should be running now. 1298 */ 1299 ttm_suspend_unlock(&dev_priv->reservation_sem); 1300 ret = vmw_kms_suspend(dev_priv->dev); 1301 if (ret) { 1302 ttm_suspend_lock(&dev_priv->reservation_sem); 1303 DRM_ERROR("Failed to freeze modesetting.\n"); 1304 return ret; 1305 } 1306 if (dev_priv->enable_fb) 1307 vmw_fb_off(dev_priv); 1308 1309 ttm_suspend_lock(&dev_priv->reservation_sem); 1310 vmw_execbuf_release_pinned_bo(dev_priv); 1311 vmw_resource_evict_all(dev_priv); 1312 vmw_release_device_early(dev_priv); 1313 ttm_bo_swapout_all(&dev_priv->bdev); 1314 if (dev_priv->enable_fb) 1315 vmw_fifo_resource_dec(dev_priv); 1316 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1317 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1318 if (dev_priv->enable_fb) 1319 vmw_fifo_resource_inc(dev_priv); 1320 WARN_ON(vmw_request_device_late(dev_priv)); 1321 dev_priv->suspend_locked = false; 1322 ttm_suspend_unlock(&dev_priv->reservation_sem); 1323 if (dev_priv->suspend_state) 1324 vmw_kms_resume(dev); 1325 if (dev_priv->enable_fb) 1326 vmw_fb_on(dev_priv); 1327 return -EBUSY; 1328 } 1329 1330 vmw_fence_fifo_down(dev_priv->fman); 1331 __vmw_svga_disable(dev_priv); 1332 1333 vmw_release_device_late(dev_priv); 1334 return 0; 1335 } 1336 1337 static int vmw_pm_restore(struct device *kdev) 1338 { 1339 struct pci_dev *pdev = to_pci_dev(kdev); 1340 struct drm_device *dev = pci_get_drvdata(pdev); 1341 struct vmw_private *dev_priv = vmw_priv(dev); 1342 int ret; 1343 1344 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1345 (void) vmw_read(dev_priv, SVGA_REG_ID); 1346 1347 if (dev_priv->enable_fb) 1348 vmw_fifo_resource_inc(dev_priv); 1349 1350 ret = vmw_request_device(dev_priv); 1351 if (ret) 1352 return ret; 1353 1354 if (dev_priv->enable_fb) 1355 __vmw_svga_enable(dev_priv); 1356 1357 vmw_fence_fifo_up(dev_priv->fman); 1358 dev_priv->suspend_locked = false; 1359 ttm_suspend_unlock(&dev_priv->reservation_sem); 1360 if (dev_priv->suspend_state) 1361 vmw_kms_resume(dev_priv->dev); 1362 1363 if (dev_priv->enable_fb) 1364 vmw_fb_on(dev_priv); 1365 1366 return 0; 1367 } 1368 1369 static const struct dev_pm_ops vmw_pm_ops = { 1370 .freeze = vmw_pm_freeze, 1371 .thaw = vmw_pm_restore, 1372 .restore = vmw_pm_restore, 1373 .suspend = vmw_pm_suspend, 1374 .resume = vmw_pm_resume, 1375 }; 1376 1377 static const struct file_operations vmwgfx_driver_fops = { 1378 .owner = THIS_MODULE, 1379 .open = drm_open, 1380 .release = drm_release, 1381 .unlocked_ioctl = vmw_unlocked_ioctl, 1382 .mmap = vmw_mmap, 1383 .poll = vmw_fops_poll, 1384 .read = vmw_fops_read, 1385 #if defined(CONFIG_COMPAT) 1386 .compat_ioctl = vmw_compat_ioctl, 1387 #endif 1388 .llseek = noop_llseek, 1389 }; 1390 1391 static struct drm_driver driver = { 1392 .driver_features = 1393 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1394 .load = vmw_driver_load, 1395 .unload = vmw_driver_unload, 1396 .get_vblank_counter = vmw_get_vblank_counter, 1397 .enable_vblank = vmw_enable_vblank, 1398 .disable_vblank = vmw_disable_vblank, 1399 .ioctls = vmw_ioctls, 1400 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1401 .master_set = vmw_master_set, 1402 .master_drop = vmw_master_drop, 1403 .open = vmw_driver_open, 1404 .postclose = vmw_postclose, 1405 1406 .dumb_create = vmw_dumb_create, 1407 .dumb_map_offset = vmw_dumb_map_offset, 1408 .dumb_destroy = vmw_dumb_destroy, 1409 1410 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1411 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1412 1413 .fops = &vmwgfx_driver_fops, 1414 .name = VMWGFX_DRIVER_NAME, 1415 .desc = VMWGFX_DRIVER_DESC, 1416 .date = VMWGFX_DRIVER_DATE, 1417 .major = VMWGFX_DRIVER_MAJOR, 1418 .minor = VMWGFX_DRIVER_MINOR, 1419 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1420 }; 1421 1422 static struct pci_driver vmw_pci_driver = { 1423 .name = VMWGFX_DRIVER_NAME, 1424 .id_table = vmw_pci_id_list, 1425 .probe = vmw_probe, 1426 .remove = vmw_remove, 1427 .driver = { 1428 .pm = &vmw_pm_ops 1429 } 1430 }; 1431 1432 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1433 { 1434 return drm_get_pci_dev(pdev, ent, &driver); 1435 } 1436 1437 static int __init vmwgfx_init(void) 1438 { 1439 int ret; 1440 1441 if (vgacon_text_force()) 1442 return -EINVAL; 1443 1444 ret = pci_register_driver(&vmw_pci_driver); 1445 if (ret) 1446 DRM_ERROR("Failed initializing DRM.\n"); 1447 return ret; 1448 } 1449 1450 static void __exit vmwgfx_exit(void) 1451 { 1452 pci_unregister_driver(&vmw_pci_driver); 1453 } 1454 1455 module_init(vmwgfx_init); 1456 module_exit(vmwgfx_exit); 1457 1458 MODULE_AUTHOR("VMware Inc. and others"); 1459 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1460 MODULE_LICENSE("GPL and additional rights"); 1461 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1462 __stringify(VMWGFX_DRIVER_MINOR) "." 1463 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1464 "0"); 1465