1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_TYPES_H_ 7 #define _XE_GT_TYPES_H_ 8 9 #include "xe_force_wake_types.h" 10 #include "xe_gt_idle_types.h" 11 #include "xe_hw_engine_types.h" 12 #include "xe_hw_fence_types.h" 13 #include "xe_reg_sr_types.h" 14 #include "xe_sa_types.h" 15 #include "xe_uc_types.h" 16 17 struct xe_exec_queue_ops; 18 struct xe_migrate; 19 struct xe_ring_ops; 20 21 enum xe_gt_type { 22 XE_GT_TYPE_UNINITIALIZED, 23 XE_GT_TYPE_MAIN, 24 XE_GT_TYPE_MEDIA, 25 }; 26 27 #define XE_MAX_DSS_FUSE_REGS 3 28 #define XE_MAX_EU_FUSE_REGS 1 29 30 typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)]; 31 typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)]; 32 33 struct xe_mmio_range { 34 u32 start; 35 u32 end; 36 }; 37 38 /* 39 * The hardware has multiple kinds of multicast register ranges that need 40 * special register steering (and future platforms are expected to add 41 * additional types). 42 * 43 * During driver startup, we initialize the steering control register to 44 * direct reads to a slice/subslice that are valid for the 'subslice' class 45 * of multicast registers. If another type of steering does not have any 46 * overlap in valid steering targets with 'subslice' style registers, we will 47 * need to explicitly re-steer reads of registers of the other type. 48 * 49 * Only the replication types that may need additional non-default steering 50 * are listed here. 51 */ 52 enum xe_steering_type { 53 L3BANK, 54 MSLICE, 55 LNCF, 56 DSS, 57 OADDRM, 58 SQIDI_PSMI, 59 60 /* 61 * On some platforms there are multiple types of MCR registers that 62 * will always return a non-terminated value at instance (0, 0). We'll 63 * lump those all into a single category to keep things simple. 64 */ 65 INSTANCE0, 66 67 /* 68 * Register ranges that don't need special steering for each register: 69 * it's sufficient to keep the HW-default for the selector, or only 70 * change it once, on GT initialization. This needs to be the last 71 * steering type. 72 */ 73 IMPLICIT_STEERING, 74 NUM_STEERING_TYPES 75 }; 76 77 #define gt_to_tile(gt__) \ 78 _Generic(gt__, \ 79 const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \ 80 struct xe_gt * : (gt__)->tile) 81 82 #define gt_to_xe(gt__) \ 83 _Generic(gt__, \ 84 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \ 85 struct xe_gt * : gt_to_tile(gt__)->xe) 86 87 /** 88 * struct xe_gt - A "Graphics Technology" unit of the GPU 89 * 90 * A GT ("Graphics Technology") is the subset of a GPU primarily responsible 91 * for implementing the graphics, compute, and/or media IP. It encapsulates 92 * the hardware engines, programmable execution units, and GuC. Each GT has 93 * its own handling of power management (RC6+forcewake) and multicast register 94 * steering. 95 * 96 * A GPU/tile may have a single GT that supplies all graphics, compute, and 97 * media functionality, or the graphics/compute and media may be split into 98 * separate GTs within a tile. 99 */ 100 struct xe_gt { 101 /** @tile: Backpointer to GT's tile */ 102 struct xe_tile *tile; 103 104 /** @info: GT info */ 105 struct { 106 /** @type: type of GT */ 107 enum xe_gt_type type; 108 /** @id: Unique ID of this GT within the PCI Device */ 109 u8 id; 110 /** @reference_clock: clock frequency */ 111 u32 reference_clock; 112 /** @engine_mask: mask of engines present on GT */ 113 u64 engine_mask; 114 /** 115 * @__engine_mask: mask of engines present on GT read from 116 * xe_pci.c, used to fake reading the engine_mask from the 117 * hwconfig blob. 118 */ 119 u64 __engine_mask; 120 } info; 121 122 /** 123 * @mmio: mmio info for GT. All GTs within a tile share the same 124 * register space, but have their own copy of GSI registers at a 125 * specific offset, as well as their own forcewake handling. 126 */ 127 struct { 128 /** @fw: force wake for GT */ 129 struct xe_force_wake fw; 130 /** 131 * @adj_limit: adjust MMIO address if address is below this 132 * value 133 */ 134 u32 adj_limit; 135 /** @adj_offset: offect to add to MMIO address when adjusting */ 136 u32 adj_offset; 137 } mmio; 138 139 /** 140 * @reg_sr: table with registers to be restored on GT init/resume/reset 141 */ 142 struct xe_reg_sr reg_sr; 143 144 /** @reset: state for GT resets */ 145 struct { 146 /** 147 * @worker: work so GT resets can done async allowing to reset 148 * code to safely flush all code paths 149 */ 150 struct work_struct worker; 151 } reset; 152 153 /** @tlb_invalidation: TLB invalidation state */ 154 struct { 155 /** @seqno: TLB invalidation seqno, protected by CT lock */ 156 #define TLB_INVALIDATION_SEQNO_MAX 0x100000 157 int seqno; 158 /** 159 * @seqno_recv: last received TLB invalidation seqno, protected by CT lock 160 */ 161 int seqno_recv; 162 /** 163 * @pending_fences: list of pending fences waiting TLB 164 * invaliations, protected by CT lock 165 */ 166 struct list_head pending_fences; 167 /** 168 * @pending_lock: protects @pending_fences and updating 169 * @seqno_recv. 170 */ 171 spinlock_t pending_lock; 172 /** 173 * @fence_tdr: schedules a delayed call to 174 * xe_gt_tlb_fence_timeout after the timeut interval is over. 175 */ 176 struct delayed_work fence_tdr; 177 /** @fence_context: context for TLB invalidation fences */ 178 u64 fence_context; 179 /** 180 * @fence_seqno: seqno to TLB invalidation fences, protected by 181 * tlb_invalidation.lock 182 */ 183 u32 fence_seqno; 184 /** @lock: protects TLB invalidation fences */ 185 spinlock_t lock; 186 } tlb_invalidation; 187 188 /** 189 * @ccs_mode: Number of compute engines enabled. 190 * Allows fixed mapping of available compute slices to compute engines. 191 * By default only the first available compute engine is enabled and all 192 * available compute slices are allocated to it. 193 */ 194 u32 ccs_mode; 195 196 /** @usm: unified shared memory state */ 197 struct { 198 /** 199 * @bb_pool: Pool from which batchbuffers, for USM operations 200 * (e.g. migrations, fixing page tables), are allocated. 201 * Dedicated pool needed so USM operations to not get blocked 202 * behind any user operations which may have resulted in a 203 * fault. 204 */ 205 struct xe_sa_manager *bb_pool; 206 /** 207 * @reserved_bcs_instance: reserved BCS instance used for USM 208 * operations (e.g. mmigrations, fixing page tables) 209 */ 210 u16 reserved_bcs_instance; 211 /** @pf_wq: page fault work queue, unbound, high priority */ 212 struct workqueue_struct *pf_wq; 213 /** @acc_wq: access counter work queue, unbound, high priority */ 214 struct workqueue_struct *acc_wq; 215 /** 216 * @pf_queue: Page fault queue used to sync faults so faults can 217 * be processed not under the GuC CT lock. The queue is sized so 218 * it can sync all possible faults (1 per physical engine). 219 * Multiple queues exists for page faults from different VMs are 220 * be processed in parallel. 221 */ 222 struct pf_queue { 223 /** @gt: back pointer to GT */ 224 struct xe_gt *gt; 225 #define PF_QUEUE_NUM_DW 128 226 /** @data: data in the page fault queue */ 227 u32 data[PF_QUEUE_NUM_DW]; 228 /** 229 * @head: head pointer in DWs for page fault queue, 230 * moved by worker which processes faults. 231 */ 232 u16 head; 233 /** 234 * @tail: tail pointer in DWs for page fault queue, 235 * moved by G2H handler. 236 */ 237 u16 tail; 238 /** @lock: protects page fault queue */ 239 spinlock_t lock; 240 /** @worker: to process page faults */ 241 struct work_struct worker; 242 #define NUM_PF_QUEUE 4 243 } pf_queue[NUM_PF_QUEUE]; 244 /** 245 * @acc_queue: Same as page fault queue, cannot process access 246 * counters under CT lock. 247 */ 248 struct acc_queue { 249 /** @gt: back pointer to GT */ 250 struct xe_gt *gt; 251 #define ACC_QUEUE_NUM_DW 128 252 /** @data: data in the page fault queue */ 253 u32 data[ACC_QUEUE_NUM_DW]; 254 /** 255 * @head: head pointer in DWs for page fault queue, 256 * moved by worker which processes faults. 257 */ 258 u16 head; 259 /** 260 * @tail: tail pointer in DWs for page fault queue, 261 * moved by G2H handler. 262 */ 263 u16 tail; 264 /** @lock: protects page fault queue */ 265 spinlock_t lock; 266 /** @worker: to process access counters */ 267 struct work_struct worker; 268 #define NUM_ACC_QUEUE 4 269 } acc_queue[NUM_ACC_QUEUE]; 270 } usm; 271 272 /** @ordered_wq: used to serialize GT resets and TDRs */ 273 struct workqueue_struct *ordered_wq; 274 275 /** @uc: micro controllers on the GT */ 276 struct xe_uc uc; 277 278 /** @gtidle: idle properties of GT */ 279 struct xe_gt_idle gtidle; 280 281 /** @exec_queue_ops: submission backend exec queue operations */ 282 const struct xe_exec_queue_ops *exec_queue_ops; 283 284 /** 285 * @ring_ops: ring operations for this hw engine (1 per engine class) 286 */ 287 const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX]; 288 289 /** @fence_irq: fence IRQs (1 per engine class) */ 290 struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX]; 291 292 /** @default_lrc: default LRC state */ 293 void *default_lrc[XE_ENGINE_CLASS_MAX]; 294 295 /** @hw_engines: hardware engines on the GT */ 296 struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES]; 297 298 /** @eclass: per hardware engine class interface on the GT */ 299 struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX]; 300 301 /** @pcode: GT's PCODE */ 302 struct { 303 /** @lock: protecting GT's PCODE mailbox data */ 304 struct mutex lock; 305 } pcode; 306 307 /** @sysfs: sysfs' kobj used by xe_gt_sysfs */ 308 struct kobject *sysfs; 309 310 /** @freq: Main GT freq sysfs control */ 311 struct kobject *freq; 312 313 /** @mocs: info */ 314 struct { 315 /** @uc_index: UC index */ 316 u8 uc_index; 317 /** @wb_index: WB index, only used on L3_CCS platforms */ 318 u8 wb_index; 319 } mocs; 320 321 /** @fuse_topo: GT topology reported by fuse registers */ 322 struct { 323 /** @g_dss_mask: dual-subslices usable by geometry */ 324 xe_dss_mask_t g_dss_mask; 325 326 /** @c_dss_mask: dual-subslices usable by compute */ 327 xe_dss_mask_t c_dss_mask; 328 329 /** @eu_mask_per_dss: EU mask per DSS*/ 330 xe_eu_mask_t eu_mask_per_dss; 331 } fuse_topo; 332 333 /** @steering: register steering for individual HW units */ 334 struct { 335 /* @ranges: register ranges used for this steering type */ 336 const struct xe_mmio_range *ranges; 337 338 /** @group_target: target to steer accesses to */ 339 u16 group_target; 340 /** @instance_target: instance to steer accesses to */ 341 u16 instance_target; 342 } steering[NUM_STEERING_TYPES]; 343 344 /** 345 * @mcr_lock: protects the MCR_SELECTOR register for the duration 346 * of a steered operation 347 */ 348 spinlock_t mcr_lock; 349 350 /** @wa_active: keep track of active workarounds */ 351 struct { 352 /** @gt: bitmap with active GT workarounds */ 353 unsigned long *gt; 354 /** @engine: bitmap with active engine workarounds */ 355 unsigned long *engine; 356 /** @lrc: bitmap with active LRC workarounds */ 357 unsigned long *lrc; 358 /** @oob: bitmap with active OOB workaroudns */ 359 unsigned long *oob; 360 } wa_active; 361 }; 362 363 #endif 364