1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_HW_FENCE_TYPES_H_ 7 #define _XE_HW_FENCE_TYPES_H_ 8 9 #include <linux/dma-fence.h> 10 #include <linux/iosys-map.h> 11 #include <linux/irq_work.h> 12 #include <linux/list.h> 13 #include <linux/spinlock.h> 14 15 struct xe_gt; 16 17 /** 18 * struct xe_hw_fence_irq - hardware fence IRQ handler 19 * 20 * One per engine class, signals completed xe_hw_fences, triggered via hw engine 21 * interrupt. On each trigger, search list of pending fences and signal. 22 */ 23 struct xe_hw_fence_irq { 24 /** @lock: protects all xe_hw_fences + pending list */ 25 spinlock_t lock; 26 /** @work: IRQ worker run to signal the fences */ 27 struct irq_work work; 28 /** @pending: list of pending xe_hw_fences */ 29 struct list_head pending; 30 /** @enabled: fence signaling enabled */ 31 bool enabled; 32 }; 33 34 #define MAX_FENCE_NAME_LEN 16 35 36 /** 37 * struct xe_hw_fence_ctx - hardware fence context 38 * 39 * The context for a hardware fence. 1 to 1 relationship with xe_engine. Points 40 * to a xe_hw_fence_irq, maintains serial seqno. 41 */ 42 struct xe_hw_fence_ctx { 43 /** @gt: graphics tile of hardware fence context */ 44 struct xe_gt *gt; 45 /** @irq: fence irq handler */ 46 struct xe_hw_fence_irq *irq; 47 /** @dma_fence_ctx: dma fence context for hardware fence */ 48 u64 dma_fence_ctx; 49 /** @next_seqno: next seqno for hardware fence */ 50 u32 next_seqno; 51 /** @name: name of hardware fence context */ 52 char name[MAX_FENCE_NAME_LEN]; 53 }; 54 55 /** 56 * struct xe_hw_fence - hardware fence 57 * 58 * Used to indicate a xe_sched_job is complete via a seqno written to memory. 59 * Signals on error or seqno past. 60 */ 61 struct xe_hw_fence { 62 /** @dma: base dma fence for hardware fence context */ 63 struct dma_fence dma; 64 /** @ctx: hardware fence context */ 65 struct xe_hw_fence_ctx *ctx; 66 /** @seqno_map: I/O map for seqno */ 67 struct iosys_map seqno_map; 68 /** @irq_link: Link in struct xe_hw_fence_irq.pending */ 69 struct list_head irq_link; 70 }; 71 72 #endif 73