1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * AMD MP2 PCIe communication driver
4  * Copyright 2020-2021 Advanced Micro Devices, Inc.
5  * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
6  *	    Sandeep Singh <Sandeep.singh@amd.com>
7  *	    Basavaraj Natikar <Basavaraj.Natikar@amd.com>
8  */
9 
10 #ifndef PCIE_MP2_AMD_H
11 #define PCIE_MP2_AMD_H
12 
13 #include <linux/pci.h>
14 #include "amd_sfh_hid.h"
15 
16 #define PCI_DEVICE_ID_AMD_MP2	0x15E4
17 
18 #define ENABLE_SENSOR		1
19 #define DISABLE_SENSOR		2
20 #define STOP_ALL_SENSORS	8
21 
22 /* MP2 C2P Message Registers */
23 #define AMD_C2P_MSG0	0x10500
24 #define AMD_C2P_MSG1	0x10504
25 #define AMD_C2P_MSG2	0x10508
26 
27 #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4))
28 #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4))
29 
30 /* MP2 P2C Message Registers */
31 #define AMD_P2C_MSG3	0x1068C /* Supported Sensors info */
32 
33 #define V2_STATUS	0x2
34 
35 #define SENSOR_ENABLED     4
36 #define SENSOR_DISABLED    5
37 
38 #define HPD_IDX		16
39 
40 #define AMD_SFH_IDLE_LOOP	200
41 
42 /* SFH Command register */
43 union sfh_cmd_base {
44 	u32 ul;
45 	struct {
46 		u32 cmd_id : 8;
47 		u32 sensor_id : 8;
48 		u32 period : 16;
49 	} s;
50 	struct {
51 		u32 cmd_id : 4;
52 		u32 intr_disable : 1;
53 		u32 rsvd1 : 3;
54 		u32 length : 7;
55 		u32 mem_type : 1;
56 		u32 sensor_id : 8;
57 		u32 period : 8;
58 	} cmd_v2;
59 };
60 
61 union cmd_response {
62 	u32 resp;
63 	struct {
64 		u32 status	: 2;
65 		u32 out_in_c2p	: 1;
66 		u32 rsvd1	: 1;
67 		u32 response	: 4;
68 		u32 sub_cmd	: 8;
69 		u32 sensor_id	: 6;
70 		u32 rsvd2	: 10;
71 	} response_v2;
72 };
73 
74 union sfh_cmd_param {
75 	u32 ul;
76 	struct {
77 		u32 buf_layout : 2;
78 		u32 buf_length : 6;
79 		u32 rsvd : 24;
80 	} s;
81 };
82 
83 struct sfh_cmd_reg {
84 	union sfh_cmd_base cmd_base;
85 	union sfh_cmd_param cmd_param;
86 	phys_addr_t phys_addr;
87 };
88 
89 enum sensor_idx {
90 	accel_idx = 0,
91 	gyro_idx = 1,
92 	mag_idx = 2,
93 	als_idx = 19
94 };
95 
96 struct amd_mp2_dev {
97 	struct pci_dev *pdev;
98 	struct amdtp_cl_data *cl_data;
99 	void __iomem *mmio;
100 	const struct amd_mp2_ops *mp2_ops;
101 	struct amd_input_data in_data;
102 	/* mp2 active control status */
103 	u32 mp2_acs;
104 };
105 
106 struct amd_mp2_sensor_info {
107 	u8 sensor_idx;
108 	u32 period;
109 	dma_addr_t dma_address;
110 };
111 
112 enum mem_use_type {
113 	USE_DRAM,
114 	USE_C2P_REG,
115 };
116 
117 struct hpd_status {
118 	union {
119 		struct {
120 			u32 human_presence_report : 4;
121 			u32 human_presence_actual : 4;
122 			u32 probablity		  : 8;
123 			u32 object_distance       : 16;
124 		} shpd;
125 		u32 val;
126 	};
127 };
128 
129 void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
130 void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx);
131 void amd_stop_all_sensors(struct amd_mp2_dev *privdata);
132 int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id);
133 int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata);
134 int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata);
135 u32 amd_sfh_wait_for_response(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts);
136 void amd_mp2_suspend(struct amd_mp2_dev *mp2);
137 void amd_mp2_resume(struct amd_mp2_dev *mp2);
138 
139 struct amd_mp2_ops {
140 	 void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
141 	 void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx);
142 	 void (*stop_all)(struct amd_mp2_dev *privdata);
143 	 int (*response)(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts);
144 	 void (*clear_intr)(struct amd_mp2_dev *privdata);
145 	 int (*init_intr)(struct amd_mp2_dev *privdata);
146 };
147 #endif
148