1d0ddfd24SEugene Shalygin // SPDX-License-Identifier: GPL-2.0+ 2d0ddfd24SEugene Shalygin /* 3d0ddfd24SEugene Shalygin * HWMON driver for ASUS motherboards that publish some sensor values 4d0ddfd24SEugene Shalygin * via the embedded controller registers. 5d0ddfd24SEugene Shalygin * 6d0ddfd24SEugene Shalygin * Copyright (C) 2021 Eugene Shalygin <eugene.shalygin@gmail.com> 7d0ddfd24SEugene Shalygin 8d0ddfd24SEugene Shalygin * EC provides: 9d0ddfd24SEugene Shalygin * - Chipset temperature 10d0ddfd24SEugene Shalygin * - CPU temperature 11d0ddfd24SEugene Shalygin * - Motherboard temperature 12d0ddfd24SEugene Shalygin * - T_Sensor temperature 13d0ddfd24SEugene Shalygin * - VRM temperature 14d0ddfd24SEugene Shalygin * - Water In temperature 15d0ddfd24SEugene Shalygin * - Water Out temperature 16d0ddfd24SEugene Shalygin * - CPU Optional fan RPM 17d0ddfd24SEugene Shalygin * - Chipset fan RPM 18d0ddfd24SEugene Shalygin * - VRM Heat Sink fan RPM 19d0ddfd24SEugene Shalygin * - Water Flow fan RPM 20d0ddfd24SEugene Shalygin * - CPU current 21f545a2fdSEugene Shalygin * - CPU core voltage 22d0ddfd24SEugene Shalygin */ 23d0ddfd24SEugene Shalygin 24d0ddfd24SEugene Shalygin #include <linux/acpi.h> 25d0ddfd24SEugene Shalygin #include <linux/bitops.h> 26d0ddfd24SEugene Shalygin #include <linux/dev_printk.h> 27d0ddfd24SEugene Shalygin #include <linux/dmi.h> 28d0ddfd24SEugene Shalygin #include <linux/hwmon.h> 29d0ddfd24SEugene Shalygin #include <linux/init.h> 30d0ddfd24SEugene Shalygin #include <linux/jiffies.h> 31d0ddfd24SEugene Shalygin #include <linux/kernel.h> 32d0ddfd24SEugene Shalygin #include <linux/module.h> 33d0ddfd24SEugene Shalygin #include <linux/platform_device.h> 34d0ddfd24SEugene Shalygin #include <linux/sort.h> 35d0ddfd24SEugene Shalygin #include <linux/units.h> 36d0ddfd24SEugene Shalygin 37d0ddfd24SEugene Shalygin #include <asm/unaligned.h> 38d0ddfd24SEugene Shalygin 39d0ddfd24SEugene Shalygin static char *mutex_path_override; 40d0ddfd24SEugene Shalygin 41d0ddfd24SEugene Shalygin /* Writing to this EC register switches EC bank */ 42d0ddfd24SEugene Shalygin #define ASUS_EC_BANK_REGISTER 0xff 43d0ddfd24SEugene Shalygin #define SENSOR_LABEL_LEN 16 44d0ddfd24SEugene Shalygin 45d0ddfd24SEugene Shalygin /* 46d0ddfd24SEugene Shalygin * Arbitrary set max. allowed bank number. Required for sorting banks and 47d0ddfd24SEugene Shalygin * currently is overkill with just 2 banks used at max, but for the sake 48d0ddfd24SEugene Shalygin * of alignment let's set it to a higher value. 49d0ddfd24SEugene Shalygin */ 50d0ddfd24SEugene Shalygin #define ASUS_EC_MAX_BANK 3 51d0ddfd24SEugene Shalygin 52d0ddfd24SEugene Shalygin #define ACPI_LOCK_DELAY_MS 500 53d0ddfd24SEugene Shalygin 54d0ddfd24SEugene Shalygin /* ACPI mutex for locking access to the EC for the firmware */ 55d0ddfd24SEugene Shalygin #define ASUS_HW_ACCESS_MUTEX_ASMX "\\AMW0.ASMX" 56d0ddfd24SEugene Shalygin 57bae26b80SShady Nawara #define ASUS_HW_ACCESS_MUTEX_RMTW_ASMX "\\RMTW.ASMX" 58bae26b80SShady Nawara 599992b19dSUrs Schroffenegger #define ASUS_HW_ACCESS_MUTEX_SB_PCI0_SBRG_SIO1_MUT0 "\\_SB_.PCI0.SBRG.SIO1.MUT0" 609992b19dSUrs Schroffenegger 615b4285c5SEugene Shalygin #define MAX_IDENTICAL_BOARD_VARIATIONS 3 62d0ddfd24SEugene Shalygin 63de8fbac5SEugene Shalygin /* Moniker for the ACPI global lock (':' is not allowed in ASL identifiers) */ 64de8fbac5SEugene Shalygin #define ACPI_GLOBAL_LOCK_PSEUDO_PATH ":GLOBAL_LOCK" 65de8fbac5SEugene Shalygin 66d0ddfd24SEugene Shalygin typedef union { 67d0ddfd24SEugene Shalygin u32 value; 68d0ddfd24SEugene Shalygin struct { 69d0ddfd24SEugene Shalygin u8 index; 70d0ddfd24SEugene Shalygin u8 bank; 71d0ddfd24SEugene Shalygin u8 size; 72d0ddfd24SEugene Shalygin u8 dummy; 73d0ddfd24SEugene Shalygin } components; 74d0ddfd24SEugene Shalygin } sensor_address; 75d0ddfd24SEugene Shalygin 76d0ddfd24SEugene Shalygin #define MAKE_SENSOR_ADDRESS(size, bank, index) { \ 77d0ddfd24SEugene Shalygin .value = (size << 16) + (bank << 8) + index \ 78d0ddfd24SEugene Shalygin } 79d0ddfd24SEugene Shalygin 80d0ddfd24SEugene Shalygin static u32 hwmon_attributes[hwmon_max] = { 81d0ddfd24SEugene Shalygin [hwmon_chip] = HWMON_C_REGISTER_TZ, 82d0ddfd24SEugene Shalygin [hwmon_temp] = HWMON_T_INPUT | HWMON_T_LABEL, 83d0ddfd24SEugene Shalygin [hwmon_in] = HWMON_I_INPUT | HWMON_I_LABEL, 84d0ddfd24SEugene Shalygin [hwmon_curr] = HWMON_C_INPUT | HWMON_C_LABEL, 85d0ddfd24SEugene Shalygin [hwmon_fan] = HWMON_F_INPUT | HWMON_F_LABEL, 86d0ddfd24SEugene Shalygin }; 87d0ddfd24SEugene Shalygin 88d0ddfd24SEugene Shalygin struct ec_sensor_info { 89d0ddfd24SEugene Shalygin char label[SENSOR_LABEL_LEN]; 90d0ddfd24SEugene Shalygin enum hwmon_sensor_types type; 91d0ddfd24SEugene Shalygin sensor_address addr; 92d0ddfd24SEugene Shalygin }; 93d0ddfd24SEugene Shalygin 94d0ddfd24SEugene Shalygin #define EC_SENSOR(sensor_label, sensor_type, size, bank, index) { \ 95d0ddfd24SEugene Shalygin .label = sensor_label, .type = sensor_type, \ 96d0ddfd24SEugene Shalygin .addr = MAKE_SENSOR_ADDRESS(size, bank, index), \ 97d0ddfd24SEugene Shalygin } 98d0ddfd24SEugene Shalygin 99d0ddfd24SEugene Shalygin enum ec_sensors { 100d0ddfd24SEugene Shalygin /* chipset temperature [℃] */ 101d0ddfd24SEugene Shalygin ec_sensor_temp_chipset, 102d0ddfd24SEugene Shalygin /* CPU temperature [℃] */ 103d0ddfd24SEugene Shalygin ec_sensor_temp_cpu, 104d0ddfd24SEugene Shalygin /* motherboard temperature [℃] */ 105d0ddfd24SEugene Shalygin ec_sensor_temp_mb, 106d0ddfd24SEugene Shalygin /* "T_Sensor" temperature sensor reading [℃] */ 107d0ddfd24SEugene Shalygin ec_sensor_temp_t_sensor, 108d0ddfd24SEugene Shalygin /* VRM temperature [℃] */ 109d0ddfd24SEugene Shalygin ec_sensor_temp_vrm, 110f545a2fdSEugene Shalygin /* CPU Core voltage [mV] */ 111f545a2fdSEugene Shalygin ec_sensor_in_cpu_core, 112d0ddfd24SEugene Shalygin /* CPU_Opt fan [RPM] */ 113d0ddfd24SEugene Shalygin ec_sensor_fan_cpu_opt, 114d0ddfd24SEugene Shalygin /* VRM heat sink fan [RPM] */ 115d0ddfd24SEugene Shalygin ec_sensor_fan_vrm_hs, 116d0ddfd24SEugene Shalygin /* Chipset fan [RPM] */ 117d0ddfd24SEugene Shalygin ec_sensor_fan_chipset, 118d0ddfd24SEugene Shalygin /* Water flow sensor reading [RPM] */ 119d0ddfd24SEugene Shalygin ec_sensor_fan_water_flow, 120d0ddfd24SEugene Shalygin /* CPU current [A] */ 121d0ddfd24SEugene Shalygin ec_sensor_curr_cpu, 122d0ddfd24SEugene Shalygin /* "Water_In" temperature sensor reading [℃] */ 123d0ddfd24SEugene Shalygin ec_sensor_temp_water_in, 124d0ddfd24SEugene Shalygin /* "Water_Out" temperature sensor reading [℃] */ 125d0ddfd24SEugene Shalygin ec_sensor_temp_water_out, 1269992b19dSUrs Schroffenegger /* "Water_Block_In" temperature sensor reading [℃] */ 1279992b19dSUrs Schroffenegger ec_sensor_temp_water_block_in, 1289992b19dSUrs Schroffenegger /* "Water_Block_Out" temperature sensor reading [℃] */ 1299992b19dSUrs Schroffenegger ec_sensor_temp_water_block_out, 1309992b19dSUrs Schroffenegger /* "T_sensor_2" temperature sensor reading [℃] */ 1319992b19dSUrs Schroffenegger ec_sensor_temp_t_sensor_2, 1329992b19dSUrs Schroffenegger /* "Extra_1" temperature sensor reading [℃] */ 1339992b19dSUrs Schroffenegger ec_sensor_temp_sensor_extra_1, 1349992b19dSUrs Schroffenegger /* "Extra_2" temperature sensor reading [℃] */ 1359992b19dSUrs Schroffenegger ec_sensor_temp_sensor_extra_2, 1369992b19dSUrs Schroffenegger /* "Extra_3" temperature sensor reading [℃] */ 1379992b19dSUrs Schroffenegger ec_sensor_temp_sensor_extra_3, 138d0ddfd24SEugene Shalygin }; 139d0ddfd24SEugene Shalygin 140d0ddfd24SEugene Shalygin #define SENSOR_TEMP_CHIPSET BIT(ec_sensor_temp_chipset) 141d0ddfd24SEugene Shalygin #define SENSOR_TEMP_CPU BIT(ec_sensor_temp_cpu) 142d0ddfd24SEugene Shalygin #define SENSOR_TEMP_MB BIT(ec_sensor_temp_mb) 143d0ddfd24SEugene Shalygin #define SENSOR_TEMP_T_SENSOR BIT(ec_sensor_temp_t_sensor) 144d0ddfd24SEugene Shalygin #define SENSOR_TEMP_VRM BIT(ec_sensor_temp_vrm) 145f545a2fdSEugene Shalygin #define SENSOR_IN_CPU_CORE BIT(ec_sensor_in_cpu_core) 146d0ddfd24SEugene Shalygin #define SENSOR_FAN_CPU_OPT BIT(ec_sensor_fan_cpu_opt) 147d0ddfd24SEugene Shalygin #define SENSOR_FAN_VRM_HS BIT(ec_sensor_fan_vrm_hs) 148d0ddfd24SEugene Shalygin #define SENSOR_FAN_CHIPSET BIT(ec_sensor_fan_chipset) 149d0ddfd24SEugene Shalygin #define SENSOR_FAN_WATER_FLOW BIT(ec_sensor_fan_water_flow) 150d0ddfd24SEugene Shalygin #define SENSOR_CURR_CPU BIT(ec_sensor_curr_cpu) 151d0ddfd24SEugene Shalygin #define SENSOR_TEMP_WATER_IN BIT(ec_sensor_temp_water_in) 152d0ddfd24SEugene Shalygin #define SENSOR_TEMP_WATER_OUT BIT(ec_sensor_temp_water_out) 1539992b19dSUrs Schroffenegger #define SENSOR_TEMP_WATER_BLOCK_IN BIT(ec_sensor_temp_water_block_in) 1549992b19dSUrs Schroffenegger #define SENSOR_TEMP_WATER_BLOCK_OUT BIT(ec_sensor_temp_water_block_out) 1559992b19dSUrs Schroffenegger #define SENSOR_TEMP_T_SENSOR_2 BIT(ec_sensor_temp_t_sensor_2) 1569992b19dSUrs Schroffenegger #define SENSOR_TEMP_SENSOR_EXTRA_1 BIT(ec_sensor_temp_sensor_extra_1) 1579992b19dSUrs Schroffenegger #define SENSOR_TEMP_SENSOR_EXTRA_2 BIT(ec_sensor_temp_sensor_extra_2) 1589992b19dSUrs Schroffenegger #define SENSOR_TEMP_SENSOR_EXTRA_3 BIT(ec_sensor_temp_sensor_extra_3) 159d0ddfd24SEugene Shalygin 16045934e4aSEugene Shalygin enum board_family { 16145934e4aSEugene Shalygin family_unknown, 1627cc44e5aSEugene Shalygin family_amd_400_series, 16345934e4aSEugene Shalygin family_amd_500_series, 1648f9eb10fSMichael Carns family_intel_300_series, 165bae26b80SShady Nawara family_intel_600_series 16645934e4aSEugene Shalygin }; 16745934e4aSEugene Shalygin 168d0ddfd24SEugene Shalygin /* All the known sensors for ASUS EC controllers */ 1697cc44e5aSEugene Shalygin static const struct ec_sensor_info sensors_family_amd_400[] = { 1707cc44e5aSEugene Shalygin [ec_sensor_temp_chipset] = 1717cc44e5aSEugene Shalygin EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a), 1727cc44e5aSEugene Shalygin [ec_sensor_temp_cpu] = 1737cc44e5aSEugene Shalygin EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b), 1747cc44e5aSEugene Shalygin [ec_sensor_temp_mb] = 1757cc44e5aSEugene Shalygin EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c), 1767cc44e5aSEugene Shalygin [ec_sensor_temp_t_sensor] = 1777cc44e5aSEugene Shalygin EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d), 1787cc44e5aSEugene Shalygin [ec_sensor_temp_vrm] = 1797cc44e5aSEugene Shalygin EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 1807cc44e5aSEugene Shalygin [ec_sensor_in_cpu_core] = 1817cc44e5aSEugene Shalygin EC_SENSOR("CPU Core", hwmon_in, 2, 0x00, 0xa2), 1827cc44e5aSEugene Shalygin [ec_sensor_fan_cpu_opt] = 1837cc44e5aSEugene Shalygin EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xbc), 1847cc44e5aSEugene Shalygin [ec_sensor_fan_vrm_hs] = 1857cc44e5aSEugene Shalygin EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2), 1867cc44e5aSEugene Shalygin [ec_sensor_fan_chipset] = 1877cc44e5aSEugene Shalygin /* no chipset fans in this generation */ 1887cc44e5aSEugene Shalygin EC_SENSOR("Chipset", hwmon_fan, 0, 0x00, 0x00), 1897cc44e5aSEugene Shalygin [ec_sensor_fan_water_flow] = 1907cc44e5aSEugene Shalygin EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xb4), 1917cc44e5aSEugene Shalygin [ec_sensor_curr_cpu] = 1927cc44e5aSEugene Shalygin EC_SENSOR("CPU", hwmon_curr, 1, 0x00, 0xf4), 1937cc44e5aSEugene Shalygin [ec_sensor_temp_water_in] = 1947cc44e5aSEugene Shalygin EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x0d), 1957cc44e5aSEugene Shalygin [ec_sensor_temp_water_out] = 1967cc44e5aSEugene Shalygin EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x0b), 1977cc44e5aSEugene Shalygin }; 1987cc44e5aSEugene Shalygin 19945934e4aSEugene Shalygin static const struct ec_sensor_info sensors_family_amd_500[] = { 200d0ddfd24SEugene Shalygin [ec_sensor_temp_chipset] = 201d0ddfd24SEugene Shalygin EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a), 202d0ddfd24SEugene Shalygin [ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b), 203d0ddfd24SEugene Shalygin [ec_sensor_temp_mb] = 204d0ddfd24SEugene Shalygin EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c), 205d0ddfd24SEugene Shalygin [ec_sensor_temp_t_sensor] = 206d0ddfd24SEugene Shalygin EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d), 207d0ddfd24SEugene Shalygin [ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 208f545a2fdSEugene Shalygin [ec_sensor_in_cpu_core] = 209f545a2fdSEugene Shalygin EC_SENSOR("CPU Core", hwmon_in, 2, 0x00, 0xa2), 210d0ddfd24SEugene Shalygin [ec_sensor_fan_cpu_opt] = 211d0ddfd24SEugene Shalygin EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0), 212d0ddfd24SEugene Shalygin [ec_sensor_fan_vrm_hs] = EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2), 213d0ddfd24SEugene Shalygin [ec_sensor_fan_chipset] = 214d0ddfd24SEugene Shalygin EC_SENSOR("Chipset", hwmon_fan, 2, 0x00, 0xb4), 215d0ddfd24SEugene Shalygin [ec_sensor_fan_water_flow] = 216d0ddfd24SEugene Shalygin EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xbc), 217d0ddfd24SEugene Shalygin [ec_sensor_curr_cpu] = EC_SENSOR("CPU", hwmon_curr, 1, 0x00, 0xf4), 218d0ddfd24SEugene Shalygin [ec_sensor_temp_water_in] = 219d0ddfd24SEugene Shalygin EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00), 220d0ddfd24SEugene Shalygin [ec_sensor_temp_water_out] = 221d0ddfd24SEugene Shalygin EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01), 2229992b19dSUrs Schroffenegger [ec_sensor_temp_water_block_in] = 2239992b19dSUrs Schroffenegger EC_SENSOR("Water_Block_In", hwmon_temp, 1, 0x01, 0x02), 2249992b19dSUrs Schroffenegger [ec_sensor_temp_water_block_out] = 2259992b19dSUrs Schroffenegger EC_SENSOR("Water_Block_Out", hwmon_temp, 1, 0x01, 0x03), 2269992b19dSUrs Schroffenegger [ec_sensor_temp_sensor_extra_1] = 2279992b19dSUrs Schroffenegger EC_SENSOR("Extra_1", hwmon_temp, 1, 0x01, 0x09), 2289992b19dSUrs Schroffenegger [ec_sensor_temp_t_sensor_2] = 2299992b19dSUrs Schroffenegger EC_SENSOR("T_sensor_2", hwmon_temp, 1, 0x01, 0x0a), 2309992b19dSUrs Schroffenegger [ec_sensor_temp_sensor_extra_2] = 2319992b19dSUrs Schroffenegger EC_SENSOR("Extra_2", hwmon_temp, 1, 0x01, 0x0b), 2329992b19dSUrs Schroffenegger [ec_sensor_temp_sensor_extra_3] = 2339992b19dSUrs Schroffenegger EC_SENSOR("Extra_3", hwmon_temp, 1, 0x01, 0x0c), 234d0ddfd24SEugene Shalygin }; 235d0ddfd24SEugene Shalygin 2368f9eb10fSMichael Carns static const struct ec_sensor_info sensors_family_intel_300[] = { 2378f9eb10fSMichael Carns [ec_sensor_temp_chipset] = 2388f9eb10fSMichael Carns EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a), 2398f9eb10fSMichael Carns [ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b), 2408f9eb10fSMichael Carns [ec_sensor_temp_mb] = 2418f9eb10fSMichael Carns EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c), 2428f9eb10fSMichael Carns [ec_sensor_temp_t_sensor] = 2438f9eb10fSMichael Carns EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d), 2448f9eb10fSMichael Carns [ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 2458f9eb10fSMichael Carns [ec_sensor_fan_cpu_opt] = 2468f9eb10fSMichael Carns EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0), 2478f9eb10fSMichael Carns [ec_sensor_fan_vrm_hs] = EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2), 2488f9eb10fSMichael Carns [ec_sensor_fan_water_flow] = 2498f9eb10fSMichael Carns EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xbc), 2508f9eb10fSMichael Carns [ec_sensor_temp_water_in] = 2518f9eb10fSMichael Carns EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00), 2528f9eb10fSMichael Carns [ec_sensor_temp_water_out] = 2538f9eb10fSMichael Carns EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01), 2548f9eb10fSMichael Carns }; 2558f9eb10fSMichael Carns 256bae26b80SShady Nawara static const struct ec_sensor_info sensors_family_intel_600[] = { 257bae26b80SShady Nawara [ec_sensor_temp_t_sensor] = 258bae26b80SShady Nawara EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d), 259bae26b80SShady Nawara [ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 260bae26b80SShady Nawara }; 261bae26b80SShady Nawara 262d0ddfd24SEugene Shalygin /* Shortcuts for common combinations */ 263d0ddfd24SEugene Shalygin #define SENSOR_SET_TEMP_CHIPSET_CPU_MB \ 264d0ddfd24SEugene Shalygin (SENSOR_TEMP_CHIPSET | SENSOR_TEMP_CPU | SENSOR_TEMP_MB) 265d0ddfd24SEugene Shalygin #define SENSOR_SET_TEMP_WATER (SENSOR_TEMP_WATER_IN | SENSOR_TEMP_WATER_OUT) 2669992b19dSUrs Schroffenegger #define SENSOR_SET_WATER_BLOCK \ 2679992b19dSUrs Schroffenegger (SENSOR_TEMP_WATER_BLOCK_IN | SENSOR_TEMP_WATER_BLOCK_OUT) 2689992b19dSUrs Schroffenegger 2695cd29012SEugene Shalygin struct ec_board_info { 2705cd29012SEugene Shalygin unsigned long sensors; 271de8fbac5SEugene Shalygin /* 272de8fbac5SEugene Shalygin * Defines which mutex to use for guarding access to the state and the 273de8fbac5SEugene Shalygin * hardware. Can be either a full path to an AML mutex or the 274de8fbac5SEugene Shalygin * pseudo-path ACPI_GLOBAL_LOCK_PSEUDO_PATH to use the global ACPI lock, 275de8fbac5SEugene Shalygin * or left empty to use a regular mutex object, in which case access to 276de8fbac5SEugene Shalygin * the hardware is not guarded. 277de8fbac5SEugene Shalygin */ 278de8fbac5SEugene Shalygin const char *mutex_path; 27945934e4aSEugene Shalygin enum board_family family; 2805cd29012SEugene Shalygin }; 281d0ddfd24SEugene Shalygin 28288700d13SEugene Shalygin static const struct ec_board_info board_info_prime_x470_pro = { 2837cc44e5aSEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 2847cc44e5aSEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM | 2857cc44e5aSEugene Shalygin SENSOR_FAN_CPU_OPT | 2867cc44e5aSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE, 2877cc44e5aSEugene Shalygin .mutex_path = ACPI_GLOBAL_LOCK_PSEUDO_PATH, 2887cc44e5aSEugene Shalygin .family = family_amd_400_series, 28988700d13SEugene Shalygin }; 29088700d13SEugene Shalygin 29188700d13SEugene Shalygin static const struct ec_board_info board_info_prime_x570_pro = { 2925cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM | 2935cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET, 294de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 29545934e4aSEugene Shalygin .family = family_amd_500_series, 29688700d13SEugene Shalygin }; 29788700d13SEugene Shalygin 29888700d13SEugene Shalygin static const struct ec_board_info board_info_pro_art_x570_creator_wifi = { 2995cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM | 300d7cc063fSEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CPU_OPT | 3015cd29012SEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE, 302e2de0e6aSEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 30388700d13SEugene Shalygin .family = family_amd_500_series, 30488700d13SEugene Shalygin }; 30588700d13SEugene Shalygin 30688700d13SEugene Shalygin static const struct ec_board_info board_info_pro_ws_x570_ace = { 3075cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM | 308ab9ac6dfSWei Shuyu SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET | 3095cd29012SEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE, 310de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 31145934e4aSEugene Shalygin .family = family_amd_500_series, 31288700d13SEugene Shalygin }; 31388700d13SEugene Shalygin 31488700d13SEugene Shalygin static const struct ec_board_info board_info_crosshair_viii_dark_hero = { 3155cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3165cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | 317d0ddfd24SEugene Shalygin SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 318f545a2fdSEugene Shalygin SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW | 3195cd29012SEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE, 320de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 32145934e4aSEugene Shalygin .family = family_amd_500_series, 32288700d13SEugene Shalygin }; 32388700d13SEugene Shalygin 32488700d13SEugene Shalygin static const struct ec_board_info board_info_crosshair_viii_hero = { 3255cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3265cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | 3272f66cb5bSEugene Shalygin SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 3282f66cb5bSEugene Shalygin SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET | 3295cd29012SEugene Shalygin SENSOR_FAN_WATER_FLOW | SENSOR_CURR_CPU | 3305cd29012SEugene Shalygin SENSOR_IN_CPU_CORE, 331de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 33245934e4aSEugene Shalygin .family = family_amd_500_series, 33388700d13SEugene Shalygin }; 33488700d13SEugene Shalygin 33588700d13SEugene Shalygin static const struct ec_board_info board_info_maximus_xi_hero = { 3368f9eb10fSMichael Carns .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3378f9eb10fSMichael Carns SENSOR_TEMP_T_SENSOR | 3388f9eb10fSMichael Carns SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 3398f9eb10fSMichael Carns SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW, 3408f9eb10fSMichael Carns .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 3418f9eb10fSMichael Carns .family = family_intel_300_series, 34288700d13SEugene Shalygin }; 34388700d13SEugene Shalygin 34488700d13SEugene Shalygin static const struct ec_board_info board_info_crosshair_viii_impact = { 3455cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3465cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM | 3475cd29012SEugene Shalygin SENSOR_FAN_CHIPSET | SENSOR_CURR_CPU | 3485cd29012SEugene Shalygin SENSOR_IN_CPU_CORE, 349de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 35045934e4aSEugene Shalygin .family = family_amd_500_series, 35188700d13SEugene Shalygin }; 35288700d13SEugene Shalygin 35388700d13SEugene Shalygin static const struct ec_board_info board_info_strix_b550_e_gaming = { 3545cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3555cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM | 3565cd29012SEugene Shalygin SENSOR_FAN_CPU_OPT, 357de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 35845934e4aSEugene Shalygin .family = family_amd_500_series, 35988700d13SEugene Shalygin }; 36088700d13SEugene Shalygin 36188700d13SEugene Shalygin static const struct ec_board_info board_info_strix_b550_i_gaming = { 3625cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3635cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM | 3645cd29012SEugene Shalygin SENSOR_FAN_VRM_HS | SENSOR_CURR_CPU | 3655cd29012SEugene Shalygin SENSOR_IN_CPU_CORE, 366de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 36745934e4aSEugene Shalygin .family = family_amd_500_series, 36888700d13SEugene Shalygin }; 36988700d13SEugene Shalygin 37088700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_e_gaming = { 3715cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3725cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM | 3735cd29012SEugene Shalygin SENSOR_FAN_CHIPSET | SENSOR_CURR_CPU | 3745cd29012SEugene Shalygin SENSOR_IN_CPU_CORE, 375de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 37645934e4aSEugene Shalygin .family = family_amd_500_series, 37788700d13SEugene Shalygin }; 37888700d13SEugene Shalygin 37988700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_e_gaming_wifi_ii = { 3809ccafe46SDebabrata Banerjee .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3819ccafe46SDebabrata Banerjee SENSOR_TEMP_T_SENSOR | SENSOR_CURR_CPU | 3829ccafe46SDebabrata Banerjee SENSOR_IN_CPU_CORE, 3839ccafe46SDebabrata Banerjee .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 3849ccafe46SDebabrata Banerjee .family = family_amd_500_series, 38588700d13SEugene Shalygin }; 38688700d13SEugene Shalygin 38788700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_f_gaming = { 3885cd29012SEugene Shalygin .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | 3895cd29012SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET, 390de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 39145934e4aSEugene Shalygin .family = family_amd_500_series, 39288700d13SEugene Shalygin }; 39388700d13SEugene Shalygin 39488700d13SEugene Shalygin static const struct ec_board_info board_info_strix_x570_i_gaming = { 3951c4e4f4aSEugene Shalygin .sensors = SENSOR_TEMP_CHIPSET | SENSOR_TEMP_VRM | 3961c4e4f4aSEugene Shalygin SENSOR_TEMP_T_SENSOR | 3971c4e4f4aSEugene Shalygin SENSOR_FAN_VRM_HS | SENSOR_FAN_CHIPSET | 3981c4e4f4aSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE, 399de8fbac5SEugene Shalygin .mutex_path = ASUS_HW_ACCESS_MUTEX_ASMX, 40045934e4aSEugene Shalygin .family = family_amd_500_series, 40188700d13SEugene Shalygin }; 40288700d13SEugene Shalygin 40388700d13SEugene Shalygin static const struct ec_board_info board_info_strix_z690_a_gaming_wifi_d4 = { 404bae26b80SShady Nawara .sensors = SENSOR_TEMP_T_SENSOR | SENSOR_TEMP_VRM, 405bae26b80SShady Nawara .mutex_path = ASUS_HW_ACCESS_MUTEX_RMTW_ASMX, 406bae26b80SShady Nawara .family = family_intel_600_series, 40788700d13SEugene Shalygin }; 40888700d13SEugene Shalygin 40988700d13SEugene Shalygin static const struct ec_board_info board_info_zenith_ii_extreme = { 4109992b19dSUrs Schroffenegger .sensors = SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR | 4119992b19dSUrs Schroffenegger SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 4129992b19dSUrs Schroffenegger SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET | SENSOR_FAN_VRM_HS | 4139992b19dSUrs Schroffenegger SENSOR_FAN_WATER_FLOW | SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE | 4149992b19dSUrs Schroffenegger SENSOR_SET_WATER_BLOCK | 4159992b19dSUrs Schroffenegger SENSOR_TEMP_T_SENSOR_2 | SENSOR_TEMP_SENSOR_EXTRA_1 | 4169992b19dSUrs Schroffenegger SENSOR_TEMP_SENSOR_EXTRA_2 | SENSOR_TEMP_SENSOR_EXTRA_3, 4179992b19dSUrs Schroffenegger .mutex_path = ASUS_HW_ACCESS_MUTEX_SB_PCI0_SBRG_SIO1_MUT0, 4189992b19dSUrs Schroffenegger .family = family_amd_500_series, 41988700d13SEugene Shalygin }; 42088700d13SEugene Shalygin 42188700d13SEugene Shalygin #define DMI_EXACT_MATCH_ASUS_BOARD_NAME(name, board_info) \ 42288700d13SEugene Shalygin { \ 42388700d13SEugene Shalygin .matches = { \ 42488700d13SEugene Shalygin DMI_EXACT_MATCH(DMI_BOARD_VENDOR, \ 42588700d13SEugene Shalygin "ASUSTeK COMPUTER INC."), \ 42688700d13SEugene Shalygin DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ 42788700d13SEugene Shalygin }, \ 42888700d13SEugene Shalygin .driver_data = (void *)board_info, \ 42988700d13SEugene Shalygin } 43088700d13SEugene Shalygin 43188700d13SEugene Shalygin static const struct dmi_system_id dmi_table[] = { 43288700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X470-PRO", 43388700d13SEugene Shalygin &board_info_prime_x470_pro), 43488700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("PRIME X570-PRO", 43588700d13SEugene Shalygin &board_info_prime_x570_pro), 43688700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ProArt X570-CREATOR WIFI", 43788700d13SEugene Shalygin &board_info_pro_art_x570_creator_wifi), 43888700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("Pro WS X570-ACE", 43988700d13SEugene Shalygin &board_info_pro_ws_x570_ace), 44088700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII DARK HERO", 44188700d13SEugene Shalygin &board_info_crosshair_viii_dark_hero), 44288700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII FORMULA", 44388700d13SEugene Shalygin &board_info_crosshair_viii_hero), 44488700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII HERO", 44588700d13SEugene Shalygin &board_info_crosshair_viii_hero), 44688700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII HERO (WI-FI)", 44788700d13SEugene Shalygin &board_info_crosshair_viii_hero), 44888700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG MAXIMUS XI HERO", 44988700d13SEugene Shalygin &board_info_maximus_xi_hero), 45088700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG MAXIMUS XI HERO (WI-FI)", 45188700d13SEugene Shalygin &board_info_maximus_xi_hero), 45288700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG CROSSHAIR VIII IMPACT", 45388700d13SEugene Shalygin &board_info_crosshair_viii_impact), 45488700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX B550-E GAMING", 45588700d13SEugene Shalygin &board_info_strix_b550_e_gaming), 45688700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX B550-I GAMING", 45788700d13SEugene Shalygin &board_info_strix_b550_i_gaming), 45888700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-E GAMING", 45988700d13SEugene Shalygin &board_info_strix_x570_e_gaming), 46088700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-E GAMING WIFI II", 46188700d13SEugene Shalygin &board_info_strix_x570_e_gaming_wifi_ii), 46288700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-F GAMING", 46388700d13SEugene Shalygin &board_info_strix_x570_f_gaming), 46488700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX X570-I GAMING", 46588700d13SEugene Shalygin &board_info_strix_x570_i_gaming), 46688700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG STRIX Z690-A GAMING WIFI D4", 46788700d13SEugene Shalygin &board_info_strix_z690_a_gaming_wifi_d4), 46888700d13SEugene Shalygin DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG ZENITH II EXTREME", 46988700d13SEugene Shalygin &board_info_zenith_ii_extreme), 470*195f46e5SEric Nguyen DMI_EXACT_MATCH_ASUS_BOARD_NAME("ROG ZENITH II EXTREME ALPHA", 471*195f46e5SEric Nguyen &board_info_zenith_ii_extreme), 47288700d13SEugene Shalygin {}, 473d0ddfd24SEugene Shalygin }; 474d0ddfd24SEugene Shalygin 475d0ddfd24SEugene Shalygin struct ec_sensor { 476d0ddfd24SEugene Shalygin unsigned int info_index; 477339f8a99SEugene Shalygin s32 cached_value; 478d0ddfd24SEugene Shalygin }; 479d0ddfd24SEugene Shalygin 480de8fbac5SEugene Shalygin struct lock_data { 481de8fbac5SEugene Shalygin union { 482de8fbac5SEugene Shalygin acpi_handle aml; 483de8fbac5SEugene Shalygin /* global lock handle */ 484de8fbac5SEugene Shalygin u32 glk; 485de8fbac5SEugene Shalygin } mutex; 486de8fbac5SEugene Shalygin bool (*lock)(struct lock_data *data); 487de8fbac5SEugene Shalygin bool (*unlock)(struct lock_data *data); 488de8fbac5SEugene Shalygin }; 489de8fbac5SEugene Shalygin 490de8fbac5SEugene Shalygin /* 491de8fbac5SEugene Shalygin * The next function pairs implement options for locking access to the 492de8fbac5SEugene Shalygin * state and the EC 493de8fbac5SEugene Shalygin */ 494de8fbac5SEugene Shalygin static bool lock_via_acpi_mutex(struct lock_data *data) 495de8fbac5SEugene Shalygin { 496de8fbac5SEugene Shalygin /* 497de8fbac5SEugene Shalygin * ASUS DSDT does not specify that access to the EC has to be guarded, 498de8fbac5SEugene Shalygin * but firmware does access it via ACPI 499de8fbac5SEugene Shalygin */ 500de8fbac5SEugene Shalygin return ACPI_SUCCESS(acpi_acquire_mutex(data->mutex.aml, 501de8fbac5SEugene Shalygin NULL, ACPI_LOCK_DELAY_MS)); 502de8fbac5SEugene Shalygin } 503de8fbac5SEugene Shalygin 504de8fbac5SEugene Shalygin static bool unlock_acpi_mutex(struct lock_data *data) 505de8fbac5SEugene Shalygin { 506de8fbac5SEugene Shalygin return ACPI_SUCCESS(acpi_release_mutex(data->mutex.aml, NULL)); 507de8fbac5SEugene Shalygin } 508de8fbac5SEugene Shalygin 509de8fbac5SEugene Shalygin static bool lock_via_global_acpi_lock(struct lock_data *data) 510de8fbac5SEugene Shalygin { 511de8fbac5SEugene Shalygin return ACPI_SUCCESS(acpi_acquire_global_lock(ACPI_LOCK_DELAY_MS, 512de8fbac5SEugene Shalygin &data->mutex.glk)); 513de8fbac5SEugene Shalygin } 514de8fbac5SEugene Shalygin 515de8fbac5SEugene Shalygin static bool unlock_global_acpi_lock(struct lock_data *data) 516de8fbac5SEugene Shalygin { 517de8fbac5SEugene Shalygin return ACPI_SUCCESS(acpi_release_global_lock(data->mutex.glk)); 518de8fbac5SEugene Shalygin } 519de8fbac5SEugene Shalygin 520d0ddfd24SEugene Shalygin struct ec_sensors_data { 5215cd29012SEugene Shalygin const struct ec_board_info *board_info; 52245934e4aSEugene Shalygin const struct ec_sensor_info *sensors_info; 523d0ddfd24SEugene Shalygin struct ec_sensor *sensors; 524d0ddfd24SEugene Shalygin /* EC registers to read from */ 525d0ddfd24SEugene Shalygin u16 *registers; 526d0ddfd24SEugene Shalygin u8 *read_buffer; 527d0ddfd24SEugene Shalygin /* sorted list of unique register banks */ 528d0ddfd24SEugene Shalygin u8 banks[ASUS_EC_MAX_BANK + 1]; 529d0ddfd24SEugene Shalygin /* in jiffies */ 530d0ddfd24SEugene Shalygin unsigned long last_updated; 531de8fbac5SEugene Shalygin struct lock_data lock_data; 532d0ddfd24SEugene Shalygin /* number of board EC sensors */ 533d0ddfd24SEugene Shalygin u8 nr_sensors; 534d0ddfd24SEugene Shalygin /* 535d0ddfd24SEugene Shalygin * number of EC registers to read 536d0ddfd24SEugene Shalygin * (sensor might span more than 1 register) 537d0ddfd24SEugene Shalygin */ 538d0ddfd24SEugene Shalygin u8 nr_registers; 539d0ddfd24SEugene Shalygin /* number of unique register banks */ 540d0ddfd24SEugene Shalygin u8 nr_banks; 541d0ddfd24SEugene Shalygin }; 542d0ddfd24SEugene Shalygin 543d0ddfd24SEugene Shalygin static u8 register_bank(u16 reg) 544d0ddfd24SEugene Shalygin { 545d0ddfd24SEugene Shalygin return reg >> 8; 546d0ddfd24SEugene Shalygin } 547d0ddfd24SEugene Shalygin 548d0ddfd24SEugene Shalygin static u8 register_index(u16 reg) 549d0ddfd24SEugene Shalygin { 550d0ddfd24SEugene Shalygin return reg & 0x00ff; 551d0ddfd24SEugene Shalygin } 552d0ddfd24SEugene Shalygin 5538aba9ca6SEugene Shalygin static bool is_sensor_data_signed(const struct ec_sensor_info *si) 5548aba9ca6SEugene Shalygin { 5558aba9ca6SEugene Shalygin /* 5568aba9ca6SEugene Shalygin * guessed from WMI functions in DSDT code for boards 5578aba9ca6SEugene Shalygin * of the X470 generation 5588aba9ca6SEugene Shalygin */ 5598aba9ca6SEugene Shalygin return si->type == hwmon_temp; 5608aba9ca6SEugene Shalygin } 5618aba9ca6SEugene Shalygin 562d0ddfd24SEugene Shalygin static const struct ec_sensor_info * 563d0ddfd24SEugene Shalygin get_sensor_info(const struct ec_sensors_data *state, int index) 564d0ddfd24SEugene Shalygin { 56545934e4aSEugene Shalygin return state->sensors_info + state->sensors[index].info_index; 566d0ddfd24SEugene Shalygin } 567d0ddfd24SEugene Shalygin 568d0ddfd24SEugene Shalygin static int find_ec_sensor_index(const struct ec_sensors_data *ec, 569d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, int channel) 570d0ddfd24SEugene Shalygin { 571d0ddfd24SEugene Shalygin unsigned int i; 572d0ddfd24SEugene Shalygin 573d0ddfd24SEugene Shalygin for (i = 0; i < ec->nr_sensors; i++) { 574d0ddfd24SEugene Shalygin if (get_sensor_info(ec, i)->type == type) { 575d0ddfd24SEugene Shalygin if (channel == 0) 576d0ddfd24SEugene Shalygin return i; 577d0ddfd24SEugene Shalygin channel--; 578d0ddfd24SEugene Shalygin } 579d0ddfd24SEugene Shalygin } 580d0ddfd24SEugene Shalygin return -ENOENT; 581d0ddfd24SEugene Shalygin } 582d0ddfd24SEugene Shalygin 58388700d13SEugene Shalygin static int bank_compare(const void *a, const void *b) 584d0ddfd24SEugene Shalygin { 585d0ddfd24SEugene Shalygin return *((const s8 *)a) - *((const s8 *)b); 586d0ddfd24SEugene Shalygin } 587d0ddfd24SEugene Shalygin 58888700d13SEugene Shalygin static void setup_sensor_data(struct ec_sensors_data *ec) 589d0ddfd24SEugene Shalygin { 590d0ddfd24SEugene Shalygin struct ec_sensor *s = ec->sensors; 591d0ddfd24SEugene Shalygin bool bank_found; 592d0ddfd24SEugene Shalygin int i, j; 593d0ddfd24SEugene Shalygin u8 bank; 594d0ddfd24SEugene Shalygin 595d0ddfd24SEugene Shalygin ec->nr_banks = 0; 596d0ddfd24SEugene Shalygin ec->nr_registers = 0; 597d0ddfd24SEugene Shalygin 5985cd29012SEugene Shalygin for_each_set_bit(i, &ec->board_info->sensors, 5995cd29012SEugene Shalygin BITS_PER_TYPE(ec->board_info->sensors)) { 600d0ddfd24SEugene Shalygin s->info_index = i; 601d0ddfd24SEugene Shalygin s->cached_value = 0; 602d0ddfd24SEugene Shalygin ec->nr_registers += 60345934e4aSEugene Shalygin ec->sensors_info[s->info_index].addr.components.size; 604d0ddfd24SEugene Shalygin bank_found = false; 60545934e4aSEugene Shalygin bank = ec->sensors_info[s->info_index].addr.components.bank; 606d0ddfd24SEugene Shalygin for (j = 0; j < ec->nr_banks; j++) { 607d0ddfd24SEugene Shalygin if (ec->banks[j] == bank) { 608d0ddfd24SEugene Shalygin bank_found = true; 609d0ddfd24SEugene Shalygin break; 610d0ddfd24SEugene Shalygin } 611d0ddfd24SEugene Shalygin } 612d0ddfd24SEugene Shalygin if (!bank_found) { 613d0ddfd24SEugene Shalygin ec->banks[ec->nr_banks++] = bank; 614d0ddfd24SEugene Shalygin } 615d0ddfd24SEugene Shalygin s++; 616d0ddfd24SEugene Shalygin } 617d0ddfd24SEugene Shalygin sort(ec->banks, ec->nr_banks, 1, bank_compare, NULL); 618d0ddfd24SEugene Shalygin } 619d0ddfd24SEugene Shalygin 62088700d13SEugene Shalygin static void fill_ec_registers(struct ec_sensors_data *ec) 621d0ddfd24SEugene Shalygin { 622d0ddfd24SEugene Shalygin const struct ec_sensor_info *si; 623d0ddfd24SEugene Shalygin unsigned int i, j, register_idx = 0; 624d0ddfd24SEugene Shalygin 625d0ddfd24SEugene Shalygin for (i = 0; i < ec->nr_sensors; ++i) { 626d0ddfd24SEugene Shalygin si = get_sensor_info(ec, i); 627d0ddfd24SEugene Shalygin for (j = 0; j < si->addr.components.size; ++j, ++register_idx) { 628d0ddfd24SEugene Shalygin ec->registers[register_idx] = 629d0ddfd24SEugene Shalygin (si->addr.components.bank << 8) + 630d0ddfd24SEugene Shalygin si->addr.components.index + j; 631d0ddfd24SEugene Shalygin } 632d0ddfd24SEugene Shalygin } 633d0ddfd24SEugene Shalygin } 634d0ddfd24SEugene Shalygin 63588700d13SEugene Shalygin static int setup_lock_data(struct device *dev) 636d0ddfd24SEugene Shalygin { 637d0ddfd24SEugene Shalygin const char *mutex_path; 638d0ddfd24SEugene Shalygin int status; 639de8fbac5SEugene Shalygin struct ec_sensors_data *state = dev_get_drvdata(dev); 640d0ddfd24SEugene Shalygin 641d0ddfd24SEugene Shalygin mutex_path = mutex_path_override ? 642de8fbac5SEugene Shalygin mutex_path_override : state->board_info->mutex_path; 643d0ddfd24SEugene Shalygin 644de8fbac5SEugene Shalygin if (!mutex_path || !strlen(mutex_path)) { 645de8fbac5SEugene Shalygin dev_err(dev, "Hardware access guard mutex name is empty"); 646de8fbac5SEugene Shalygin return -EINVAL; 647de8fbac5SEugene Shalygin } 648de8fbac5SEugene Shalygin if (!strcmp(mutex_path, ACPI_GLOBAL_LOCK_PSEUDO_PATH)) { 649de8fbac5SEugene Shalygin state->lock_data.mutex.glk = 0; 650de8fbac5SEugene Shalygin state->lock_data.lock = lock_via_global_acpi_lock; 651de8fbac5SEugene Shalygin state->lock_data.unlock = unlock_global_acpi_lock; 652de8fbac5SEugene Shalygin } else { 653de8fbac5SEugene Shalygin status = acpi_get_handle(NULL, (acpi_string)mutex_path, 654de8fbac5SEugene Shalygin &state->lock_data.mutex.aml); 655d0ddfd24SEugene Shalygin if (ACPI_FAILURE(status)) { 656d0ddfd24SEugene Shalygin dev_err(dev, 657de8fbac5SEugene Shalygin "Failed to get hardware access guard AML mutex '%s': error %d", 658d0ddfd24SEugene Shalygin mutex_path, status); 659de8fbac5SEugene Shalygin return -ENOENT; 660d0ddfd24SEugene Shalygin } 661de8fbac5SEugene Shalygin state->lock_data.lock = lock_via_acpi_mutex; 662de8fbac5SEugene Shalygin state->lock_data.unlock = unlock_acpi_mutex; 663de8fbac5SEugene Shalygin } 664de8fbac5SEugene Shalygin return 0; 665d0ddfd24SEugene Shalygin } 666d0ddfd24SEugene Shalygin 667d0ddfd24SEugene Shalygin static int asus_ec_bank_switch(u8 bank, u8 *old) 668d0ddfd24SEugene Shalygin { 669d0ddfd24SEugene Shalygin int status = 0; 670d0ddfd24SEugene Shalygin 671d0ddfd24SEugene Shalygin if (old) { 672d0ddfd24SEugene Shalygin status = ec_read(ASUS_EC_BANK_REGISTER, old); 673d0ddfd24SEugene Shalygin } 674d0ddfd24SEugene Shalygin if (status || (old && (*old == bank))) 675d0ddfd24SEugene Shalygin return status; 676d0ddfd24SEugene Shalygin return ec_write(ASUS_EC_BANK_REGISTER, bank); 677d0ddfd24SEugene Shalygin } 678d0ddfd24SEugene Shalygin 679d0ddfd24SEugene Shalygin static int asus_ec_block_read(const struct device *dev, 680d0ddfd24SEugene Shalygin struct ec_sensors_data *ec) 681d0ddfd24SEugene Shalygin { 682d0ddfd24SEugene Shalygin int ireg, ibank, status; 683d0ddfd24SEugene Shalygin u8 bank, reg_bank, prev_bank; 684d0ddfd24SEugene Shalygin 685d0ddfd24SEugene Shalygin bank = 0; 686d0ddfd24SEugene Shalygin status = asus_ec_bank_switch(bank, &prev_bank); 687d0ddfd24SEugene Shalygin if (status) { 688d0ddfd24SEugene Shalygin dev_warn(dev, "EC bank switch failed"); 689d0ddfd24SEugene Shalygin return status; 690d0ddfd24SEugene Shalygin } 691d0ddfd24SEugene Shalygin 692d0ddfd24SEugene Shalygin if (prev_bank) { 693d0ddfd24SEugene Shalygin /* oops... somebody else is working with the EC too */ 694d0ddfd24SEugene Shalygin dev_warn(dev, 695d0ddfd24SEugene Shalygin "Concurrent access to the ACPI EC detected.\nRace condition possible."); 696d0ddfd24SEugene Shalygin } 697d0ddfd24SEugene Shalygin 698d0ddfd24SEugene Shalygin /* read registers minimizing bank switches. */ 699d0ddfd24SEugene Shalygin for (ibank = 0; ibank < ec->nr_banks; ibank++) { 700d0ddfd24SEugene Shalygin if (bank != ec->banks[ibank]) { 701d0ddfd24SEugene Shalygin bank = ec->banks[ibank]; 702d0ddfd24SEugene Shalygin if (asus_ec_bank_switch(bank, NULL)) { 703d0ddfd24SEugene Shalygin dev_warn(dev, "EC bank switch to %d failed", 704d0ddfd24SEugene Shalygin bank); 705d0ddfd24SEugene Shalygin break; 706d0ddfd24SEugene Shalygin } 707d0ddfd24SEugene Shalygin } 708d0ddfd24SEugene Shalygin for (ireg = 0; ireg < ec->nr_registers; ireg++) { 709d0ddfd24SEugene Shalygin reg_bank = register_bank(ec->registers[ireg]); 710d0ddfd24SEugene Shalygin if (reg_bank < bank) { 711d0ddfd24SEugene Shalygin continue; 712d0ddfd24SEugene Shalygin } 713d0ddfd24SEugene Shalygin ec_read(register_index(ec->registers[ireg]), 714d0ddfd24SEugene Shalygin ec->read_buffer + ireg); 715d0ddfd24SEugene Shalygin } 716d0ddfd24SEugene Shalygin } 717d0ddfd24SEugene Shalygin 718d0ddfd24SEugene Shalygin status = asus_ec_bank_switch(prev_bank, NULL); 719d0ddfd24SEugene Shalygin return status; 720d0ddfd24SEugene Shalygin } 721d0ddfd24SEugene Shalygin 722339f8a99SEugene Shalygin static inline s32 get_sensor_value(const struct ec_sensor_info *si, u8 *data) 723d0ddfd24SEugene Shalygin { 7248aba9ca6SEugene Shalygin if (is_sensor_data_signed(si)) { 725d0ddfd24SEugene Shalygin switch (si->addr.components.size) { 726d0ddfd24SEugene Shalygin case 1: 727339f8a99SEugene Shalygin return (s8)*data; 728d0ddfd24SEugene Shalygin case 2: 729339f8a99SEugene Shalygin return (s16)get_unaligned_be16(data); 730d0ddfd24SEugene Shalygin case 4: 731339f8a99SEugene Shalygin return (s32)get_unaligned_be32(data); 732d0ddfd24SEugene Shalygin default: 733d0ddfd24SEugene Shalygin return 0; 734d0ddfd24SEugene Shalygin } 7358aba9ca6SEugene Shalygin } else { 7368aba9ca6SEugene Shalygin switch (si->addr.components.size) { 7378aba9ca6SEugene Shalygin case 1: 7388aba9ca6SEugene Shalygin return *data; 7398aba9ca6SEugene Shalygin case 2: 7408aba9ca6SEugene Shalygin return get_unaligned_be16(data); 7418aba9ca6SEugene Shalygin case 4: 7428aba9ca6SEugene Shalygin return get_unaligned_be32(data); 7438aba9ca6SEugene Shalygin default: 7448aba9ca6SEugene Shalygin return 0; 7458aba9ca6SEugene Shalygin } 7468aba9ca6SEugene Shalygin } 747d0ddfd24SEugene Shalygin } 748d0ddfd24SEugene Shalygin 749d0ddfd24SEugene Shalygin static void update_sensor_values(struct ec_sensors_data *ec, u8 *data) 750d0ddfd24SEugene Shalygin { 751d0ddfd24SEugene Shalygin const struct ec_sensor_info *si; 7525cd29012SEugene Shalygin struct ec_sensor *s, *sensor_end; 753d0ddfd24SEugene Shalygin 7545cd29012SEugene Shalygin sensor_end = ec->sensors + ec->nr_sensors; 7555cd29012SEugene Shalygin for (s = ec->sensors; s != sensor_end; s++) { 75645934e4aSEugene Shalygin si = ec->sensors_info + s->info_index; 757d0ddfd24SEugene Shalygin s->cached_value = get_sensor_value(si, data); 758d0ddfd24SEugene Shalygin data += si->addr.components.size; 759d0ddfd24SEugene Shalygin } 760d0ddfd24SEugene Shalygin } 761d0ddfd24SEugene Shalygin 762d0ddfd24SEugene Shalygin static int update_ec_sensors(const struct device *dev, 763d0ddfd24SEugene Shalygin struct ec_sensors_data *ec) 764d0ddfd24SEugene Shalygin { 765d0ddfd24SEugene Shalygin int status; 766d0ddfd24SEugene Shalygin 767de8fbac5SEugene Shalygin if (!ec->lock_data.lock(&ec->lock_data)) { 768de8fbac5SEugene Shalygin dev_warn(dev, "Failed to acquire mutex"); 769de8fbac5SEugene Shalygin return -EBUSY; 770d0ddfd24SEugene Shalygin } 771d0ddfd24SEugene Shalygin 772d0ddfd24SEugene Shalygin status = asus_ec_block_read(dev, ec); 773d0ddfd24SEugene Shalygin 774d0ddfd24SEugene Shalygin if (!status) { 775d0ddfd24SEugene Shalygin update_sensor_values(ec, ec->read_buffer); 776d0ddfd24SEugene Shalygin } 777de8fbac5SEugene Shalygin 778de8fbac5SEugene Shalygin if (!ec->lock_data.unlock(&ec->lock_data)) 779de8fbac5SEugene Shalygin dev_err(dev, "Failed to release mutex"); 780de8fbac5SEugene Shalygin 781d0ddfd24SEugene Shalygin return status; 782d0ddfd24SEugene Shalygin } 783d0ddfd24SEugene Shalygin 784339f8a99SEugene Shalygin static long scale_sensor_value(s32 value, int data_type) 785d0ddfd24SEugene Shalygin { 786d0ddfd24SEugene Shalygin switch (data_type) { 787d0ddfd24SEugene Shalygin case hwmon_curr: 788d0ddfd24SEugene Shalygin case hwmon_temp: 789d0ddfd24SEugene Shalygin return value * MILLI; 790d0ddfd24SEugene Shalygin default: 791d0ddfd24SEugene Shalygin return value; 792d0ddfd24SEugene Shalygin } 793d0ddfd24SEugene Shalygin } 794d0ddfd24SEugene Shalygin 795d0ddfd24SEugene Shalygin static int get_cached_value_or_update(const struct device *dev, 796d0ddfd24SEugene Shalygin int sensor_index, 797339f8a99SEugene Shalygin struct ec_sensors_data *state, s32 *value) 798d0ddfd24SEugene Shalygin { 799d0ddfd24SEugene Shalygin if (time_after(jiffies, state->last_updated + HZ)) { 800d0ddfd24SEugene Shalygin if (update_ec_sensors(dev, state)) { 801d0ddfd24SEugene Shalygin dev_err(dev, "update_ec_sensors() failure\n"); 802d0ddfd24SEugene Shalygin return -EIO; 803d0ddfd24SEugene Shalygin } 804d0ddfd24SEugene Shalygin 805d0ddfd24SEugene Shalygin state->last_updated = jiffies; 806d0ddfd24SEugene Shalygin } 807d0ddfd24SEugene Shalygin 808d0ddfd24SEugene Shalygin *value = state->sensors[sensor_index].cached_value; 809d0ddfd24SEugene Shalygin return 0; 810d0ddfd24SEugene Shalygin } 811d0ddfd24SEugene Shalygin 812d0ddfd24SEugene Shalygin /* 813d0ddfd24SEugene Shalygin * Now follow the functions that implement the hwmon interface 814d0ddfd24SEugene Shalygin */ 815d0ddfd24SEugene Shalygin 816d0ddfd24SEugene Shalygin static int asus_ec_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 817d0ddfd24SEugene Shalygin u32 attr, int channel, long *val) 818d0ddfd24SEugene Shalygin { 819d0ddfd24SEugene Shalygin int ret; 820339f8a99SEugene Shalygin s32 value = 0; 821d0ddfd24SEugene Shalygin 822d0ddfd24SEugene Shalygin struct ec_sensors_data *state = dev_get_drvdata(dev); 823d0ddfd24SEugene Shalygin int sidx = find_ec_sensor_index(state, type, channel); 824d0ddfd24SEugene Shalygin 825d0ddfd24SEugene Shalygin if (sidx < 0) { 826d0ddfd24SEugene Shalygin return sidx; 827d0ddfd24SEugene Shalygin } 828d0ddfd24SEugene Shalygin 829d0ddfd24SEugene Shalygin ret = get_cached_value_or_update(dev, sidx, state, &value); 830d0ddfd24SEugene Shalygin if (!ret) { 831d0ddfd24SEugene Shalygin *val = scale_sensor_value(value, 832d0ddfd24SEugene Shalygin get_sensor_info(state, sidx)->type); 833d0ddfd24SEugene Shalygin } 834d0ddfd24SEugene Shalygin 835d0ddfd24SEugene Shalygin return ret; 836d0ddfd24SEugene Shalygin } 837d0ddfd24SEugene Shalygin 838d0ddfd24SEugene Shalygin static int asus_ec_hwmon_read_string(struct device *dev, 839d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, u32 attr, 840d0ddfd24SEugene Shalygin int channel, const char **str) 841d0ddfd24SEugene Shalygin { 842d0ddfd24SEugene Shalygin struct ec_sensors_data *state = dev_get_drvdata(dev); 843d0ddfd24SEugene Shalygin int sensor_index = find_ec_sensor_index(state, type, channel); 844d0ddfd24SEugene Shalygin *str = get_sensor_info(state, sensor_index)->label; 845d0ddfd24SEugene Shalygin 846d0ddfd24SEugene Shalygin return 0; 847d0ddfd24SEugene Shalygin } 848d0ddfd24SEugene Shalygin 849d0ddfd24SEugene Shalygin static umode_t asus_ec_hwmon_is_visible(const void *drvdata, 850d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, u32 attr, 851d0ddfd24SEugene Shalygin int channel) 852d0ddfd24SEugene Shalygin { 853d0ddfd24SEugene Shalygin const struct ec_sensors_data *state = drvdata; 854d0ddfd24SEugene Shalygin 855d0ddfd24SEugene Shalygin return find_ec_sensor_index(state, type, channel) >= 0 ? S_IRUGO : 0; 856d0ddfd24SEugene Shalygin } 857d0ddfd24SEugene Shalygin 85888700d13SEugene Shalygin static int 859d0ddfd24SEugene Shalygin asus_ec_hwmon_add_chan_info(struct hwmon_channel_info *asus_ec_hwmon_chan, 860d0ddfd24SEugene Shalygin struct device *dev, int num, 861d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, u32 config) 862d0ddfd24SEugene Shalygin { 863d0ddfd24SEugene Shalygin int i; 864d0ddfd24SEugene Shalygin u32 *cfg = devm_kcalloc(dev, num + 1, sizeof(*cfg), GFP_KERNEL); 865d0ddfd24SEugene Shalygin 866d0ddfd24SEugene Shalygin if (!cfg) 867d0ddfd24SEugene Shalygin return -ENOMEM; 868d0ddfd24SEugene Shalygin 869d0ddfd24SEugene Shalygin asus_ec_hwmon_chan->type = type; 870d0ddfd24SEugene Shalygin asus_ec_hwmon_chan->config = cfg; 871d0ddfd24SEugene Shalygin for (i = 0; i < num; i++, cfg++) 872d0ddfd24SEugene Shalygin *cfg = config; 873d0ddfd24SEugene Shalygin 874d0ddfd24SEugene Shalygin return 0; 875d0ddfd24SEugene Shalygin } 876d0ddfd24SEugene Shalygin 877d0ddfd24SEugene Shalygin static const struct hwmon_ops asus_ec_hwmon_ops = { 878d0ddfd24SEugene Shalygin .is_visible = asus_ec_hwmon_is_visible, 879d0ddfd24SEugene Shalygin .read = asus_ec_hwmon_read, 880d0ddfd24SEugene Shalygin .read_string = asus_ec_hwmon_read_string, 881d0ddfd24SEugene Shalygin }; 882d0ddfd24SEugene Shalygin 883d0ddfd24SEugene Shalygin static struct hwmon_chip_info asus_ec_chip_info = { 884d0ddfd24SEugene Shalygin .ops = &asus_ec_hwmon_ops, 885d0ddfd24SEugene Shalygin }; 886d0ddfd24SEugene Shalygin 88788700d13SEugene Shalygin static const struct ec_board_info *get_board_info(void) 888d0ddfd24SEugene Shalygin { 88988700d13SEugene Shalygin const struct dmi_system_id *dmi_entry; 890d0ddfd24SEugene Shalygin 89188700d13SEugene Shalygin dmi_entry = dmi_first_match(dmi_table); 89288700d13SEugene Shalygin return dmi_entry ? dmi_entry->driver_data : NULL; 8935cd29012SEugene Shalygin } 8945cd29012SEugene Shalygin 89588700d13SEugene Shalygin static int asus_ec_probe(struct platform_device *pdev) 896d0ddfd24SEugene Shalygin { 897d0ddfd24SEugene Shalygin const struct hwmon_channel_info **ptr_asus_ec_ci; 8981298184bSEugene Shalygin int nr_count[hwmon_max] = { 0 }, nr_types = 0; 8991298184bSEugene Shalygin struct hwmon_channel_info *asus_ec_hwmon_chan; 9005cd29012SEugene Shalygin const struct ec_board_info *pboard_info; 901d0ddfd24SEugene Shalygin const struct hwmon_chip_info *chip_info; 9021298184bSEugene Shalygin struct device *dev = &pdev->dev; 9031298184bSEugene Shalygin struct ec_sensors_data *ec_data; 904d0ddfd24SEugene Shalygin const struct ec_sensor_info *si; 905d0ddfd24SEugene Shalygin enum hwmon_sensor_types type; 9061298184bSEugene Shalygin struct device *hwdev; 907d0ddfd24SEugene Shalygin unsigned int i; 908de8fbac5SEugene Shalygin int status; 909d0ddfd24SEugene Shalygin 9105cd29012SEugene Shalygin pboard_info = get_board_info(); 9115cd29012SEugene Shalygin if (!pboard_info) 912d0ddfd24SEugene Shalygin return -ENODEV; 913d0ddfd24SEugene Shalygin 9141298184bSEugene Shalygin ec_data = devm_kzalloc(dev, sizeof(struct ec_sensors_data), 9151298184bSEugene Shalygin GFP_KERNEL); 9161298184bSEugene Shalygin if (!ec_data) 9171298184bSEugene Shalygin return -ENOMEM; 9181298184bSEugene Shalygin 9191298184bSEugene Shalygin dev_set_drvdata(dev, ec_data); 9205cd29012SEugene Shalygin ec_data->board_info = pboard_info; 92145934e4aSEugene Shalygin 92245934e4aSEugene Shalygin switch (ec_data->board_info->family) { 9237cc44e5aSEugene Shalygin case family_amd_400_series: 9247cc44e5aSEugene Shalygin ec_data->sensors_info = sensors_family_amd_400; 9257cc44e5aSEugene Shalygin break; 92645934e4aSEugene Shalygin case family_amd_500_series: 92745934e4aSEugene Shalygin ec_data->sensors_info = sensors_family_amd_500; 92845934e4aSEugene Shalygin break; 9298f9eb10fSMichael Carns case family_intel_300_series: 9308f9eb10fSMichael Carns ec_data->sensors_info = sensors_family_intel_300; 9318f9eb10fSMichael Carns break; 932bae26b80SShady Nawara case family_intel_600_series: 933bae26b80SShady Nawara ec_data->sensors_info = sensors_family_intel_600; 934bae26b80SShady Nawara break; 93545934e4aSEugene Shalygin default: 93645934e4aSEugene Shalygin dev_err(dev, "Unknown board family: %d", 93745934e4aSEugene Shalygin ec_data->board_info->family); 93845934e4aSEugene Shalygin return -EINVAL; 93945934e4aSEugene Shalygin } 94045934e4aSEugene Shalygin 9415cd29012SEugene Shalygin ec_data->nr_sensors = hweight_long(ec_data->board_info->sensors); 942d0ddfd24SEugene Shalygin ec_data->sensors = devm_kcalloc(dev, ec_data->nr_sensors, 943d0ddfd24SEugene Shalygin sizeof(struct ec_sensor), GFP_KERNEL); 9449bdc112bSYuan Can if (!ec_data->sensors) 9459bdc112bSYuan Can return -ENOMEM; 946d0ddfd24SEugene Shalygin 947de8fbac5SEugene Shalygin status = setup_lock_data(dev); 948de8fbac5SEugene Shalygin if (status) { 949de8fbac5SEugene Shalygin dev_err(dev, "Failed to setup state/EC locking: %d", status); 950de8fbac5SEugene Shalygin return status; 951de8fbac5SEugene Shalygin } 95245934e4aSEugene Shalygin 953d0ddfd24SEugene Shalygin setup_sensor_data(ec_data); 954d0ddfd24SEugene Shalygin ec_data->registers = devm_kcalloc(dev, ec_data->nr_registers, 955d0ddfd24SEugene Shalygin sizeof(u16), GFP_KERNEL); 956d0ddfd24SEugene Shalygin ec_data->read_buffer = devm_kcalloc(dev, ec_data->nr_registers, 957d0ddfd24SEugene Shalygin sizeof(u8), GFP_KERNEL); 958d0ddfd24SEugene Shalygin 9591298184bSEugene Shalygin if (!ec_data->registers || !ec_data->read_buffer) 960d0ddfd24SEugene Shalygin return -ENOMEM; 961d0ddfd24SEugene Shalygin 962d0ddfd24SEugene Shalygin fill_ec_registers(ec_data); 963d0ddfd24SEugene Shalygin 964d0ddfd24SEugene Shalygin for (i = 0; i < ec_data->nr_sensors; ++i) { 965d0ddfd24SEugene Shalygin si = get_sensor_info(ec_data, i); 966d0ddfd24SEugene Shalygin if (!nr_count[si->type]) 967d0ddfd24SEugene Shalygin ++nr_types; 968d0ddfd24SEugene Shalygin ++nr_count[si->type]; 969d0ddfd24SEugene Shalygin } 970d0ddfd24SEugene Shalygin 971d0ddfd24SEugene Shalygin if (nr_count[hwmon_temp]) 972d0ddfd24SEugene Shalygin nr_count[hwmon_chip]++, nr_types++; 973d0ddfd24SEugene Shalygin 974d0ddfd24SEugene Shalygin asus_ec_hwmon_chan = devm_kcalloc( 975d0ddfd24SEugene Shalygin dev, nr_types, sizeof(*asus_ec_hwmon_chan), GFP_KERNEL); 976d0ddfd24SEugene Shalygin if (!asus_ec_hwmon_chan) 977d0ddfd24SEugene Shalygin return -ENOMEM; 978d0ddfd24SEugene Shalygin 979d0ddfd24SEugene Shalygin ptr_asus_ec_ci = devm_kcalloc(dev, nr_types + 1, 980d0ddfd24SEugene Shalygin sizeof(*ptr_asus_ec_ci), GFP_KERNEL); 981d0ddfd24SEugene Shalygin if (!ptr_asus_ec_ci) 982d0ddfd24SEugene Shalygin return -ENOMEM; 983d0ddfd24SEugene Shalygin 984d0ddfd24SEugene Shalygin asus_ec_chip_info.info = ptr_asus_ec_ci; 985d0ddfd24SEugene Shalygin chip_info = &asus_ec_chip_info; 986d0ddfd24SEugene Shalygin 987d0ddfd24SEugene Shalygin for (type = 0; type < hwmon_max; ++type) { 988d0ddfd24SEugene Shalygin if (!nr_count[type]) 989d0ddfd24SEugene Shalygin continue; 990d0ddfd24SEugene Shalygin 991d0ddfd24SEugene Shalygin asus_ec_hwmon_add_chan_info(asus_ec_hwmon_chan, dev, 992d0ddfd24SEugene Shalygin nr_count[type], type, 993d0ddfd24SEugene Shalygin hwmon_attributes[type]); 994d0ddfd24SEugene Shalygin *ptr_asus_ec_ci++ = asus_ec_hwmon_chan++; 995d0ddfd24SEugene Shalygin } 996d0ddfd24SEugene Shalygin 997d0ddfd24SEugene Shalygin dev_info(dev, "board has %d EC sensors that span %d registers", 998d0ddfd24SEugene Shalygin ec_data->nr_sensors, ec_data->nr_registers); 999d0ddfd24SEugene Shalygin 1000d0ddfd24SEugene Shalygin hwdev = devm_hwmon_device_register_with_info(dev, "asusec", 1001d0ddfd24SEugene Shalygin ec_data, chip_info, NULL); 1002d0ddfd24SEugene Shalygin 1003d0ddfd24SEugene Shalygin return PTR_ERR_OR_ZERO(hwdev); 1004d0ddfd24SEugene Shalygin } 1005d0ddfd24SEugene Shalygin 100688700d13SEugene Shalygin MODULE_DEVICE_TABLE(dmi, dmi_table); 1007d0ddfd24SEugene Shalygin 1008d0ddfd24SEugene Shalygin static struct platform_driver asus_ec_sensors_platform_driver = { 1009d0ddfd24SEugene Shalygin .driver = { 1010d0ddfd24SEugene Shalygin .name = "asus-ec-sensors", 1011d0ddfd24SEugene Shalygin }, 101288700d13SEugene Shalygin .probe = asus_ec_probe, 1013d0ddfd24SEugene Shalygin }; 1014d0ddfd24SEugene Shalygin 101588700d13SEugene Shalygin static struct platform_device *asus_ec_sensors_platform_device; 101688700d13SEugene Shalygin 101788700d13SEugene Shalygin static int __init asus_ec_init(void) 101888700d13SEugene Shalygin { 101988700d13SEugene Shalygin asus_ec_sensors_platform_device = 102088700d13SEugene Shalygin platform_create_bundle(&asus_ec_sensors_platform_driver, 102188700d13SEugene Shalygin asus_ec_probe, NULL, 0, NULL, 0); 102288700d13SEugene Shalygin 102388700d13SEugene Shalygin if (IS_ERR(asus_ec_sensors_platform_device)) 102488700d13SEugene Shalygin return PTR_ERR(asus_ec_sensors_platform_device); 102588700d13SEugene Shalygin 102688700d13SEugene Shalygin return 0; 102788700d13SEugene Shalygin } 102888700d13SEugene Shalygin 102988700d13SEugene Shalygin static void __exit asus_ec_exit(void) 103088700d13SEugene Shalygin { 103188700d13SEugene Shalygin platform_device_unregister(asus_ec_sensors_platform_device); 103288700d13SEugene Shalygin platform_driver_unregister(&asus_ec_sensors_platform_driver); 103388700d13SEugene Shalygin } 103488700d13SEugene Shalygin 103588700d13SEugene Shalygin module_init(asus_ec_init); 103688700d13SEugene Shalygin module_exit(asus_ec_exit); 1037d0ddfd24SEugene Shalygin 1038d0ddfd24SEugene Shalygin module_param_named(mutex_path, mutex_path_override, charp, 0); 1039d0ddfd24SEugene Shalygin MODULE_PARM_DESC(mutex_path, 1040d0ddfd24SEugene Shalygin "Override ACPI mutex path used to guard access to hardware"); 1041d0ddfd24SEugene Shalygin 1042d0ddfd24SEugene Shalygin MODULE_AUTHOR("Eugene Shalygin <eugene.shalygin@gmail.com>"); 1043d0ddfd24SEugene Shalygin MODULE_DESCRIPTION( 1044d0ddfd24SEugene Shalygin "HWMON driver for sensors accessible via ACPI EC in ASUS motherboards"); 1045d0ddfd24SEugene Shalygin MODULE_LICENSE("GPL"); 1046