1d0ddfd24SEugene Shalygin // SPDX-License-Identifier: GPL-2.0+ 2d0ddfd24SEugene Shalygin /* 3d0ddfd24SEugene Shalygin * HWMON driver for ASUS motherboards that publish some sensor values 4d0ddfd24SEugene Shalygin * via the embedded controller registers. 5d0ddfd24SEugene Shalygin * 6d0ddfd24SEugene Shalygin * Copyright (C) 2021 Eugene Shalygin <eugene.shalygin@gmail.com> 7d0ddfd24SEugene Shalygin 8d0ddfd24SEugene Shalygin * EC provides: 9d0ddfd24SEugene Shalygin * - Chipset temperature 10d0ddfd24SEugene Shalygin * - CPU temperature 11d0ddfd24SEugene Shalygin * - Motherboard temperature 12d0ddfd24SEugene Shalygin * - T_Sensor temperature 13d0ddfd24SEugene Shalygin * - VRM temperature 14d0ddfd24SEugene Shalygin * - Water In temperature 15d0ddfd24SEugene Shalygin * - Water Out temperature 16d0ddfd24SEugene Shalygin * - CPU Optional fan RPM 17d0ddfd24SEugene Shalygin * - Chipset fan RPM 18d0ddfd24SEugene Shalygin * - VRM Heat Sink fan RPM 19d0ddfd24SEugene Shalygin * - Water Flow fan RPM 20d0ddfd24SEugene Shalygin * - CPU current 21*f545a2fdSEugene Shalygin * - CPU core voltage 22d0ddfd24SEugene Shalygin */ 23d0ddfd24SEugene Shalygin 24d0ddfd24SEugene Shalygin #include <linux/acpi.h> 25d0ddfd24SEugene Shalygin #include <linux/bitops.h> 26d0ddfd24SEugene Shalygin #include <linux/dev_printk.h> 27d0ddfd24SEugene Shalygin #include <linux/dmi.h> 28d0ddfd24SEugene Shalygin #include <linux/hwmon.h> 29d0ddfd24SEugene Shalygin #include <linux/init.h> 30d0ddfd24SEugene Shalygin #include <linux/jiffies.h> 31d0ddfd24SEugene Shalygin #include <linux/kernel.h> 32d0ddfd24SEugene Shalygin #include <linux/module.h> 33d0ddfd24SEugene Shalygin #include <linux/platform_device.h> 34d0ddfd24SEugene Shalygin #include <linux/sort.h> 35d0ddfd24SEugene Shalygin #include <linux/units.h> 36d0ddfd24SEugene Shalygin 37d0ddfd24SEugene Shalygin #include <asm/unaligned.h> 38d0ddfd24SEugene Shalygin 39d0ddfd24SEugene Shalygin static char *mutex_path_override; 40d0ddfd24SEugene Shalygin 41d0ddfd24SEugene Shalygin /* Writing to this EC register switches EC bank */ 42d0ddfd24SEugene Shalygin #define ASUS_EC_BANK_REGISTER 0xff 43d0ddfd24SEugene Shalygin #define SENSOR_LABEL_LEN 16 44d0ddfd24SEugene Shalygin 45d0ddfd24SEugene Shalygin /* 46d0ddfd24SEugene Shalygin * Arbitrary set max. allowed bank number. Required for sorting banks and 47d0ddfd24SEugene Shalygin * currently is overkill with just 2 banks used at max, but for the sake 48d0ddfd24SEugene Shalygin * of alignment let's set it to a higher value. 49d0ddfd24SEugene Shalygin */ 50d0ddfd24SEugene Shalygin #define ASUS_EC_MAX_BANK 3 51d0ddfd24SEugene Shalygin 52d0ddfd24SEugene Shalygin #define ACPI_LOCK_DELAY_MS 500 53d0ddfd24SEugene Shalygin 54d0ddfd24SEugene Shalygin /* ACPI mutex for locking access to the EC for the firmware */ 55d0ddfd24SEugene Shalygin #define ASUS_HW_ACCESS_MUTEX_ASMX "\\AMW0.ASMX" 56d0ddfd24SEugene Shalygin 57d0ddfd24SEugene Shalygin /* There are two variants of the vendor spelling */ 58d0ddfd24SEugene Shalygin #define VENDOR_ASUS_UPPER_CASE "ASUSTeK COMPUTER INC." 59d0ddfd24SEugene Shalygin 60d0ddfd24SEugene Shalygin typedef union { 61d0ddfd24SEugene Shalygin u32 value; 62d0ddfd24SEugene Shalygin struct { 63d0ddfd24SEugene Shalygin u8 index; 64d0ddfd24SEugene Shalygin u8 bank; 65d0ddfd24SEugene Shalygin u8 size; 66d0ddfd24SEugene Shalygin u8 dummy; 67d0ddfd24SEugene Shalygin } components; 68d0ddfd24SEugene Shalygin } sensor_address; 69d0ddfd24SEugene Shalygin 70d0ddfd24SEugene Shalygin #define MAKE_SENSOR_ADDRESS(size, bank, index) { \ 71d0ddfd24SEugene Shalygin .value = (size << 16) + (bank << 8) + index \ 72d0ddfd24SEugene Shalygin } 73d0ddfd24SEugene Shalygin 74d0ddfd24SEugene Shalygin static u32 hwmon_attributes[hwmon_max] = { 75d0ddfd24SEugene Shalygin [hwmon_chip] = HWMON_C_REGISTER_TZ, 76d0ddfd24SEugene Shalygin [hwmon_temp] = HWMON_T_INPUT | HWMON_T_LABEL, 77d0ddfd24SEugene Shalygin [hwmon_in] = HWMON_I_INPUT | HWMON_I_LABEL, 78d0ddfd24SEugene Shalygin [hwmon_curr] = HWMON_C_INPUT | HWMON_C_LABEL, 79d0ddfd24SEugene Shalygin [hwmon_fan] = HWMON_F_INPUT | HWMON_F_LABEL, 80d0ddfd24SEugene Shalygin }; 81d0ddfd24SEugene Shalygin 82d0ddfd24SEugene Shalygin struct ec_sensor_info { 83d0ddfd24SEugene Shalygin char label[SENSOR_LABEL_LEN]; 84d0ddfd24SEugene Shalygin enum hwmon_sensor_types type; 85d0ddfd24SEugene Shalygin sensor_address addr; 86d0ddfd24SEugene Shalygin }; 87d0ddfd24SEugene Shalygin 88d0ddfd24SEugene Shalygin #define EC_SENSOR(sensor_label, sensor_type, size, bank, index) { \ 89d0ddfd24SEugene Shalygin .label = sensor_label, .type = sensor_type, \ 90d0ddfd24SEugene Shalygin .addr = MAKE_SENSOR_ADDRESS(size, bank, index), \ 91d0ddfd24SEugene Shalygin } 92d0ddfd24SEugene Shalygin 93d0ddfd24SEugene Shalygin enum ec_sensors { 94d0ddfd24SEugene Shalygin /* chipset temperature [℃] */ 95d0ddfd24SEugene Shalygin ec_sensor_temp_chipset, 96d0ddfd24SEugene Shalygin /* CPU temperature [℃] */ 97d0ddfd24SEugene Shalygin ec_sensor_temp_cpu, 98d0ddfd24SEugene Shalygin /* motherboard temperature [℃] */ 99d0ddfd24SEugene Shalygin ec_sensor_temp_mb, 100d0ddfd24SEugene Shalygin /* "T_Sensor" temperature sensor reading [℃] */ 101d0ddfd24SEugene Shalygin ec_sensor_temp_t_sensor, 102d0ddfd24SEugene Shalygin /* VRM temperature [℃] */ 103d0ddfd24SEugene Shalygin ec_sensor_temp_vrm, 104*f545a2fdSEugene Shalygin /* CPU Core voltage [mV] */ 105*f545a2fdSEugene Shalygin ec_sensor_in_cpu_core, 106d0ddfd24SEugene Shalygin /* CPU_Opt fan [RPM] */ 107d0ddfd24SEugene Shalygin ec_sensor_fan_cpu_opt, 108d0ddfd24SEugene Shalygin /* VRM heat sink fan [RPM] */ 109d0ddfd24SEugene Shalygin ec_sensor_fan_vrm_hs, 110d0ddfd24SEugene Shalygin /* Chipset fan [RPM] */ 111d0ddfd24SEugene Shalygin ec_sensor_fan_chipset, 112d0ddfd24SEugene Shalygin /* Water flow sensor reading [RPM] */ 113d0ddfd24SEugene Shalygin ec_sensor_fan_water_flow, 114d0ddfd24SEugene Shalygin /* CPU current [A] */ 115d0ddfd24SEugene Shalygin ec_sensor_curr_cpu, 116d0ddfd24SEugene Shalygin /* "Water_In" temperature sensor reading [℃] */ 117d0ddfd24SEugene Shalygin ec_sensor_temp_water_in, 118d0ddfd24SEugene Shalygin /* "Water_Out" temperature sensor reading [℃] */ 119d0ddfd24SEugene Shalygin ec_sensor_temp_water_out, 120d0ddfd24SEugene Shalygin }; 121d0ddfd24SEugene Shalygin 122d0ddfd24SEugene Shalygin #define SENSOR_TEMP_CHIPSET BIT(ec_sensor_temp_chipset) 123d0ddfd24SEugene Shalygin #define SENSOR_TEMP_CPU BIT(ec_sensor_temp_cpu) 124d0ddfd24SEugene Shalygin #define SENSOR_TEMP_MB BIT(ec_sensor_temp_mb) 125d0ddfd24SEugene Shalygin #define SENSOR_TEMP_T_SENSOR BIT(ec_sensor_temp_t_sensor) 126d0ddfd24SEugene Shalygin #define SENSOR_TEMP_VRM BIT(ec_sensor_temp_vrm) 127*f545a2fdSEugene Shalygin #define SENSOR_IN_CPU_CORE BIT(ec_sensor_in_cpu_core) 128d0ddfd24SEugene Shalygin #define SENSOR_FAN_CPU_OPT BIT(ec_sensor_fan_cpu_opt) 129d0ddfd24SEugene Shalygin #define SENSOR_FAN_VRM_HS BIT(ec_sensor_fan_vrm_hs) 130d0ddfd24SEugene Shalygin #define SENSOR_FAN_CHIPSET BIT(ec_sensor_fan_chipset) 131d0ddfd24SEugene Shalygin #define SENSOR_FAN_WATER_FLOW BIT(ec_sensor_fan_water_flow) 132d0ddfd24SEugene Shalygin #define SENSOR_CURR_CPU BIT(ec_sensor_curr_cpu) 133d0ddfd24SEugene Shalygin #define SENSOR_TEMP_WATER_IN BIT(ec_sensor_temp_water_in) 134d0ddfd24SEugene Shalygin #define SENSOR_TEMP_WATER_OUT BIT(ec_sensor_temp_water_out) 135d0ddfd24SEugene Shalygin 136d0ddfd24SEugene Shalygin /* All the known sensors for ASUS EC controllers */ 137d0ddfd24SEugene Shalygin static const struct ec_sensor_info known_ec_sensors[] = { 138d0ddfd24SEugene Shalygin [ec_sensor_temp_chipset] = 139d0ddfd24SEugene Shalygin EC_SENSOR("Chipset", hwmon_temp, 1, 0x00, 0x3a), 140d0ddfd24SEugene Shalygin [ec_sensor_temp_cpu] = EC_SENSOR("CPU", hwmon_temp, 1, 0x00, 0x3b), 141d0ddfd24SEugene Shalygin [ec_sensor_temp_mb] = 142d0ddfd24SEugene Shalygin EC_SENSOR("Motherboard", hwmon_temp, 1, 0x00, 0x3c), 143d0ddfd24SEugene Shalygin [ec_sensor_temp_t_sensor] = 144d0ddfd24SEugene Shalygin EC_SENSOR("T_Sensor", hwmon_temp, 1, 0x00, 0x3d), 145d0ddfd24SEugene Shalygin [ec_sensor_temp_vrm] = EC_SENSOR("VRM", hwmon_temp, 1, 0x00, 0x3e), 146*f545a2fdSEugene Shalygin [ec_sensor_in_cpu_core] = 147*f545a2fdSEugene Shalygin EC_SENSOR("CPU Core", hwmon_in, 2, 0x00, 0xa2), 148d0ddfd24SEugene Shalygin [ec_sensor_fan_cpu_opt] = 149d0ddfd24SEugene Shalygin EC_SENSOR("CPU_Opt", hwmon_fan, 2, 0x00, 0xb0), 150d0ddfd24SEugene Shalygin [ec_sensor_fan_vrm_hs] = EC_SENSOR("VRM HS", hwmon_fan, 2, 0x00, 0xb2), 151d0ddfd24SEugene Shalygin [ec_sensor_fan_chipset] = 152d0ddfd24SEugene Shalygin EC_SENSOR("Chipset", hwmon_fan, 2, 0x00, 0xb4), 153d0ddfd24SEugene Shalygin [ec_sensor_fan_water_flow] = 154d0ddfd24SEugene Shalygin EC_SENSOR("Water_Flow", hwmon_fan, 2, 0x00, 0xbc), 155d0ddfd24SEugene Shalygin [ec_sensor_curr_cpu] = EC_SENSOR("CPU", hwmon_curr, 1, 0x00, 0xf4), 156d0ddfd24SEugene Shalygin [ec_sensor_temp_water_in] = 157d0ddfd24SEugene Shalygin EC_SENSOR("Water_In", hwmon_temp, 1, 0x01, 0x00), 158d0ddfd24SEugene Shalygin [ec_sensor_temp_water_out] = 159d0ddfd24SEugene Shalygin EC_SENSOR("Water_Out", hwmon_temp, 1, 0x01, 0x01), 160d0ddfd24SEugene Shalygin }; 161d0ddfd24SEugene Shalygin 162d0ddfd24SEugene Shalygin /* Shortcuts for common combinations */ 163d0ddfd24SEugene Shalygin #define SENSOR_SET_TEMP_CHIPSET_CPU_MB \ 164d0ddfd24SEugene Shalygin (SENSOR_TEMP_CHIPSET | SENSOR_TEMP_CPU | SENSOR_TEMP_MB) 165d0ddfd24SEugene Shalygin #define SENSOR_SET_TEMP_WATER (SENSOR_TEMP_WATER_IN | SENSOR_TEMP_WATER_OUT) 166d0ddfd24SEugene Shalygin 167d0ddfd24SEugene Shalygin #define DMI_EXACT_MATCH_BOARD(vendor, name, sensors) { \ 168d0ddfd24SEugene Shalygin .matches = { \ 169d0ddfd24SEugene Shalygin DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \ 170d0ddfd24SEugene Shalygin DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ 171d0ddfd24SEugene Shalygin }, \ 172d0ddfd24SEugene Shalygin .driver_data = (void *)(sensors), \ 173d0ddfd24SEugene Shalygin } 174d0ddfd24SEugene Shalygin 175d0ddfd24SEugene Shalygin static const struct dmi_system_id asus_ec_dmi_table[] __initconst = { 176d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "PRIME X570-PRO", 177d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM | 178d0ddfd24SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET), 179d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "Pro WS X570-ACE", 180d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_VRM | 181*f545a2fdSEugene Shalygin SENSOR_FAN_CHIPSET | SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 182d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, 183d0ddfd24SEugene Shalygin "ROG CROSSHAIR VIII DARK HERO", 184d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR | 185d0ddfd24SEugene Shalygin SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 186*f545a2fdSEugene Shalygin SENSOR_FAN_CPU_OPT | SENSOR_FAN_WATER_FLOW | 187*f545a2fdSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 188d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, 189d0ddfd24SEugene Shalygin "ROG CROSSHAIR VIII FORMULA", 190d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR | 191d0ddfd24SEugene Shalygin SENSOR_TEMP_VRM | SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET | 192*f545a2fdSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 193d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "ROG CROSSHAIR VIII HERO", 194d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR | 195d0ddfd24SEugene Shalygin SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 196d0ddfd24SEugene Shalygin SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET | 197*f545a2fdSEugene Shalygin SENSOR_FAN_WATER_FLOW | SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 198d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, 1992f66cb5bSEugene Shalygin "ROG CROSSHAIR VIII HERO (WI-FI)", 2002f66cb5bSEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR | 2012f66cb5bSEugene Shalygin SENSOR_TEMP_VRM | SENSOR_SET_TEMP_WATER | 2022f66cb5bSEugene Shalygin SENSOR_FAN_CPU_OPT | SENSOR_FAN_CHIPSET | 203*f545a2fdSEugene Shalygin SENSOR_FAN_WATER_FLOW | SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 2042f66cb5bSEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, 205d0ddfd24SEugene Shalygin "ROG CROSSHAIR VIII IMPACT", 206d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | SENSOR_TEMP_T_SENSOR | 207*f545a2fdSEugene Shalygin SENSOR_TEMP_VRM | SENSOR_FAN_CHIPSET | 208*f545a2fdSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 209d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "ROG STRIX B550-E GAMING", 210d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | 211d0ddfd24SEugene Shalygin SENSOR_TEMP_T_SENSOR | 212d0ddfd24SEugene Shalygin SENSOR_TEMP_VRM | SENSOR_FAN_CPU_OPT), 213d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "ROG STRIX B550-I GAMING", 214d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | 215d0ddfd24SEugene Shalygin SENSOR_TEMP_T_SENSOR | 216*f545a2fdSEugene Shalygin SENSOR_TEMP_VRM | SENSOR_FAN_VRM_HS | 217*f545a2fdSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 218d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "ROG STRIX X570-E GAMING", 219d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | 220d0ddfd24SEugene Shalygin SENSOR_TEMP_T_SENSOR | 221*f545a2fdSEugene Shalygin SENSOR_TEMP_VRM | SENSOR_FAN_CHIPSET | 222*f545a2fdSEugene Shalygin SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 223d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "ROG STRIX X570-F GAMING", 224d0ddfd24SEugene Shalygin SENSOR_SET_TEMP_CHIPSET_CPU_MB | 225d0ddfd24SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_FAN_CHIPSET), 226d0ddfd24SEugene Shalygin DMI_EXACT_MATCH_BOARD(VENDOR_ASUS_UPPER_CASE, "ROG STRIX X570-I GAMING", 227d0ddfd24SEugene Shalygin SENSOR_TEMP_T_SENSOR | SENSOR_FAN_VRM_HS | 228*f545a2fdSEugene Shalygin SENSOR_FAN_CHIPSET | SENSOR_CURR_CPU | SENSOR_IN_CPU_CORE), 229d0ddfd24SEugene Shalygin {} 230d0ddfd24SEugene Shalygin }; 231d0ddfd24SEugene Shalygin 232d0ddfd24SEugene Shalygin struct ec_sensor { 233d0ddfd24SEugene Shalygin unsigned int info_index; 234339f8a99SEugene Shalygin s32 cached_value; 235d0ddfd24SEugene Shalygin }; 236d0ddfd24SEugene Shalygin 237d0ddfd24SEugene Shalygin struct ec_sensors_data { 238d0ddfd24SEugene Shalygin unsigned long board_sensors; 239d0ddfd24SEugene Shalygin struct ec_sensor *sensors; 240d0ddfd24SEugene Shalygin /* EC registers to read from */ 241d0ddfd24SEugene Shalygin u16 *registers; 242d0ddfd24SEugene Shalygin u8 *read_buffer; 243d0ddfd24SEugene Shalygin /* sorted list of unique register banks */ 244d0ddfd24SEugene Shalygin u8 banks[ASUS_EC_MAX_BANK + 1]; 245d0ddfd24SEugene Shalygin /* in jiffies */ 246d0ddfd24SEugene Shalygin unsigned long last_updated; 247d0ddfd24SEugene Shalygin acpi_handle aml_mutex; 248d0ddfd24SEugene Shalygin /* number of board EC sensors */ 249d0ddfd24SEugene Shalygin u8 nr_sensors; 250d0ddfd24SEugene Shalygin /* 251d0ddfd24SEugene Shalygin * number of EC registers to read 252d0ddfd24SEugene Shalygin * (sensor might span more than 1 register) 253d0ddfd24SEugene Shalygin */ 254d0ddfd24SEugene Shalygin u8 nr_registers; 255d0ddfd24SEugene Shalygin /* number of unique register banks */ 256d0ddfd24SEugene Shalygin u8 nr_banks; 257d0ddfd24SEugene Shalygin }; 258d0ddfd24SEugene Shalygin 259d0ddfd24SEugene Shalygin static u8 register_bank(u16 reg) 260d0ddfd24SEugene Shalygin { 261d0ddfd24SEugene Shalygin return reg >> 8; 262d0ddfd24SEugene Shalygin } 263d0ddfd24SEugene Shalygin 264d0ddfd24SEugene Shalygin static u8 register_index(u16 reg) 265d0ddfd24SEugene Shalygin { 266d0ddfd24SEugene Shalygin return reg & 0x00ff; 267d0ddfd24SEugene Shalygin } 268d0ddfd24SEugene Shalygin 269d0ddfd24SEugene Shalygin static const struct ec_sensor_info * 270d0ddfd24SEugene Shalygin get_sensor_info(const struct ec_sensors_data *state, int index) 271d0ddfd24SEugene Shalygin { 272d0ddfd24SEugene Shalygin return &known_ec_sensors[state->sensors[index].info_index]; 273d0ddfd24SEugene Shalygin } 274d0ddfd24SEugene Shalygin 275d0ddfd24SEugene Shalygin static int find_ec_sensor_index(const struct ec_sensors_data *ec, 276d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, int channel) 277d0ddfd24SEugene Shalygin { 278d0ddfd24SEugene Shalygin unsigned int i; 279d0ddfd24SEugene Shalygin 280d0ddfd24SEugene Shalygin for (i = 0; i < ec->nr_sensors; i++) { 281d0ddfd24SEugene Shalygin if (get_sensor_info(ec, i)->type == type) { 282d0ddfd24SEugene Shalygin if (channel == 0) 283d0ddfd24SEugene Shalygin return i; 284d0ddfd24SEugene Shalygin channel--; 285d0ddfd24SEugene Shalygin } 286d0ddfd24SEugene Shalygin } 287d0ddfd24SEugene Shalygin return -ENOENT; 288d0ddfd24SEugene Shalygin } 289d0ddfd24SEugene Shalygin 290d0ddfd24SEugene Shalygin static int __init bank_compare(const void *a, const void *b) 291d0ddfd24SEugene Shalygin { 292d0ddfd24SEugene Shalygin return *((const s8 *)a) - *((const s8 *)b); 293d0ddfd24SEugene Shalygin } 294d0ddfd24SEugene Shalygin 295d0ddfd24SEugene Shalygin static int __init board_sensors_count(unsigned long sensors) 296d0ddfd24SEugene Shalygin { 297d0ddfd24SEugene Shalygin return hweight_long(sensors); 298d0ddfd24SEugene Shalygin } 299d0ddfd24SEugene Shalygin 300d0ddfd24SEugene Shalygin static void __init setup_sensor_data(struct ec_sensors_data *ec) 301d0ddfd24SEugene Shalygin { 302d0ddfd24SEugene Shalygin struct ec_sensor *s = ec->sensors; 303d0ddfd24SEugene Shalygin bool bank_found; 304d0ddfd24SEugene Shalygin int i, j; 305d0ddfd24SEugene Shalygin u8 bank; 306d0ddfd24SEugene Shalygin 307d0ddfd24SEugene Shalygin ec->nr_banks = 0; 308d0ddfd24SEugene Shalygin ec->nr_registers = 0; 309d0ddfd24SEugene Shalygin 310d0ddfd24SEugene Shalygin for_each_set_bit(i, &ec->board_sensors, 311d0ddfd24SEugene Shalygin BITS_PER_TYPE(ec->board_sensors)) { 312d0ddfd24SEugene Shalygin s->info_index = i; 313d0ddfd24SEugene Shalygin s->cached_value = 0; 314d0ddfd24SEugene Shalygin ec->nr_registers += 315d0ddfd24SEugene Shalygin known_ec_sensors[s->info_index].addr.components.size; 316d0ddfd24SEugene Shalygin bank_found = false; 317d0ddfd24SEugene Shalygin bank = known_ec_sensors[s->info_index].addr.components.bank; 318d0ddfd24SEugene Shalygin for (j = 0; j < ec->nr_banks; j++) { 319d0ddfd24SEugene Shalygin if (ec->banks[j] == bank) { 320d0ddfd24SEugene Shalygin bank_found = true; 321d0ddfd24SEugene Shalygin break; 322d0ddfd24SEugene Shalygin } 323d0ddfd24SEugene Shalygin } 324d0ddfd24SEugene Shalygin if (!bank_found) { 325d0ddfd24SEugene Shalygin ec->banks[ec->nr_banks++] = bank; 326d0ddfd24SEugene Shalygin } 327d0ddfd24SEugene Shalygin s++; 328d0ddfd24SEugene Shalygin } 329d0ddfd24SEugene Shalygin sort(ec->banks, ec->nr_banks, 1, bank_compare, NULL); 330d0ddfd24SEugene Shalygin } 331d0ddfd24SEugene Shalygin 332d0ddfd24SEugene Shalygin static void __init fill_ec_registers(struct ec_sensors_data *ec) 333d0ddfd24SEugene Shalygin { 334d0ddfd24SEugene Shalygin const struct ec_sensor_info *si; 335d0ddfd24SEugene Shalygin unsigned int i, j, register_idx = 0; 336d0ddfd24SEugene Shalygin 337d0ddfd24SEugene Shalygin for (i = 0; i < ec->nr_sensors; ++i) { 338d0ddfd24SEugene Shalygin si = get_sensor_info(ec, i); 339d0ddfd24SEugene Shalygin for (j = 0; j < si->addr.components.size; ++j, ++register_idx) { 340d0ddfd24SEugene Shalygin ec->registers[register_idx] = 341d0ddfd24SEugene Shalygin (si->addr.components.bank << 8) + 342d0ddfd24SEugene Shalygin si->addr.components.index + j; 343d0ddfd24SEugene Shalygin } 344d0ddfd24SEugene Shalygin } 345d0ddfd24SEugene Shalygin } 346d0ddfd24SEugene Shalygin 347d0ddfd24SEugene Shalygin static acpi_handle __init asus_hw_access_mutex(struct device *dev) 348d0ddfd24SEugene Shalygin { 349d0ddfd24SEugene Shalygin const char *mutex_path; 350d0ddfd24SEugene Shalygin acpi_handle res; 351d0ddfd24SEugene Shalygin int status; 352d0ddfd24SEugene Shalygin 353d0ddfd24SEugene Shalygin mutex_path = mutex_path_override ? 354d0ddfd24SEugene Shalygin mutex_path_override : ASUS_HW_ACCESS_MUTEX_ASMX; 355d0ddfd24SEugene Shalygin 356d0ddfd24SEugene Shalygin status = acpi_get_handle(NULL, (acpi_string)mutex_path, &res); 357d0ddfd24SEugene Shalygin if (ACPI_FAILURE(status)) { 358d0ddfd24SEugene Shalygin dev_err(dev, 359d0ddfd24SEugene Shalygin "Could not get hardware access guard mutex '%s': error %d", 360d0ddfd24SEugene Shalygin mutex_path, status); 361d0ddfd24SEugene Shalygin return NULL; 362d0ddfd24SEugene Shalygin } 363d0ddfd24SEugene Shalygin return res; 364d0ddfd24SEugene Shalygin } 365d0ddfd24SEugene Shalygin 366d0ddfd24SEugene Shalygin static int asus_ec_bank_switch(u8 bank, u8 *old) 367d0ddfd24SEugene Shalygin { 368d0ddfd24SEugene Shalygin int status = 0; 369d0ddfd24SEugene Shalygin 370d0ddfd24SEugene Shalygin if (old) { 371d0ddfd24SEugene Shalygin status = ec_read(ASUS_EC_BANK_REGISTER, old); 372d0ddfd24SEugene Shalygin } 373d0ddfd24SEugene Shalygin if (status || (old && (*old == bank))) 374d0ddfd24SEugene Shalygin return status; 375d0ddfd24SEugene Shalygin return ec_write(ASUS_EC_BANK_REGISTER, bank); 376d0ddfd24SEugene Shalygin } 377d0ddfd24SEugene Shalygin 378d0ddfd24SEugene Shalygin static int asus_ec_block_read(const struct device *dev, 379d0ddfd24SEugene Shalygin struct ec_sensors_data *ec) 380d0ddfd24SEugene Shalygin { 381d0ddfd24SEugene Shalygin int ireg, ibank, status; 382d0ddfd24SEugene Shalygin u8 bank, reg_bank, prev_bank; 383d0ddfd24SEugene Shalygin 384d0ddfd24SEugene Shalygin bank = 0; 385d0ddfd24SEugene Shalygin status = asus_ec_bank_switch(bank, &prev_bank); 386d0ddfd24SEugene Shalygin if (status) { 387d0ddfd24SEugene Shalygin dev_warn(dev, "EC bank switch failed"); 388d0ddfd24SEugene Shalygin return status; 389d0ddfd24SEugene Shalygin } 390d0ddfd24SEugene Shalygin 391d0ddfd24SEugene Shalygin if (prev_bank) { 392d0ddfd24SEugene Shalygin /* oops... somebody else is working with the EC too */ 393d0ddfd24SEugene Shalygin dev_warn(dev, 394d0ddfd24SEugene Shalygin "Concurrent access to the ACPI EC detected.\nRace condition possible."); 395d0ddfd24SEugene Shalygin } 396d0ddfd24SEugene Shalygin 397d0ddfd24SEugene Shalygin /* read registers minimizing bank switches. */ 398d0ddfd24SEugene Shalygin for (ibank = 0; ibank < ec->nr_banks; ibank++) { 399d0ddfd24SEugene Shalygin if (bank != ec->banks[ibank]) { 400d0ddfd24SEugene Shalygin bank = ec->banks[ibank]; 401d0ddfd24SEugene Shalygin if (asus_ec_bank_switch(bank, NULL)) { 402d0ddfd24SEugene Shalygin dev_warn(dev, "EC bank switch to %d failed", 403d0ddfd24SEugene Shalygin bank); 404d0ddfd24SEugene Shalygin break; 405d0ddfd24SEugene Shalygin } 406d0ddfd24SEugene Shalygin } 407d0ddfd24SEugene Shalygin for (ireg = 0; ireg < ec->nr_registers; ireg++) { 408d0ddfd24SEugene Shalygin reg_bank = register_bank(ec->registers[ireg]); 409d0ddfd24SEugene Shalygin if (reg_bank < bank) { 410d0ddfd24SEugene Shalygin continue; 411d0ddfd24SEugene Shalygin } 412d0ddfd24SEugene Shalygin ec_read(register_index(ec->registers[ireg]), 413d0ddfd24SEugene Shalygin ec->read_buffer + ireg); 414d0ddfd24SEugene Shalygin } 415d0ddfd24SEugene Shalygin } 416d0ddfd24SEugene Shalygin 417d0ddfd24SEugene Shalygin status = asus_ec_bank_switch(prev_bank, NULL); 418d0ddfd24SEugene Shalygin return status; 419d0ddfd24SEugene Shalygin } 420d0ddfd24SEugene Shalygin 421339f8a99SEugene Shalygin static inline s32 get_sensor_value(const struct ec_sensor_info *si, u8 *data) 422d0ddfd24SEugene Shalygin { 423d0ddfd24SEugene Shalygin switch (si->addr.components.size) { 424d0ddfd24SEugene Shalygin case 1: 425339f8a99SEugene Shalygin return (s8)*data; 426d0ddfd24SEugene Shalygin case 2: 427339f8a99SEugene Shalygin return (s16)get_unaligned_be16(data); 428d0ddfd24SEugene Shalygin case 4: 429339f8a99SEugene Shalygin return (s32)get_unaligned_be32(data); 430d0ddfd24SEugene Shalygin default: 431d0ddfd24SEugene Shalygin return 0; 432d0ddfd24SEugene Shalygin } 433d0ddfd24SEugene Shalygin } 434d0ddfd24SEugene Shalygin 435d0ddfd24SEugene Shalygin static void update_sensor_values(struct ec_sensors_data *ec, u8 *data) 436d0ddfd24SEugene Shalygin { 437d0ddfd24SEugene Shalygin const struct ec_sensor_info *si; 438d0ddfd24SEugene Shalygin struct ec_sensor *s; 439d0ddfd24SEugene Shalygin 440d0ddfd24SEugene Shalygin for (s = ec->sensors; s != ec->sensors + ec->nr_sensors; s++) { 441d0ddfd24SEugene Shalygin si = &known_ec_sensors[s->info_index]; 442d0ddfd24SEugene Shalygin s->cached_value = get_sensor_value(si, data); 443d0ddfd24SEugene Shalygin data += si->addr.components.size; 444d0ddfd24SEugene Shalygin } 445d0ddfd24SEugene Shalygin } 446d0ddfd24SEugene Shalygin 447d0ddfd24SEugene Shalygin static int update_ec_sensors(const struct device *dev, 448d0ddfd24SEugene Shalygin struct ec_sensors_data *ec) 449d0ddfd24SEugene Shalygin { 450d0ddfd24SEugene Shalygin int status; 451d0ddfd24SEugene Shalygin 452d0ddfd24SEugene Shalygin /* 453d0ddfd24SEugene Shalygin * ASUS DSDT does not specify that access to the EC has to be guarded, 454d0ddfd24SEugene Shalygin * but firmware does access it via ACPI 455d0ddfd24SEugene Shalygin */ 456d0ddfd24SEugene Shalygin if (ACPI_FAILURE(acpi_acquire_mutex(ec->aml_mutex, NULL, 457d0ddfd24SEugene Shalygin ACPI_LOCK_DELAY_MS))) { 458d0ddfd24SEugene Shalygin dev_err(dev, "Failed to acquire AML mutex"); 459d0ddfd24SEugene Shalygin status = -EBUSY; 460d0ddfd24SEugene Shalygin goto cleanup; 461d0ddfd24SEugene Shalygin } 462d0ddfd24SEugene Shalygin 463d0ddfd24SEugene Shalygin status = asus_ec_block_read(dev, ec); 464d0ddfd24SEugene Shalygin 465d0ddfd24SEugene Shalygin if (!status) { 466d0ddfd24SEugene Shalygin update_sensor_values(ec, ec->read_buffer); 467d0ddfd24SEugene Shalygin } 468d0ddfd24SEugene Shalygin if (ACPI_FAILURE(acpi_release_mutex(ec->aml_mutex, NULL))) { 469d0ddfd24SEugene Shalygin dev_err(dev, "Failed to release AML mutex"); 470d0ddfd24SEugene Shalygin } 471d0ddfd24SEugene Shalygin cleanup: 472d0ddfd24SEugene Shalygin return status; 473d0ddfd24SEugene Shalygin } 474d0ddfd24SEugene Shalygin 475339f8a99SEugene Shalygin static long scale_sensor_value(s32 value, int data_type) 476d0ddfd24SEugene Shalygin { 477d0ddfd24SEugene Shalygin switch (data_type) { 478d0ddfd24SEugene Shalygin case hwmon_curr: 479d0ddfd24SEugene Shalygin case hwmon_temp: 480d0ddfd24SEugene Shalygin return value * MILLI; 481d0ddfd24SEugene Shalygin default: 482d0ddfd24SEugene Shalygin return value; 483d0ddfd24SEugene Shalygin } 484d0ddfd24SEugene Shalygin } 485d0ddfd24SEugene Shalygin 486d0ddfd24SEugene Shalygin static int get_cached_value_or_update(const struct device *dev, 487d0ddfd24SEugene Shalygin int sensor_index, 488339f8a99SEugene Shalygin struct ec_sensors_data *state, s32 *value) 489d0ddfd24SEugene Shalygin { 490d0ddfd24SEugene Shalygin if (time_after(jiffies, state->last_updated + HZ)) { 491d0ddfd24SEugene Shalygin if (update_ec_sensors(dev, state)) { 492d0ddfd24SEugene Shalygin dev_err(dev, "update_ec_sensors() failure\n"); 493d0ddfd24SEugene Shalygin return -EIO; 494d0ddfd24SEugene Shalygin } 495d0ddfd24SEugene Shalygin 496d0ddfd24SEugene Shalygin state->last_updated = jiffies; 497d0ddfd24SEugene Shalygin } 498d0ddfd24SEugene Shalygin 499d0ddfd24SEugene Shalygin *value = state->sensors[sensor_index].cached_value; 500d0ddfd24SEugene Shalygin return 0; 501d0ddfd24SEugene Shalygin } 502d0ddfd24SEugene Shalygin 503d0ddfd24SEugene Shalygin /* 504d0ddfd24SEugene Shalygin * Now follow the functions that implement the hwmon interface 505d0ddfd24SEugene Shalygin */ 506d0ddfd24SEugene Shalygin 507d0ddfd24SEugene Shalygin static int asus_ec_hwmon_read(struct device *dev, enum hwmon_sensor_types type, 508d0ddfd24SEugene Shalygin u32 attr, int channel, long *val) 509d0ddfd24SEugene Shalygin { 510d0ddfd24SEugene Shalygin int ret; 511339f8a99SEugene Shalygin s32 value = 0; 512d0ddfd24SEugene Shalygin 513d0ddfd24SEugene Shalygin struct ec_sensors_data *state = dev_get_drvdata(dev); 514d0ddfd24SEugene Shalygin int sidx = find_ec_sensor_index(state, type, channel); 515d0ddfd24SEugene Shalygin 516d0ddfd24SEugene Shalygin if (sidx < 0) { 517d0ddfd24SEugene Shalygin return sidx; 518d0ddfd24SEugene Shalygin } 519d0ddfd24SEugene Shalygin 520d0ddfd24SEugene Shalygin ret = get_cached_value_or_update(dev, sidx, state, &value); 521d0ddfd24SEugene Shalygin if (!ret) { 522d0ddfd24SEugene Shalygin *val = scale_sensor_value(value, 523d0ddfd24SEugene Shalygin get_sensor_info(state, sidx)->type); 524d0ddfd24SEugene Shalygin } 525d0ddfd24SEugene Shalygin 526d0ddfd24SEugene Shalygin return ret; 527d0ddfd24SEugene Shalygin } 528d0ddfd24SEugene Shalygin 529d0ddfd24SEugene Shalygin static int asus_ec_hwmon_read_string(struct device *dev, 530d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, u32 attr, 531d0ddfd24SEugene Shalygin int channel, const char **str) 532d0ddfd24SEugene Shalygin { 533d0ddfd24SEugene Shalygin struct ec_sensors_data *state = dev_get_drvdata(dev); 534d0ddfd24SEugene Shalygin int sensor_index = find_ec_sensor_index(state, type, channel); 535d0ddfd24SEugene Shalygin *str = get_sensor_info(state, sensor_index)->label; 536d0ddfd24SEugene Shalygin 537d0ddfd24SEugene Shalygin return 0; 538d0ddfd24SEugene Shalygin } 539d0ddfd24SEugene Shalygin 540d0ddfd24SEugene Shalygin static umode_t asus_ec_hwmon_is_visible(const void *drvdata, 541d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, u32 attr, 542d0ddfd24SEugene Shalygin int channel) 543d0ddfd24SEugene Shalygin { 544d0ddfd24SEugene Shalygin const struct ec_sensors_data *state = drvdata; 545d0ddfd24SEugene Shalygin 546d0ddfd24SEugene Shalygin return find_ec_sensor_index(state, type, channel) >= 0 ? S_IRUGO : 0; 547d0ddfd24SEugene Shalygin } 548d0ddfd24SEugene Shalygin 549d0ddfd24SEugene Shalygin static int __init 550d0ddfd24SEugene Shalygin asus_ec_hwmon_add_chan_info(struct hwmon_channel_info *asus_ec_hwmon_chan, 551d0ddfd24SEugene Shalygin struct device *dev, int num, 552d0ddfd24SEugene Shalygin enum hwmon_sensor_types type, u32 config) 553d0ddfd24SEugene Shalygin { 554d0ddfd24SEugene Shalygin int i; 555d0ddfd24SEugene Shalygin u32 *cfg = devm_kcalloc(dev, num + 1, sizeof(*cfg), GFP_KERNEL); 556d0ddfd24SEugene Shalygin 557d0ddfd24SEugene Shalygin if (!cfg) 558d0ddfd24SEugene Shalygin return -ENOMEM; 559d0ddfd24SEugene Shalygin 560d0ddfd24SEugene Shalygin asus_ec_hwmon_chan->type = type; 561d0ddfd24SEugene Shalygin asus_ec_hwmon_chan->config = cfg; 562d0ddfd24SEugene Shalygin for (i = 0; i < num; i++, cfg++) 563d0ddfd24SEugene Shalygin *cfg = config; 564d0ddfd24SEugene Shalygin 565d0ddfd24SEugene Shalygin return 0; 566d0ddfd24SEugene Shalygin } 567d0ddfd24SEugene Shalygin 568d0ddfd24SEugene Shalygin static const struct hwmon_ops asus_ec_hwmon_ops = { 569d0ddfd24SEugene Shalygin .is_visible = asus_ec_hwmon_is_visible, 570d0ddfd24SEugene Shalygin .read = asus_ec_hwmon_read, 571d0ddfd24SEugene Shalygin .read_string = asus_ec_hwmon_read_string, 572d0ddfd24SEugene Shalygin }; 573d0ddfd24SEugene Shalygin 574d0ddfd24SEugene Shalygin static struct hwmon_chip_info asus_ec_chip_info = { 575d0ddfd24SEugene Shalygin .ops = &asus_ec_hwmon_ops, 576d0ddfd24SEugene Shalygin }; 577d0ddfd24SEugene Shalygin 578d0ddfd24SEugene Shalygin static unsigned long __init 579d0ddfd24SEugene Shalygin get_board_sensors(const struct device *dev) 580d0ddfd24SEugene Shalygin { 581d0ddfd24SEugene Shalygin const struct dmi_system_id *dmi_entry; 582d0ddfd24SEugene Shalygin 583d0ddfd24SEugene Shalygin dmi_entry = dmi_first_match(asus_ec_dmi_table); 584d0ddfd24SEugene Shalygin if (!dmi_entry) { 585d0ddfd24SEugene Shalygin dev_info(dev, "Unsupported board"); 586d0ddfd24SEugene Shalygin return 0; 587d0ddfd24SEugene Shalygin } 588d0ddfd24SEugene Shalygin 589d0ddfd24SEugene Shalygin return (unsigned long)dmi_entry->driver_data; 590d0ddfd24SEugene Shalygin } 591d0ddfd24SEugene Shalygin 592d0ddfd24SEugene Shalygin static int __init configure_sensor_setup(struct device *dev) 593d0ddfd24SEugene Shalygin { 594d0ddfd24SEugene Shalygin struct ec_sensors_data *ec_data = dev_get_drvdata(dev); 595d0ddfd24SEugene Shalygin int nr_count[hwmon_max] = { 0 }, nr_types = 0; 596d0ddfd24SEugene Shalygin struct device *hwdev; 597d0ddfd24SEugene Shalygin struct hwmon_channel_info *asus_ec_hwmon_chan; 598d0ddfd24SEugene Shalygin const struct hwmon_channel_info **ptr_asus_ec_ci; 599d0ddfd24SEugene Shalygin const struct hwmon_chip_info *chip_info; 600d0ddfd24SEugene Shalygin const struct ec_sensor_info *si; 601d0ddfd24SEugene Shalygin enum hwmon_sensor_types type; 602d0ddfd24SEugene Shalygin unsigned int i; 603d0ddfd24SEugene Shalygin 604d0ddfd24SEugene Shalygin ec_data->board_sensors = get_board_sensors(dev); 605d0ddfd24SEugene Shalygin if (!ec_data->board_sensors) { 606d0ddfd24SEugene Shalygin return -ENODEV; 607d0ddfd24SEugene Shalygin } 608d0ddfd24SEugene Shalygin 609d0ddfd24SEugene Shalygin ec_data->nr_sensors = board_sensors_count(ec_data->board_sensors); 610d0ddfd24SEugene Shalygin ec_data->sensors = devm_kcalloc(dev, ec_data->nr_sensors, 611d0ddfd24SEugene Shalygin sizeof(struct ec_sensor), GFP_KERNEL); 612d0ddfd24SEugene Shalygin 613d0ddfd24SEugene Shalygin setup_sensor_data(ec_data); 614d0ddfd24SEugene Shalygin ec_data->registers = devm_kcalloc(dev, ec_data->nr_registers, 615d0ddfd24SEugene Shalygin sizeof(u16), GFP_KERNEL); 616d0ddfd24SEugene Shalygin ec_data->read_buffer = devm_kcalloc(dev, ec_data->nr_registers, 617d0ddfd24SEugene Shalygin sizeof(u8), GFP_KERNEL); 618d0ddfd24SEugene Shalygin 619d0ddfd24SEugene Shalygin if (!ec_data->registers || !ec_data->read_buffer) { 620d0ddfd24SEugene Shalygin return -ENOMEM; 621d0ddfd24SEugene Shalygin } 622d0ddfd24SEugene Shalygin 623d0ddfd24SEugene Shalygin fill_ec_registers(ec_data); 624d0ddfd24SEugene Shalygin 625d0ddfd24SEugene Shalygin ec_data->aml_mutex = asus_hw_access_mutex(dev); 626d0ddfd24SEugene Shalygin 627d0ddfd24SEugene Shalygin for (i = 0; i < ec_data->nr_sensors; ++i) { 628d0ddfd24SEugene Shalygin si = get_sensor_info(ec_data, i); 629d0ddfd24SEugene Shalygin if (!nr_count[si->type]) 630d0ddfd24SEugene Shalygin ++nr_types; 631d0ddfd24SEugene Shalygin ++nr_count[si->type]; 632d0ddfd24SEugene Shalygin } 633d0ddfd24SEugene Shalygin 634d0ddfd24SEugene Shalygin if (nr_count[hwmon_temp]) 635d0ddfd24SEugene Shalygin nr_count[hwmon_chip]++, nr_types++; 636d0ddfd24SEugene Shalygin 637d0ddfd24SEugene Shalygin asus_ec_hwmon_chan = devm_kcalloc( 638d0ddfd24SEugene Shalygin dev, nr_types, sizeof(*asus_ec_hwmon_chan), GFP_KERNEL); 639d0ddfd24SEugene Shalygin if (!asus_ec_hwmon_chan) 640d0ddfd24SEugene Shalygin return -ENOMEM; 641d0ddfd24SEugene Shalygin 642d0ddfd24SEugene Shalygin ptr_asus_ec_ci = devm_kcalloc(dev, nr_types + 1, 643d0ddfd24SEugene Shalygin sizeof(*ptr_asus_ec_ci), GFP_KERNEL); 644d0ddfd24SEugene Shalygin if (!ptr_asus_ec_ci) 645d0ddfd24SEugene Shalygin return -ENOMEM; 646d0ddfd24SEugene Shalygin 647d0ddfd24SEugene Shalygin asus_ec_chip_info.info = ptr_asus_ec_ci; 648d0ddfd24SEugene Shalygin chip_info = &asus_ec_chip_info; 649d0ddfd24SEugene Shalygin 650d0ddfd24SEugene Shalygin for (type = 0; type < hwmon_max; ++type) { 651d0ddfd24SEugene Shalygin if (!nr_count[type]) 652d0ddfd24SEugene Shalygin continue; 653d0ddfd24SEugene Shalygin 654d0ddfd24SEugene Shalygin asus_ec_hwmon_add_chan_info(asus_ec_hwmon_chan, dev, 655d0ddfd24SEugene Shalygin nr_count[type], type, 656d0ddfd24SEugene Shalygin hwmon_attributes[type]); 657d0ddfd24SEugene Shalygin *ptr_asus_ec_ci++ = asus_ec_hwmon_chan++; 658d0ddfd24SEugene Shalygin } 659d0ddfd24SEugene Shalygin 660d0ddfd24SEugene Shalygin dev_info(dev, "board has %d EC sensors that span %d registers", 661d0ddfd24SEugene Shalygin ec_data->nr_sensors, ec_data->nr_registers); 662d0ddfd24SEugene Shalygin 663d0ddfd24SEugene Shalygin hwdev = devm_hwmon_device_register_with_info(dev, "asusec", 664d0ddfd24SEugene Shalygin ec_data, chip_info, NULL); 665d0ddfd24SEugene Shalygin 666d0ddfd24SEugene Shalygin return PTR_ERR_OR_ZERO(hwdev); 667d0ddfd24SEugene Shalygin } 668d0ddfd24SEugene Shalygin 669d0ddfd24SEugene Shalygin static int __init asus_ec_probe(struct platform_device *pdev) 670d0ddfd24SEugene Shalygin { 67188846ff7SDan Carpenter struct ec_sensors_data *state; 672d0ddfd24SEugene Shalygin int status = 0; 673d0ddfd24SEugene Shalygin 674d0ddfd24SEugene Shalygin state = devm_kzalloc(&pdev->dev, sizeof(struct ec_sensors_data), 675d0ddfd24SEugene Shalygin GFP_KERNEL); 676d0ddfd24SEugene Shalygin 677d0ddfd24SEugene Shalygin if (!state) { 678d0ddfd24SEugene Shalygin return -ENOMEM; 679d0ddfd24SEugene Shalygin } 680d0ddfd24SEugene Shalygin 681d0ddfd24SEugene Shalygin dev_set_drvdata(&pdev->dev, state); 682d0ddfd24SEugene Shalygin status = configure_sensor_setup(&pdev->dev); 683d0ddfd24SEugene Shalygin return status; 684d0ddfd24SEugene Shalygin } 685d0ddfd24SEugene Shalygin 686d0ddfd24SEugene Shalygin static const struct acpi_device_id acpi_ec_ids[] = { 687d0ddfd24SEugene Shalygin /* Embedded Controller Device */ 688d0ddfd24SEugene Shalygin { "PNP0C09", 0 }, 689d0ddfd24SEugene Shalygin {} 690d0ddfd24SEugene Shalygin }; 691d0ddfd24SEugene Shalygin 692d0ddfd24SEugene Shalygin static struct platform_driver asus_ec_sensors_platform_driver = { 693d0ddfd24SEugene Shalygin .driver = { 694d0ddfd24SEugene Shalygin .name = "asus-ec-sensors", 695d0ddfd24SEugene Shalygin .acpi_match_table = acpi_ec_ids, 696d0ddfd24SEugene Shalygin }, 697d0ddfd24SEugene Shalygin }; 698d0ddfd24SEugene Shalygin 699d0ddfd24SEugene Shalygin MODULE_DEVICE_TABLE(dmi, asus_ec_dmi_table); 700d0ddfd24SEugene Shalygin module_platform_driver_probe(asus_ec_sensors_platform_driver, asus_ec_probe); 701d0ddfd24SEugene Shalygin 702d0ddfd24SEugene Shalygin module_param_named(mutex_path, mutex_path_override, charp, 0); 703d0ddfd24SEugene Shalygin MODULE_PARM_DESC(mutex_path, 704d0ddfd24SEugene Shalygin "Override ACPI mutex path used to guard access to hardware"); 705d0ddfd24SEugene Shalygin 706d0ddfd24SEugene Shalygin MODULE_AUTHOR("Eugene Shalygin <eugene.shalygin@gmail.com>"); 707d0ddfd24SEugene Shalygin MODULE_DESCRIPTION( 708d0ddfd24SEugene Shalygin "HWMON driver for sensors accessible via ACPI EC in ASUS motherboards"); 709d0ddfd24SEugene Shalygin MODULE_LICENSE("GPL"); 710