1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #ifndef _CORESIGHT_CORESIGHT_TPDA_H
7 #define _CORESIGHT_CORESIGHT_TPDA_H
8 
9 #define TPDA_CR			(0x000)
10 #define TPDA_Pn_CR(n)		(0x004 + (n * 4))
11 /* Aggregator port enable bit */
12 #define TPDA_Pn_CR_ENA		BIT(0)
13 /* Aggregator port DSB data set element size bit */
14 #define TPDA_Pn_CR_DSBSIZE		BIT(8)
15 
16 #define TPDA_MAX_INPORTS	32
17 
18 /* Bits 6 ~ 12 is for atid value */
19 #define TPDA_CR_ATID		GENMASK(12, 6)
20 
21 /**
22  * struct tpda_drvdata - specifics associated to an TPDA component
23  * @base:       memory mapped base address for this component.
24  * @dev:        The device entity associated to this component.
25  * @csdev:      component vitals needed by the framework.
26  * @spinlock:   lock for the drvdata value.
27  * @enable:     enable status of the component.
28  */
29 struct tpda_drvdata {
30 	void __iomem		*base;
31 	struct device		*dev;
32 	struct coresight_device	*csdev;
33 	spinlock_t		spinlock;
34 	u8			atid;
35 };
36 
37 #endif  /* _CORESIGHT_CORESIGHT_TPDA_H */
38