1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_CORESIGHT_TPDM_H 7 #define _CORESIGHT_CORESIGHT_TPDM_H 8 9 /* The max number of the datasets that TPDM supports */ 10 #define TPDM_DATASETS 7 11 12 /* DSB Subunit Registers */ 13 #define TPDM_DSB_CR (0x780) 14 /* Enable bit for DSB subunit */ 15 #define TPDM_DSB_CR_ENA BIT(0) 16 17 /* TPDM integration test registers */ 18 #define TPDM_ITATBCNTRL (0xEF0) 19 #define TPDM_ITCNTRL (0xF00) 20 21 /* Register value for integration test */ 22 #define ATBCNTRL_VAL_32 0xC00F1409 23 #define ATBCNTRL_VAL_64 0xC01F1409 24 25 /* 26 * Number of cycles to write value when 27 * integration test. 28 */ 29 #define INTEGRATION_TEST_CYCLE 10 30 31 /** 32 * The bits of PERIPHIDR0 register. 33 * The fields [6:0] of PERIPHIDR0 are used to determine what 34 * interfaces and subunits are present on a given TPDM. 35 * 36 * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0 37 * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0 38 */ 39 40 #define TPDM_PIDR0_DS_IMPDEF BIT(0) 41 #define TPDM_PIDR0_DS_DSB BIT(1) 42 43 /** 44 * struct tpdm_drvdata - specifics associated to an TPDM component 45 * @base: memory mapped base address for this component. 46 * @dev: The device entity associated to this component. 47 * @csdev: component vitals needed by the framework. 48 * @spinlock: lock for the drvdata value. 49 * @enable: enable status of the component. 50 * @datasets: The datasets types present of the TPDM. 51 */ 52 53 struct tpdm_drvdata { 54 void __iomem *base; 55 struct device *dev; 56 struct coresight_device *csdev; 57 spinlock_t spinlock; 58 bool enable; 59 unsigned long datasets; 60 }; 61 62 #endif /* _CORESIGHT_CORESIGHT_TPDM_H */ 63