1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight Trace Port Interface Unit driver 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/err.h> 14 #include <linux/slab.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/coresight.h> 17 #include <linux/amba/bus.h> 18 #include <linux/clk.h> 19 20 #include "coresight-priv.h" 21 22 #define TPIU_SUPP_PORTSZ 0x000 23 #define TPIU_CURR_PORTSZ 0x004 24 #define TPIU_SUPP_TRIGMODES 0x100 25 #define TPIU_TRIG_CNTRVAL 0x104 26 #define TPIU_TRIG_MULT 0x108 27 #define TPIU_SUPP_TESTPATM 0x200 28 #define TPIU_CURR_TESTPATM 0x204 29 #define TPIU_TEST_PATREPCNTR 0x208 30 #define TPIU_FFSR 0x300 31 #define TPIU_FFCR 0x304 32 #define TPIU_FSYNC_CNTR 0x308 33 #define TPIU_EXTCTL_INPORT 0x400 34 #define TPIU_EXTCTL_OUTPORT 0x404 35 #define TPIU_ITTRFLINACK 0xee4 36 #define TPIU_ITTRFLIN 0xee8 37 #define TPIU_ITATBDATA0 0xeec 38 #define TPIU_ITATBCTR2 0xef0 39 #define TPIU_ITATBCTR1 0xef4 40 #define TPIU_ITATBCTR0 0xef8 41 42 /** register definition **/ 43 /* FFSR - 0x300 */ 44 #define FFSR_FT_STOPPED_BIT 1 45 /* FFCR - 0x304 */ 46 #define FFCR_FON_MAN_BIT 6 47 #define FFCR_FON_MAN BIT(6) 48 #define FFCR_STOP_FI BIT(12) 49 50 /** 51 * @base: memory mapped base address for this component. 52 * @dev: the device entity associated to this component. 53 * @atclk: optional clock for the core parts of the TPIU. 54 * @csdev: component vitals needed by the framework. 55 */ 56 struct tpiu_drvdata { 57 void __iomem *base; 58 struct device *dev; 59 struct clk *atclk; 60 struct coresight_device *csdev; 61 }; 62 63 static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) 64 { 65 CS_UNLOCK(drvdata->base); 66 67 /* TODO: fill this up */ 68 69 CS_LOCK(drvdata->base); 70 } 71 72 static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused) 73 { 74 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 75 76 tpiu_enable_hw(drvdata); 77 atomic_inc(csdev->refcnt); 78 dev_dbg(drvdata->dev, "TPIU enabled\n"); 79 return 0; 80 } 81 82 static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) 83 { 84 CS_UNLOCK(drvdata->base); 85 86 /* Clear formatter and stop on flush */ 87 writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); 88 /* Generate manual flush */ 89 writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); 90 /* Wait for flush to complete */ 91 coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); 92 /* Wait for formatter to stop */ 93 coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); 94 95 CS_LOCK(drvdata->base); 96 } 97 98 static int tpiu_disable(struct coresight_device *csdev) 99 { 100 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 101 102 if (atomic_dec_return(csdev->refcnt)) 103 return -EBUSY; 104 105 tpiu_disable_hw(drvdata); 106 107 dev_dbg(drvdata->dev, "TPIU disabled\n"); 108 return 0; 109 } 110 111 static const struct coresight_ops_sink tpiu_sink_ops = { 112 .enable = tpiu_enable, 113 .disable = tpiu_disable, 114 }; 115 116 static const struct coresight_ops tpiu_cs_ops = { 117 .sink_ops = &tpiu_sink_ops, 118 }; 119 120 static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) 121 { 122 int ret; 123 void __iomem *base; 124 struct device *dev = &adev->dev; 125 struct coresight_platform_data *pdata = NULL; 126 struct tpiu_drvdata *drvdata; 127 struct resource *res = &adev->res; 128 struct coresight_desc desc = { 0 }; 129 struct device_node *np = adev->dev.of_node; 130 131 if (np) { 132 pdata = of_get_coresight_platform_data(dev, np); 133 if (IS_ERR(pdata)) 134 return PTR_ERR(pdata); 135 adev->dev.platform_data = pdata; 136 } 137 138 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 139 if (!drvdata) 140 return -ENOMEM; 141 142 drvdata->dev = &adev->dev; 143 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 144 if (!IS_ERR(drvdata->atclk)) { 145 ret = clk_prepare_enable(drvdata->atclk); 146 if (ret) 147 return ret; 148 } 149 dev_set_drvdata(dev, drvdata); 150 151 /* Validity for the resource is already checked by the AMBA core */ 152 base = devm_ioremap_resource(dev, res); 153 if (IS_ERR(base)) 154 return PTR_ERR(base); 155 156 drvdata->base = base; 157 158 /* Disable tpiu to support older devices */ 159 tpiu_disable_hw(drvdata); 160 161 desc.type = CORESIGHT_DEV_TYPE_SINK; 162 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT; 163 desc.ops = &tpiu_cs_ops; 164 desc.pdata = pdata; 165 desc.dev = dev; 166 drvdata->csdev = coresight_register(&desc); 167 168 if (!IS_ERR(drvdata->csdev)) { 169 pm_runtime_put(&adev->dev); 170 return 0; 171 } 172 173 return PTR_ERR(drvdata->csdev); 174 } 175 176 #ifdef CONFIG_PM 177 static int tpiu_runtime_suspend(struct device *dev) 178 { 179 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev); 180 181 if (drvdata && !IS_ERR(drvdata->atclk)) 182 clk_disable_unprepare(drvdata->atclk); 183 184 return 0; 185 } 186 187 static int tpiu_runtime_resume(struct device *dev) 188 { 189 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev); 190 191 if (drvdata && !IS_ERR(drvdata->atclk)) 192 clk_prepare_enable(drvdata->atclk); 193 194 return 0; 195 } 196 #endif 197 198 static const struct dev_pm_ops tpiu_dev_pm_ops = { 199 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL) 200 }; 201 202 static const struct amba_id tpiu_ids[] = { 203 { 204 .id = 0x000bb912, 205 .mask = 0x000fffff, 206 }, 207 { 208 .id = 0x0004b912, 209 .mask = 0x0007ffff, 210 }, 211 { 212 /* Coresight SoC-600 */ 213 .id = 0x000bb9e7, 214 .mask = 0x000fffff, 215 }, 216 { 0, 0}, 217 }; 218 219 static struct amba_driver tpiu_driver = { 220 .drv = { 221 .name = "coresight-tpiu", 222 .owner = THIS_MODULE, 223 .pm = &tpiu_dev_pm_ops, 224 .suppress_bind_attrs = true, 225 }, 226 .probe = tpiu_probe, 227 .id_table = tpiu_ids, 228 }; 229 builtin_amba_driver(tpiu_driver); 230