1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare I2C adapter driver. 4 * 5 * Based on the TI DAVINCI I2C adapter driver. 6 * 7 * Copyright (C) 2006 Texas Instruments. 8 * Copyright (C) 2007 MontaVista Software Inc. 9 * Copyright (C) 2009 Provigent Ltd. 10 */ 11 12 #include <linux/bits.h> 13 #include <linux/compiler_types.h> 14 #include <linux/completion.h> 15 #include <linux/dev_printk.h> 16 #include <linux/errno.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/types.h> 20 21 #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ 22 I2C_FUNC_SMBUS_BYTE | \ 23 I2C_FUNC_SMBUS_BYTE_DATA | \ 24 I2C_FUNC_SMBUS_WORD_DATA | \ 25 I2C_FUNC_SMBUS_BLOCK_DATA | \ 26 I2C_FUNC_SMBUS_I2C_BLOCK) 27 28 #define DW_IC_CON_MASTER BIT(0) 29 #define DW_IC_CON_SPEED_STD (1 << 1) 30 #define DW_IC_CON_SPEED_FAST (2 << 1) 31 #define DW_IC_CON_SPEED_HIGH (3 << 1) 32 #define DW_IC_CON_SPEED_MASK GENMASK(2, 1) 33 #define DW_IC_CON_10BITADDR_SLAVE BIT(3) 34 #define DW_IC_CON_10BITADDR_MASTER BIT(4) 35 #define DW_IC_CON_RESTART_EN BIT(5) 36 #define DW_IC_CON_SLAVE_DISABLE BIT(6) 37 #define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) 38 #define DW_IC_CON_TX_EMPTY_CTRL BIT(8) 39 #define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) 40 #define DW_IC_CON_BUS_CLEAR_CTRL BIT(11) 41 42 #define DW_IC_DATA_CMD_DAT GENMASK(7, 0) 43 44 /* 45 * Registers offset 46 */ 47 #define DW_IC_CON 0x00 48 #define DW_IC_TAR 0x04 49 #define DW_IC_SAR 0x08 50 #define DW_IC_DATA_CMD 0x10 51 #define DW_IC_SS_SCL_HCNT 0x14 52 #define DW_IC_SS_SCL_LCNT 0x18 53 #define DW_IC_FS_SCL_HCNT 0x1c 54 #define DW_IC_FS_SCL_LCNT 0x20 55 #define DW_IC_HS_SCL_HCNT 0x24 56 #define DW_IC_HS_SCL_LCNT 0x28 57 #define DW_IC_INTR_STAT 0x2c 58 #define DW_IC_INTR_MASK 0x30 59 #define DW_IC_RAW_INTR_STAT 0x34 60 #define DW_IC_RX_TL 0x38 61 #define DW_IC_TX_TL 0x3c 62 #define DW_IC_CLR_INTR 0x40 63 #define DW_IC_CLR_RX_UNDER 0x44 64 #define DW_IC_CLR_RX_OVER 0x48 65 #define DW_IC_CLR_TX_OVER 0x4c 66 #define DW_IC_CLR_RD_REQ 0x50 67 #define DW_IC_CLR_TX_ABRT 0x54 68 #define DW_IC_CLR_RX_DONE 0x58 69 #define DW_IC_CLR_ACTIVITY 0x5c 70 #define DW_IC_CLR_STOP_DET 0x60 71 #define DW_IC_CLR_START_DET 0x64 72 #define DW_IC_CLR_GEN_CALL 0x68 73 #define DW_IC_ENABLE 0x6c 74 #define DW_IC_STATUS 0x70 75 #define DW_IC_TXFLR 0x74 76 #define DW_IC_RXFLR 0x78 77 #define DW_IC_SDA_HOLD 0x7c 78 #define DW_IC_TX_ABRT_SOURCE 0x80 79 #define DW_IC_ENABLE_STATUS 0x9c 80 #define DW_IC_CLR_RESTART_DET 0xa8 81 #define DW_IC_COMP_PARAM_1 0xf4 82 #define DW_IC_COMP_VERSION 0xf8 83 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */ 84 #define DW_IC_COMP_TYPE 0xfc 85 #define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */ 86 87 #define DW_IC_INTR_RX_UNDER BIT(0) 88 #define DW_IC_INTR_RX_OVER BIT(1) 89 #define DW_IC_INTR_RX_FULL BIT(2) 90 #define DW_IC_INTR_TX_OVER BIT(3) 91 #define DW_IC_INTR_TX_EMPTY BIT(4) 92 #define DW_IC_INTR_RD_REQ BIT(5) 93 #define DW_IC_INTR_TX_ABRT BIT(6) 94 #define DW_IC_INTR_RX_DONE BIT(7) 95 #define DW_IC_INTR_ACTIVITY BIT(8) 96 #define DW_IC_INTR_STOP_DET BIT(9) 97 #define DW_IC_INTR_START_DET BIT(10) 98 #define DW_IC_INTR_GEN_CALL BIT(11) 99 #define DW_IC_INTR_RESTART_DET BIT(12) 100 101 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ 102 DW_IC_INTR_TX_ABRT | \ 103 DW_IC_INTR_STOP_DET) 104 #define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \ 105 DW_IC_INTR_TX_EMPTY) 106 #define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \ 107 DW_IC_INTR_RX_UNDER | \ 108 DW_IC_INTR_RD_REQ) 109 110 #define DW_IC_STATUS_ACTIVITY BIT(0) 111 #define DW_IC_STATUS_TFE BIT(2) 112 #define DW_IC_STATUS_RFNE BIT(3) 113 #define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) 114 #define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) 115 116 #define DW_IC_SDA_HOLD_RX_SHIFT 16 117 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16) 118 119 #define DW_IC_ERR_TX_ABRT 0x1 120 121 #define DW_IC_TAR_10BITADDR_MASTER BIT(12) 122 123 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3)) 124 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2) 125 126 /* 127 * Sofware status flags 128 */ 129 #define STATUS_ACTIVE BIT(0) 130 #define STATUS_WRITE_IN_PROGRESS BIT(1) 131 #define STATUS_READ_IN_PROGRESS BIT(2) 132 #define STATUS_MASK GENMASK(2, 0) 133 134 /* 135 * operation modes 136 */ 137 #define DW_IC_MASTER 0 138 #define DW_IC_SLAVE 1 139 140 /* 141 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register 142 * 143 * Only expected abort codes are listed here 144 * refer to the datasheet for the full list 145 */ 146 #define ABRT_7B_ADDR_NOACK 0 147 #define ABRT_10ADDR1_NOACK 1 148 #define ABRT_10ADDR2_NOACK 2 149 #define ABRT_TXDATA_NOACK 3 150 #define ABRT_GCALL_NOACK 4 151 #define ABRT_GCALL_READ 5 152 #define ABRT_SBYTE_ACKDET 7 153 #define ABRT_SBYTE_NORSTRT 9 154 #define ABRT_10B_RD_NORSTRT 10 155 #define ABRT_MASTER_DIS 11 156 #define ARB_LOST 12 157 #define ABRT_SLAVE_FLUSH_TXFIFO 13 158 #define ABRT_SLAVE_ARBLOST 14 159 #define ABRT_SLAVE_RD_INTX 15 160 161 #define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK) 162 #define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK) 163 #define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK) 164 #define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK) 165 #define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK) 166 #define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ) 167 #define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET) 168 #define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT) 169 #define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT) 170 #define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS) 171 #define DW_IC_TX_ARB_LOST BIT(ARB_LOST) 172 #define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX) 173 #define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST) 174 #define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO) 175 176 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ 177 DW_IC_TX_ABRT_10ADDR1_NOACK | \ 178 DW_IC_TX_ABRT_10ADDR2_NOACK | \ 179 DW_IC_TX_ABRT_TXDATA_NOACK | \ 180 DW_IC_TX_ABRT_GCALL_NOACK) 181 182 struct clk; 183 struct device; 184 struct reset_control; 185 186 /** 187 * struct dw_i2c_dev - private i2c-designware data 188 * @dev: driver model device node 189 * @map: IO registers map 190 * @sysmap: System controller registers map 191 * @base: IO registers pointer 192 * @ext: Extended IO registers pointer 193 * @cmd_complete: tx completion indicator 194 * @clk: input reference clock 195 * @pclk: clock required to access the registers 196 * @rst: optional reset for the controller 197 * @slave: represent an I2C slave device 198 * @get_clk_rate_khz: callback to retrieve IP specific bus speed 199 * @cmd_err: run time hadware error code 200 * @msgs: points to an array of messages currently being transferred 201 * @msgs_num: the number of elements in msgs 202 * @msg_write_idx: the element index of the current tx message in the msgs array 203 * @tx_buf_len: the length of the current tx buffer 204 * @tx_buf: the current tx buffer 205 * @msg_read_idx: the element index of the current rx message in the msgs array 206 * @rx_buf_len: the length of the current rx buffer 207 * @rx_buf: the current rx buffer 208 * @msg_err: error status of the current transfer 209 * @status: i2c master status, one of STATUS_* 210 * @abort_source: copy of the TX_ABRT_SOURCE register 211 * @irq: interrupt number for the i2c master 212 * @flags: platform specific flags like type of IO accessors or model 213 * @adapter: i2c subsystem adapter node 214 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support 215 * @master_cfg: configuration for the master device 216 * @slave_cfg: configuration for the slave device 217 * @tx_fifo_depth: depth of the hardware tx fifo 218 * @rx_fifo_depth: depth of the hardware rx fifo 219 * @rx_outstanding: current master-rx elements in tx fifo 220 * @timings: bus clock frequency, SDA hold and other timings 221 * @sda_hold_time: SDA hold value 222 * @ss_hcnt: standard speed HCNT value 223 * @ss_lcnt: standard speed LCNT value 224 * @fs_hcnt: fast speed HCNT value 225 * @fs_lcnt: fast speed LCNT value 226 * @fp_hcnt: fast plus HCNT value 227 * @fp_lcnt: fast plus LCNT value 228 * @hs_hcnt: high speed HCNT value 229 * @hs_lcnt: high speed LCNT value 230 * @acquire_lock: function to acquire a hardware lock on the bus 231 * @release_lock: function to release a hardware lock on the bus 232 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's 233 * -1 if there is no semaphore. 234 * @shared_with_punit: true if this bus is shared with the SoCs PUNIT 235 * @disable: function to disable the controller 236 * @init: function to initialize the I2C hardware 237 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing 238 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE 239 * @rinfo: I²C GPIO recovery information 240 * 241 * HCNT and LCNT parameters can be used if the platform knows more accurate 242 * values than the one computed based only on the input clock frequency. 243 * Leave them to be %0 if not used. 244 */ 245 struct dw_i2c_dev { 246 struct device *dev; 247 struct regmap *map; 248 struct regmap *sysmap; 249 void __iomem *base; 250 void __iomem *ext; 251 struct completion cmd_complete; 252 struct clk *clk; 253 struct clk *pclk; 254 struct reset_control *rst; 255 struct i2c_client *slave; 256 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); 257 int cmd_err; 258 struct i2c_msg *msgs; 259 int msgs_num; 260 int msg_write_idx; 261 u32 tx_buf_len; 262 u8 *tx_buf; 263 int msg_read_idx; 264 u32 rx_buf_len; 265 u8 *rx_buf; 266 int msg_err; 267 unsigned int status; 268 unsigned int abort_source; 269 int irq; 270 u32 flags; 271 struct i2c_adapter adapter; 272 u32 functionality; 273 u32 master_cfg; 274 u32 slave_cfg; 275 unsigned int tx_fifo_depth; 276 unsigned int rx_fifo_depth; 277 int rx_outstanding; 278 struct i2c_timings timings; 279 u32 sda_hold_time; 280 u16 ss_hcnt; 281 u16 ss_lcnt; 282 u16 fs_hcnt; 283 u16 fs_lcnt; 284 u16 fp_hcnt; 285 u16 fp_lcnt; 286 u16 hs_hcnt; 287 u16 hs_lcnt; 288 int (*acquire_lock)(void); 289 void (*release_lock)(void); 290 int semaphore_idx; 291 bool shared_with_punit; 292 void (*disable)(struct dw_i2c_dev *dev); 293 int (*init)(struct dw_i2c_dev *dev); 294 int (*set_sda_hold_time)(struct dw_i2c_dev *dev); 295 int mode; 296 struct i2c_bus_recovery_info rinfo; 297 }; 298 299 #define ACCESS_INTR_MASK BIT(0) 300 #define ACCESS_NO_IRQ_SUSPEND BIT(1) 301 #define ARBITRATION_SEMAPHORE BIT(2) 302 303 #define MODEL_MSCC_OCELOT BIT(8) 304 #define MODEL_BAIKAL_BT1 BIT(9) 305 #define MODEL_AMD_NAVI_GPU BIT(10) 306 #define MODEL_MASK GENMASK(11, 8) 307 308 /* 309 * Enable UCSI interrupt by writing 0xd at register 310 * offset 0x474 specified in hardware specification. 311 */ 312 #define AMD_UCSI_INTR_REG 0x474 313 #define AMD_UCSI_INTR_EN 0xd 314 315 struct i2c_dw_semaphore_callbacks { 316 int (*probe)(struct dw_i2c_dev *dev); 317 void (*remove)(struct dw_i2c_dev *dev); 318 }; 319 320 int i2c_dw_init_regmap(struct dw_i2c_dev *dev); 321 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset); 322 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset); 323 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev); 324 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev); 325 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare); 326 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev); 327 void i2c_dw_release_lock(struct dw_i2c_dev *dev); 328 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev); 329 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev); 330 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev); 331 u32 i2c_dw_func(struct i2c_adapter *adap); 332 void i2c_dw_disable(struct dw_i2c_dev *dev); 333 334 static inline void __i2c_dw_enable(struct dw_i2c_dev *dev) 335 { 336 dev->status |= STATUS_ACTIVE; 337 regmap_write(dev->map, DW_IC_ENABLE, 1); 338 } 339 340 static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev) 341 { 342 regmap_write(dev->map, DW_IC_ENABLE, 0); 343 dev->status &= ~STATUS_ACTIVE; 344 } 345 346 void __i2c_dw_disable(struct dw_i2c_dev *dev); 347 348 extern void i2c_dw_configure_master(struct dw_i2c_dev *dev); 349 extern int i2c_dw_probe_master(struct dw_i2c_dev *dev); 350 351 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE) 352 extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev); 353 extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev); 354 #else 355 static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { } 356 static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; } 357 #endif 358 359 static inline int i2c_dw_probe(struct dw_i2c_dev *dev) 360 { 361 switch (dev->mode) { 362 case DW_IC_SLAVE: 363 return i2c_dw_probe_slave(dev); 364 case DW_IC_MASTER: 365 return i2c_dw_probe_master(dev); 366 default: 367 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); 368 return -EINVAL; 369 } 370 } 371 372 static inline void i2c_dw_configure(struct dw_i2c_dev *dev) 373 { 374 if (i2c_detect_slave_mode(dev->dev)) 375 i2c_dw_configure_slave(dev); 376 else 377 i2c_dw_configure_master(dev); 378 } 379 380 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL) 381 int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev); 382 #endif 383 384 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP) 385 int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev); 386 #endif 387 388 int i2c_dw_validate_speed(struct dw_i2c_dev *dev); 389 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev); 390 391 #if IS_ENABLED(CONFIG_ACPI) 392 int i2c_dw_acpi_configure(struct device *device); 393 #else 394 static inline int i2c_dw_acpi_configure(struct device *device) { return -ENODEV; } 395 #endif 396