1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes 81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes 82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes 83 * 84 * Features supported by this driver: 85 * Software PEC no 86 * Hardware PEC yes 87 * Block buffer yes 88 * Block process call transaction yes 89 * I2C block read transaction yes (doesn't use the block buffer) 90 * Slave mode no 91 * SMBus Host Notify yes 92 * Interrupt processing yes 93 * 94 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 95 */ 96 97 #define DRV_NAME "i801_smbus" 98 99 #include <linux/interrupt.h> 100 #include <linux/module.h> 101 #include <linux/pci.h> 102 #include <linux/kernel.h> 103 #include <linux/stddef.h> 104 #include <linux/delay.h> 105 #include <linux/ioport.h> 106 #include <linux/init.h> 107 #include <linux/i2c.h> 108 #include <linux/i2c-smbus.h> 109 #include <linux/acpi.h> 110 #include <linux/io.h> 111 #include <linux/dmi.h> 112 #include <linux/slab.h> 113 #include <linux/string.h> 114 #include <linux/completion.h> 115 #include <linux/err.h> 116 #include <linux/platform_device.h> 117 #include <linux/platform_data/itco_wdt.h> 118 #include <linux/platform_data/x86/p2sb.h> 119 #include <linux/pm_runtime.h> 120 #include <linux/mutex.h> 121 122 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 123 #include <linux/gpio/machine.h> 124 #include <linux/platform_data/i2c-mux-gpio.h> 125 #endif 126 127 /* I801 SMBus address offsets */ 128 #define SMBHSTSTS(p) (0 + (p)->smba) 129 #define SMBHSTCNT(p) (2 + (p)->smba) 130 #define SMBHSTCMD(p) (3 + (p)->smba) 131 #define SMBHSTADD(p) (4 + (p)->smba) 132 #define SMBHSTDAT0(p) (5 + (p)->smba) 133 #define SMBHSTDAT1(p) (6 + (p)->smba) 134 #define SMBBLKDAT(p) (7 + (p)->smba) 135 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 136 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 137 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 138 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 139 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 140 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 141 142 /* PCI Address Constants */ 143 #define SMBBAR 4 144 #define SMBHSTCFG 0x040 145 #define TCOBASE 0x050 146 #define TCOCTL 0x054 147 148 #define SBREG_SMBCTRL 0xc6000c 149 #define SBREG_SMBCTRL_DNV 0xcf000c 150 151 /* Host configuration bits for SMBHSTCFG */ 152 #define SMBHSTCFG_HST_EN BIT(0) 153 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 154 #define SMBHSTCFG_I2C_EN BIT(2) 155 #define SMBHSTCFG_SPD_WD BIT(4) 156 157 /* TCO configuration bits for TCOCTL */ 158 #define TCOCTL_EN BIT(8) 159 160 /* Auxiliary status register bits, ICH4+ only */ 161 #define SMBAUXSTS_CRCE BIT(0) 162 #define SMBAUXSTS_STCO BIT(1) 163 164 /* Auxiliary control register bits, ICH4+ only */ 165 #define SMBAUXCTL_CRC BIT(0) 166 #define SMBAUXCTL_E32B BIT(1) 167 168 /* I801 command constants */ 169 #define I801_QUICK 0x00 170 #define I801_BYTE 0x04 171 #define I801_BYTE_DATA 0x08 172 #define I801_WORD_DATA 0x0C 173 #define I801_PROC_CALL 0x10 174 #define I801_BLOCK_DATA 0x14 175 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 176 #define I801_BLOCK_PROC_CALL 0x1C 177 178 /* I801 Host Control register bits */ 179 #define SMBHSTCNT_INTREN BIT(0) 180 #define SMBHSTCNT_KILL BIT(1) 181 #define SMBHSTCNT_LAST_BYTE BIT(5) 182 #define SMBHSTCNT_START BIT(6) 183 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 184 185 /* I801 Hosts Status register bits */ 186 #define SMBHSTSTS_BYTE_DONE BIT(7) 187 #define SMBHSTSTS_INUSE_STS BIT(6) 188 #define SMBHSTSTS_SMBALERT_STS BIT(5) 189 #define SMBHSTSTS_FAILED BIT(4) 190 #define SMBHSTSTS_BUS_ERR BIT(3) 191 #define SMBHSTSTS_DEV_ERR BIT(2) 192 #define SMBHSTSTS_INTR BIT(1) 193 #define SMBHSTSTS_HOST_BUSY BIT(0) 194 195 /* Host Notify Status register bits */ 196 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 197 198 /* Host Notify Command register bits */ 199 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 200 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 201 202 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 203 SMBHSTSTS_DEV_ERR) 204 205 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 206 STATUS_ERROR_FLAGS) 207 208 /* Older devices have their ID defined in <linux/pci_ids.h> */ 209 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 214 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 215 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 217 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 221 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 222 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 223 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 224 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 225 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 226 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 227 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 228 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 229 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 230 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 231 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 232 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 235 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796 236 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 237 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 238 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 239 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 240 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23 241 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 242 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 243 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 244 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 245 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 246 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 247 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 248 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 249 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 250 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 251 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 252 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 253 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 254 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 255 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 256 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 257 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 258 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22 259 260 struct i801_mux_config { 261 char *gpio_chip; 262 unsigned values[3]; 263 int n_values; 264 unsigned classes[3]; 265 unsigned gpios[2]; /* Relative to gpio_chip->base */ 266 int n_gpios; 267 }; 268 269 struct i801_priv { 270 struct i2c_adapter adapter; 271 unsigned long smba; 272 unsigned char original_hstcfg; 273 unsigned char original_hstcnt; 274 unsigned char original_slvcmd; 275 struct pci_dev *pci_dev; 276 unsigned int features; 277 278 /* isr processing */ 279 struct completion done; 280 u8 status; 281 282 /* Command state used by isr for byte-by-byte block transactions */ 283 u8 cmd; 284 bool is_read; 285 int count; 286 int len; 287 u8 *data; 288 289 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 290 struct platform_device *mux_pdev; 291 struct gpiod_lookup_table *lookup; 292 #endif 293 struct platform_device *tco_pdev; 294 295 /* 296 * If set to true the host controller registers are reserved for 297 * ACPI AML use. 298 */ 299 bool acpi_reserved; 300 }; 301 302 #define FEATURE_SMBUS_PEC BIT(0) 303 #define FEATURE_BLOCK_BUFFER BIT(1) 304 #define FEATURE_BLOCK_PROC BIT(2) 305 #define FEATURE_I2C_BLOCK_READ BIT(3) 306 #define FEATURE_IRQ BIT(4) 307 #define FEATURE_HOST_NOTIFY BIT(5) 308 /* Not really a feature, but it's convenient to handle it as such */ 309 #define FEATURE_IDF BIT(15) 310 #define FEATURE_TCO_SPT BIT(16) 311 #define FEATURE_TCO_CNL BIT(17) 312 313 static const char *i801_feature_names[] = { 314 "SMBus PEC", 315 "Block buffer", 316 "Block process call", 317 "I2C block read", 318 "Interrupt", 319 "SMBus Host Notify", 320 }; 321 322 static unsigned int disable_features; 323 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 324 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 325 "\t\t 0x01 disable SMBus PEC\n" 326 "\t\t 0x02 disable the block buffer\n" 327 "\t\t 0x08 disable the I2C block read functionality\n" 328 "\t\t 0x10 don't use interrupts\n" 329 "\t\t 0x20 disable SMBus Host Notify "); 330 331 /* Make sure the SMBus host is ready to start transmitting. 332 Return 0 if it is, -EBUSY if it is not. */ 333 static int i801_check_pre(struct i801_priv *priv) 334 { 335 int status; 336 337 status = inb_p(SMBHSTSTS(priv)); 338 if (status & SMBHSTSTS_HOST_BUSY) { 339 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 340 return -EBUSY; 341 } 342 343 status &= STATUS_FLAGS; 344 if (status) { 345 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 346 outb_p(status, SMBHSTSTS(priv)); 347 } 348 349 /* 350 * Clear CRC status if needed. 351 * During normal operation, i801_check_post() takes care 352 * of it after every operation. We do it here only in case 353 * the hardware was already in this state when the driver 354 * started. 355 */ 356 if (priv->features & FEATURE_SMBUS_PEC) { 357 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 358 if (status) { 359 pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status); 360 outb_p(status, SMBAUXSTS(priv)); 361 } 362 } 363 364 return 0; 365 } 366 367 static int i801_check_post(struct i801_priv *priv, int status) 368 { 369 int result = 0; 370 371 /* 372 * If the SMBus is still busy, we give up 373 */ 374 if (unlikely(status < 0)) { 375 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 376 /* try to stop the current command */ 377 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 378 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 379 usleep_range(1000, 2000); 380 outb_p(0, SMBHSTCNT(priv)); 381 382 /* Check if it worked */ 383 status = inb_p(SMBHSTSTS(priv)); 384 if ((status & SMBHSTSTS_HOST_BUSY) || 385 !(status & SMBHSTSTS_FAILED)) 386 dev_err(&priv->pci_dev->dev, 387 "Failed terminating the transaction\n"); 388 return -ETIMEDOUT; 389 } 390 391 if (status & SMBHSTSTS_FAILED) { 392 result = -EIO; 393 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 394 } 395 if (status & SMBHSTSTS_DEV_ERR) { 396 /* 397 * This may be a PEC error, check and clear it. 398 * 399 * AUXSTS is handled differently from HSTSTS. 400 * For HSTSTS, i801_isr() or i801_wait_intr() 401 * has already cleared the error bits in hardware, 402 * and we are passed a copy of the original value 403 * in "status". 404 * For AUXSTS, the hardware register is left 405 * for us to handle here. 406 * This is asymmetric, slightly iffy, but safe, 407 * since all this code is serialized and the CRCE 408 * bit is harmless as long as it's cleared before 409 * the next operation. 410 */ 411 if ((priv->features & FEATURE_SMBUS_PEC) && 412 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 413 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 414 result = -EBADMSG; 415 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 416 } else { 417 result = -ENXIO; 418 dev_dbg(&priv->pci_dev->dev, "No response\n"); 419 } 420 } 421 if (status & SMBHSTSTS_BUS_ERR) { 422 result = -EAGAIN; 423 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 424 } 425 426 return result; 427 } 428 429 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 430 static int i801_wait_intr(struct i801_priv *priv) 431 { 432 unsigned long timeout = jiffies + priv->adapter.timeout; 433 int status, busy; 434 435 do { 436 usleep_range(250, 500); 437 status = inb_p(SMBHSTSTS(priv)); 438 busy = status & SMBHSTSTS_HOST_BUSY; 439 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 440 if (!busy && status) 441 return status & STATUS_ERROR_FLAGS; 442 } while (time_is_after_eq_jiffies(timeout)); 443 444 return -ETIMEDOUT; 445 } 446 447 /* Wait for either BYTE_DONE or an error flag being set */ 448 static int i801_wait_byte_done(struct i801_priv *priv) 449 { 450 unsigned long timeout = jiffies + priv->adapter.timeout; 451 int status; 452 453 do { 454 usleep_range(250, 500); 455 status = inb_p(SMBHSTSTS(priv)); 456 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 457 return status & STATUS_ERROR_FLAGS; 458 } while (time_is_after_eq_jiffies(timeout)); 459 460 return -ETIMEDOUT; 461 } 462 463 static int i801_transaction(struct i801_priv *priv, int xact) 464 { 465 unsigned long result; 466 const struct i2c_adapter *adap = &priv->adapter; 467 468 if (priv->features & FEATURE_IRQ) { 469 reinit_completion(&priv->done); 470 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 471 SMBHSTCNT(priv)); 472 result = wait_for_completion_timeout(&priv->done, adap->timeout); 473 return result ? priv->status : -ETIMEDOUT; 474 } 475 476 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 477 478 return i801_wait_intr(priv); 479 } 480 481 static int i801_block_transaction_by_block(struct i801_priv *priv, 482 union i2c_smbus_data *data, 483 char read_write, int command) 484 { 485 int i, len, status, xact; 486 487 switch (command) { 488 case I2C_SMBUS_BLOCK_PROC_CALL: 489 xact = I801_BLOCK_PROC_CALL; 490 break; 491 case I2C_SMBUS_BLOCK_DATA: 492 xact = I801_BLOCK_DATA; 493 break; 494 default: 495 return -EOPNOTSUPP; 496 } 497 498 /* Set block buffer mode */ 499 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 500 501 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 502 503 if (read_write == I2C_SMBUS_WRITE) { 504 len = data->block[0]; 505 outb_p(len, SMBHSTDAT0(priv)); 506 for (i = 0; i < len; i++) 507 outb_p(data->block[i+1], SMBBLKDAT(priv)); 508 } 509 510 status = i801_transaction(priv, xact); 511 if (status) 512 goto out; 513 514 if (read_write == I2C_SMBUS_READ || 515 command == I2C_SMBUS_BLOCK_PROC_CALL) { 516 len = inb_p(SMBHSTDAT0(priv)); 517 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 518 status = -EPROTO; 519 goto out; 520 } 521 522 data->block[0] = len; 523 for (i = 0; i < len; i++) 524 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 525 } 526 out: 527 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 528 return status; 529 } 530 531 static void i801_isr_byte_done(struct i801_priv *priv) 532 { 533 if (priv->is_read) { 534 /* For SMBus block reads, length is received with first byte */ 535 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 536 (priv->count == 0)) { 537 priv->len = inb_p(SMBHSTDAT0(priv)); 538 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 539 dev_err(&priv->pci_dev->dev, 540 "Illegal SMBus block read size %d\n", 541 priv->len); 542 /* FIXME: Recover */ 543 priv->len = I2C_SMBUS_BLOCK_MAX; 544 } 545 priv->data[-1] = priv->len; 546 } 547 548 /* Read next byte */ 549 if (priv->count < priv->len) 550 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 551 else 552 dev_dbg(&priv->pci_dev->dev, 553 "Discarding extra byte on block read\n"); 554 555 /* Set LAST_BYTE for last byte of read transaction */ 556 if (priv->count == priv->len - 1) 557 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 558 SMBHSTCNT(priv)); 559 } else if (priv->count < priv->len - 1) { 560 /* Write next byte, except for IRQ after last byte */ 561 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 562 } 563 } 564 565 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 566 { 567 unsigned short addr; 568 569 addr = inb_p(SMBNTFDADD(priv)) >> 1; 570 571 /* 572 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 573 * always returns 0. Our current implementation doesn't provide 574 * data, so we just ignore it. 575 */ 576 i2c_handle_smbus_host_notify(&priv->adapter, addr); 577 578 /* clear Host Notify bit and return */ 579 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 580 return IRQ_HANDLED; 581 } 582 583 /* 584 * There are three kinds of interrupts: 585 * 586 * 1) i801 signals transaction completion with one of these interrupts: 587 * INTR - Success 588 * DEV_ERR - Invalid command, NAK or communication timeout 589 * BUS_ERR - SMI# transaction collision 590 * FAILED - transaction was canceled due to a KILL request 591 * When any of these occur, update ->status and signal completion. 592 * 593 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 594 * occurs for each byte of a byte-by-byte to prepare the next byte. 595 * 596 * 3) Host Notify interrupts 597 */ 598 static irqreturn_t i801_isr(int irq, void *dev_id) 599 { 600 struct i801_priv *priv = dev_id; 601 u16 pcists; 602 u8 status; 603 604 /* Confirm this is our interrupt */ 605 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 606 if (!(pcists & PCI_STATUS_INTERRUPT)) 607 return IRQ_NONE; 608 609 if (priv->features & FEATURE_HOST_NOTIFY) { 610 status = inb_p(SMBSLVSTS(priv)); 611 if (status & SMBSLVSTS_HST_NTFY_STS) 612 return i801_host_notify_isr(priv); 613 } 614 615 status = inb_p(SMBHSTSTS(priv)); 616 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 617 i801_isr_byte_done(priv); 618 619 /* 620 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 621 * independently of the interrupt generation being blocked or not 622 * so clear it always when the status is set. 623 */ 624 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 625 outb_p(status, SMBHSTSTS(priv)); 626 627 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 628 if (status) { 629 priv->status = status & STATUS_ERROR_FLAGS; 630 complete(&priv->done); 631 } 632 633 return IRQ_HANDLED; 634 } 635 636 /* 637 * For "byte-by-byte" block transactions: 638 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 639 * I2C read uses cmd=I801_I2C_BLOCK_DATA 640 */ 641 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 642 union i2c_smbus_data *data, 643 char read_write, int command) 644 { 645 int i, len; 646 int smbcmd; 647 int status; 648 unsigned long result; 649 const struct i2c_adapter *adap = &priv->adapter; 650 651 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 652 return -EOPNOTSUPP; 653 654 len = data->block[0]; 655 656 if (read_write == I2C_SMBUS_WRITE) { 657 outb_p(len, SMBHSTDAT0(priv)); 658 outb_p(data->block[1], SMBBLKDAT(priv)); 659 } 660 661 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 662 read_write == I2C_SMBUS_READ) 663 smbcmd = I801_I2C_BLOCK_DATA; 664 else 665 smbcmd = I801_BLOCK_DATA; 666 667 if (priv->features & FEATURE_IRQ) { 668 priv->is_read = (read_write == I2C_SMBUS_READ); 669 if (len == 1 && priv->is_read) 670 smbcmd |= SMBHSTCNT_LAST_BYTE; 671 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 672 priv->len = len; 673 priv->count = 0; 674 priv->data = &data->block[1]; 675 676 reinit_completion(&priv->done); 677 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 678 result = wait_for_completion_timeout(&priv->done, adap->timeout); 679 return result ? priv->status : -ETIMEDOUT; 680 } 681 682 if (len == 1 && read_write == I2C_SMBUS_READ) 683 smbcmd |= SMBHSTCNT_LAST_BYTE; 684 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 685 686 for (i = 1; i <= len; i++) { 687 status = i801_wait_byte_done(priv); 688 if (status) 689 return status; 690 691 if (i == 1 && read_write == I2C_SMBUS_READ 692 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 693 len = inb_p(SMBHSTDAT0(priv)); 694 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 695 dev_err(&priv->pci_dev->dev, 696 "Illegal SMBus block read size %d\n", 697 len); 698 /* Recover */ 699 while (inb_p(SMBHSTSTS(priv)) & 700 SMBHSTSTS_HOST_BUSY) 701 outb_p(SMBHSTSTS_BYTE_DONE, 702 SMBHSTSTS(priv)); 703 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 704 return -EPROTO; 705 } 706 data->block[0] = len; 707 } 708 709 if (read_write == I2C_SMBUS_READ) { 710 data->block[i] = inb_p(SMBBLKDAT(priv)); 711 if (i == len - 1) 712 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 713 } 714 715 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 716 outb_p(data->block[i+1], SMBBLKDAT(priv)); 717 718 /* signals SMBBLKDAT ready */ 719 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 720 } 721 722 return i801_wait_intr(priv); 723 } 724 725 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 726 { 727 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 728 } 729 730 /* Single value transaction function */ 731 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 732 u8 addr, u8 hstcmd, char read_write, int command) 733 { 734 int xact, ret; 735 736 switch (command) { 737 case I2C_SMBUS_QUICK: 738 i801_set_hstadd(priv, addr, read_write); 739 xact = I801_QUICK; 740 break; 741 case I2C_SMBUS_BYTE: 742 i801_set_hstadd(priv, addr, read_write); 743 if (read_write == I2C_SMBUS_WRITE) 744 outb_p(hstcmd, SMBHSTCMD(priv)); 745 xact = I801_BYTE; 746 break; 747 case I2C_SMBUS_BYTE_DATA: 748 i801_set_hstadd(priv, addr, read_write); 749 if (read_write == I2C_SMBUS_WRITE) 750 outb_p(data->byte, SMBHSTDAT0(priv)); 751 outb_p(hstcmd, SMBHSTCMD(priv)); 752 xact = I801_BYTE_DATA; 753 break; 754 case I2C_SMBUS_WORD_DATA: 755 i801_set_hstadd(priv, addr, read_write); 756 if (read_write == I2C_SMBUS_WRITE) { 757 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 758 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 759 } 760 outb_p(hstcmd, SMBHSTCMD(priv)); 761 xact = I801_WORD_DATA; 762 break; 763 case I2C_SMBUS_PROC_CALL: 764 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 765 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 766 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 767 outb_p(hstcmd, SMBHSTCMD(priv)); 768 read_write = I2C_SMBUS_READ; 769 xact = I801_PROC_CALL; 770 break; 771 default: 772 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 773 return -EOPNOTSUPP; 774 } 775 776 ret = i801_transaction(priv, xact); 777 if (ret || read_write == I2C_SMBUS_WRITE) 778 return ret; 779 780 switch (command) { 781 case I2C_SMBUS_BYTE: 782 case I2C_SMBUS_BYTE_DATA: 783 data->byte = inb_p(SMBHSTDAT0(priv)); 784 break; 785 case I2C_SMBUS_WORD_DATA: 786 case I2C_SMBUS_PROC_CALL: 787 data->word = inb_p(SMBHSTDAT0(priv)) + 788 (inb_p(SMBHSTDAT1(priv)) << 8); 789 break; 790 } 791 792 return 0; 793 } 794 795 /* Block transaction function */ 796 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 797 u8 addr, u8 hstcmd, char read_write, int command) 798 { 799 int result = 0; 800 unsigned char hostc; 801 802 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 803 data->block[0] = I2C_SMBUS_BLOCK_MAX; 804 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 805 return -EPROTO; 806 807 switch (command) { 808 case I2C_SMBUS_BLOCK_DATA: 809 i801_set_hstadd(priv, addr, read_write); 810 outb_p(hstcmd, SMBHSTCMD(priv)); 811 break; 812 case I2C_SMBUS_I2C_BLOCK_DATA: 813 /* 814 * NB: page 240 of ICH5 datasheet shows that the R/#W 815 * bit should be cleared here, even when reading. 816 * However if SPD Write Disable is set (Lynx Point and later), 817 * the read will fail if we don't set the R/#W bit. 818 */ 819 i801_set_hstadd(priv, addr, 820 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? 821 read_write : I2C_SMBUS_WRITE); 822 if (read_write == I2C_SMBUS_READ) { 823 /* NB: page 240 of ICH5 datasheet also shows 824 * that DATA1 is the cmd field when reading 825 */ 826 outb_p(hstcmd, SMBHSTDAT1(priv)); 827 } else 828 outb_p(hstcmd, SMBHSTCMD(priv)); 829 830 if (read_write == I2C_SMBUS_WRITE) { 831 /* set I2C_EN bit in configuration register */ 832 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 833 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 834 hostc | SMBHSTCFG_I2C_EN); 835 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 836 dev_err(&priv->pci_dev->dev, 837 "I2C block read is unsupported!\n"); 838 return -EOPNOTSUPP; 839 } 840 break; 841 case I2C_SMBUS_BLOCK_PROC_CALL: 842 /* Needs to be flagged as write transaction */ 843 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 844 outb_p(hstcmd, SMBHSTCMD(priv)); 845 break; 846 } 847 848 /* Experience has shown that the block buffer can only be used for 849 SMBus (not I2C) block transactions, even though the datasheet 850 doesn't mention this limitation. */ 851 if ((priv->features & FEATURE_BLOCK_BUFFER) && 852 command != I2C_SMBUS_I2C_BLOCK_DATA) 853 result = i801_block_transaction_by_block(priv, data, 854 read_write, 855 command); 856 else 857 result = i801_block_transaction_byte_by_byte(priv, data, 858 read_write, 859 command); 860 861 if (command == I2C_SMBUS_I2C_BLOCK_DATA 862 && read_write == I2C_SMBUS_WRITE) { 863 /* restore saved configuration register value */ 864 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 865 } 866 return result; 867 } 868 869 /* Return negative errno on error. */ 870 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 871 unsigned short flags, char read_write, u8 command, 872 int size, union i2c_smbus_data *data) 873 { 874 int hwpec, ret; 875 struct i801_priv *priv = i2c_get_adapdata(adap); 876 877 if (priv->acpi_reserved) 878 return -EBUSY; 879 880 pm_runtime_get_sync(&priv->pci_dev->dev); 881 882 ret = i801_check_pre(priv); 883 if (ret) 884 goto out; 885 886 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 887 && size != I2C_SMBUS_QUICK 888 && size != I2C_SMBUS_I2C_BLOCK_DATA; 889 890 if (hwpec) /* enable/disable hardware PEC */ 891 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 892 else 893 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 894 SMBAUXCTL(priv)); 895 896 if (size == I2C_SMBUS_BLOCK_DATA || 897 size == I2C_SMBUS_I2C_BLOCK_DATA || 898 size == I2C_SMBUS_BLOCK_PROC_CALL) 899 ret = i801_block_transaction(priv, data, addr, command, read_write, size); 900 else 901 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 902 903 ret = i801_check_post(priv, ret); 904 905 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 906 * time, so we forcibly disable it after every transaction. 907 */ 908 if (hwpec) 909 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 910 out: 911 /* 912 * Unlock the SMBus device for use by BIOS/ACPI, 913 * and clear status flags if not done already. 914 */ 915 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 916 917 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 918 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 919 return ret; 920 } 921 922 923 static u32 i801_func(struct i2c_adapter *adapter) 924 { 925 struct i801_priv *priv = i2c_get_adapdata(adapter); 926 927 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 928 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 929 I2C_FUNC_SMBUS_PROC_CALL | 930 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 931 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 932 ((priv->features & FEATURE_BLOCK_PROC) ? 933 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 934 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 935 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 936 ((priv->features & FEATURE_HOST_NOTIFY) ? 937 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 938 } 939 940 static void i801_enable_host_notify(struct i2c_adapter *adapter) 941 { 942 struct i801_priv *priv = i2c_get_adapdata(adapter); 943 944 if (!(priv->features & FEATURE_HOST_NOTIFY)) 945 return; 946 947 /* 948 * Enable host notify interrupt and block the generation of interrupt 949 * from the SMB_ALERT signal because the driver does not support 950 * SMBus Alert. 951 */ 952 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 953 priv->original_slvcmd, SMBSLVCMD(priv)); 954 955 /* clear Host Notify bit to allow a new notification */ 956 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 957 } 958 959 static void i801_disable_host_notify(struct i801_priv *priv) 960 { 961 if (!(priv->features & FEATURE_HOST_NOTIFY)) 962 return; 963 964 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 965 } 966 967 static const struct i2c_algorithm smbus_algorithm = { 968 .smbus_xfer = i801_access, 969 .functionality = i801_func, 970 }; 971 972 #define FEATURES_ICH5 (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ | \ 973 FEATURE_IRQ | FEATURE_SMBUS_PEC | \ 974 FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY) 975 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 976 FEATURE_HOST_NOTIFY) 977 978 static const struct pci_device_id i801_ids[] = { 979 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 980 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 981 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 982 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 983 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 984 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 985 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 986 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 987 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 988 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 989 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 990 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 991 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 992 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 993 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 994 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 995 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 996 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 997 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 998 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 999 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1000 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1007 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1008 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1009 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1011 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1012 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1013 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1014 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1015 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1016 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1017 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1018 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1019 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1020 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1021 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1022 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1023 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1024 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1025 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1026 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1027 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1028 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1029 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1030 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1031 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1032 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1034 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1035 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1036 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1037 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1038 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1039 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { 0, } 1044 }; 1045 1046 MODULE_DEVICE_TABLE(pci, i801_ids); 1047 1048 #if defined CONFIG_X86 && defined CONFIG_DMI 1049 static unsigned char apanel_addr; 1050 1051 /* Scan the system ROM for the signature "FJKEYINF" */ 1052 static __init const void __iomem *bios_signature(const void __iomem *bios) 1053 { 1054 ssize_t offset; 1055 const unsigned char signature[] = "FJKEYINF"; 1056 1057 for (offset = 0; offset < 0x10000; offset += 0x10) { 1058 if (check_signature(bios + offset, signature, 1059 sizeof(signature)-1)) 1060 return bios + offset; 1061 } 1062 return NULL; 1063 } 1064 1065 static void __init input_apanel_init(void) 1066 { 1067 void __iomem *bios; 1068 const void __iomem *p; 1069 1070 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1071 p = bios_signature(bios); 1072 if (p) { 1073 /* just use the first address */ 1074 apanel_addr = readb(p + 8 + 3) >> 1; 1075 } 1076 iounmap(bios); 1077 } 1078 1079 struct dmi_onboard_device_info { 1080 const char *name; 1081 u8 type; 1082 unsigned short i2c_addr; 1083 const char *i2c_type; 1084 }; 1085 1086 static const struct dmi_onboard_device_info dmi_devices[] = { 1087 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1088 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1089 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1090 }; 1091 1092 static void dmi_check_onboard_device(u8 type, const char *name, 1093 struct i2c_adapter *adap) 1094 { 1095 int i; 1096 struct i2c_board_info info; 1097 1098 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1099 /* & ~0x80, ignore enabled/disabled bit */ 1100 if ((type & ~0x80) != dmi_devices[i].type) 1101 continue; 1102 if (strcasecmp(name, dmi_devices[i].name)) 1103 continue; 1104 1105 memset(&info, 0, sizeof(struct i2c_board_info)); 1106 info.addr = dmi_devices[i].i2c_addr; 1107 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1108 i2c_new_client_device(adap, &info); 1109 break; 1110 } 1111 } 1112 1113 /* We use our own function to check for onboard devices instead of 1114 dmi_find_device() as some buggy BIOS's have the devices we are interested 1115 in marked as disabled */ 1116 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1117 { 1118 int i, count; 1119 1120 if (dm->type != 10) 1121 return; 1122 1123 count = (dm->length - sizeof(struct dmi_header)) / 2; 1124 for (i = 0; i < count; i++) { 1125 const u8 *d = (char *)(dm + 1) + (i * 2); 1126 const char *name = ((char *) dm) + dm->length; 1127 u8 type = d[0]; 1128 u8 s = d[1]; 1129 1130 if (!s) 1131 continue; 1132 s--; 1133 while (s > 0 && name[0]) { 1134 name += strlen(name) + 1; 1135 s--; 1136 } 1137 if (name[0] == 0) /* Bogus string reference */ 1138 continue; 1139 1140 dmi_check_onboard_device(type, name, adap); 1141 } 1142 } 1143 1144 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1145 static const char *const acpi_smo8800_ids[] = { 1146 "SMO8800", 1147 "SMO8801", 1148 "SMO8810", 1149 "SMO8811", 1150 "SMO8820", 1151 "SMO8821", 1152 "SMO8830", 1153 "SMO8831", 1154 }; 1155 1156 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1157 u32 nesting_level, 1158 void *context, 1159 void **return_value) 1160 { 1161 struct acpi_device_info *info; 1162 acpi_status status; 1163 char *hid; 1164 int i; 1165 1166 status = acpi_get_object_info(obj_handle, &info); 1167 if (ACPI_FAILURE(status)) 1168 return AE_OK; 1169 1170 if (!(info->valid & ACPI_VALID_HID)) 1171 goto smo88xx_not_found; 1172 1173 hid = info->hardware_id.string; 1174 if (!hid) 1175 goto smo88xx_not_found; 1176 1177 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1178 if (i < 0) 1179 goto smo88xx_not_found; 1180 1181 kfree(info); 1182 1183 *return_value = NULL; 1184 return AE_CTRL_TERMINATE; 1185 1186 smo88xx_not_found: 1187 kfree(info); 1188 return AE_OK; 1189 } 1190 1191 static bool is_dell_system_with_lis3lv02d(void) 1192 { 1193 void *err = ERR_PTR(-ENOENT); 1194 1195 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1196 return false; 1197 1198 /* 1199 * Check that ACPI device SMO88xx is present and is functioning. 1200 * Function acpi_get_devices() already filters all ACPI devices 1201 * which are not present or are not functioning. 1202 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1203 * accelerometer but unfortunately ACPI does not provide any other 1204 * information (like I2C address). 1205 */ 1206 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1207 1208 return !IS_ERR(err); 1209 } 1210 1211 /* 1212 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1213 * so it is needed to define mapping table based on DMI product names. 1214 */ 1215 static const struct { 1216 const char *dmi_product_name; 1217 unsigned short i2c_addr; 1218 } dell_lis3lv02d_devices[] = { 1219 /* 1220 * Dell platform team told us that these Latitude devices have 1221 * ST microelectronics accelerometer at I2C address 0x29. 1222 */ 1223 { "Latitude E5250", 0x29 }, 1224 { "Latitude E5450", 0x29 }, 1225 { "Latitude E5550", 0x29 }, 1226 { "Latitude E6440", 0x29 }, 1227 { "Latitude E6440 ATG", 0x29 }, 1228 { "Latitude E6540", 0x29 }, 1229 /* 1230 * Additional individual entries were added after verification. 1231 */ 1232 { "Latitude 5480", 0x29 }, 1233 { "Precision 3540", 0x29 }, 1234 { "Vostro V131", 0x1d }, 1235 { "Vostro 5568", 0x29 }, 1236 }; 1237 1238 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1239 { 1240 struct i2c_board_info info; 1241 const char *dmi_product_name; 1242 int i; 1243 1244 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1245 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1246 if (strcmp(dmi_product_name, 1247 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1248 break; 1249 } 1250 1251 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1252 dev_warn(&priv->pci_dev->dev, 1253 "Accelerometer lis3lv02d is present on SMBus but its" 1254 " address is unknown, skipping registration\n"); 1255 return; 1256 } 1257 1258 memset(&info, 0, sizeof(struct i2c_board_info)); 1259 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1260 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1261 i2c_new_client_device(&priv->adapter, &info); 1262 } 1263 1264 /* Register optional slaves */ 1265 static void i801_probe_optional_slaves(struct i801_priv *priv) 1266 { 1267 /* Only register slaves on main SMBus channel */ 1268 if (priv->features & FEATURE_IDF) 1269 return; 1270 1271 if (apanel_addr) { 1272 struct i2c_board_info info = { 1273 .addr = apanel_addr, 1274 .type = "fujitsu_apanel", 1275 }; 1276 1277 i2c_new_client_device(&priv->adapter, &info); 1278 } 1279 1280 if (dmi_name_in_vendors("FUJITSU")) 1281 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1282 1283 if (is_dell_system_with_lis3lv02d()) 1284 register_dell_lis3lv02d_i2c_device(priv); 1285 1286 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1287 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1288 if (!priv->mux_pdev) 1289 #endif 1290 i2c_register_spd(&priv->adapter); 1291 } 1292 #else 1293 static void __init input_apanel_init(void) {} 1294 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1295 #endif /* CONFIG_X86 && CONFIG_DMI */ 1296 1297 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1298 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1299 .gpio_chip = "gpio_ich", 1300 .values = { 0x02, 0x03 }, 1301 .n_values = 2, 1302 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1303 .gpios = { 52, 53 }, 1304 .n_gpios = 2, 1305 }; 1306 1307 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1308 .gpio_chip = "gpio_ich", 1309 .values = { 0x02, 0x03, 0x01 }, 1310 .n_values = 3, 1311 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1312 .gpios = { 52, 53 }, 1313 .n_gpios = 2, 1314 }; 1315 1316 static const struct dmi_system_id mux_dmi_table[] = { 1317 { 1318 .matches = { 1319 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1320 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1321 }, 1322 .driver_data = &i801_mux_config_asus_z8_d12, 1323 }, 1324 { 1325 .matches = { 1326 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1327 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1328 }, 1329 .driver_data = &i801_mux_config_asus_z8_d12, 1330 }, 1331 { 1332 .matches = { 1333 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1334 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1335 }, 1336 .driver_data = &i801_mux_config_asus_z8_d12, 1337 }, 1338 { 1339 .matches = { 1340 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1341 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1342 }, 1343 .driver_data = &i801_mux_config_asus_z8_d12, 1344 }, 1345 { 1346 .matches = { 1347 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1348 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1349 }, 1350 .driver_data = &i801_mux_config_asus_z8_d12, 1351 }, 1352 { 1353 .matches = { 1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1355 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1356 }, 1357 .driver_data = &i801_mux_config_asus_z8_d12, 1358 }, 1359 { 1360 .matches = { 1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1362 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1363 }, 1364 .driver_data = &i801_mux_config_asus_z8_d18, 1365 }, 1366 { 1367 .matches = { 1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1369 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1370 }, 1371 .driver_data = &i801_mux_config_asus_z8_d18, 1372 }, 1373 { 1374 .matches = { 1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1377 }, 1378 .driver_data = &i801_mux_config_asus_z8_d12, 1379 }, 1380 { } 1381 }; 1382 1383 /* Setup multiplexing if needed */ 1384 static void i801_add_mux(struct i801_priv *priv) 1385 { 1386 struct device *dev = &priv->adapter.dev; 1387 const struct i801_mux_config *mux_config; 1388 struct i2c_mux_gpio_platform_data gpio_data; 1389 struct gpiod_lookup_table *lookup; 1390 const struct dmi_system_id *id; 1391 int i; 1392 1393 id = dmi_first_match(mux_dmi_table); 1394 if (!id) 1395 return; 1396 1397 mux_config = id->driver_data; 1398 1399 /* Prepare the platform data */ 1400 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1401 gpio_data.parent = priv->adapter.nr; 1402 gpio_data.values = mux_config->values; 1403 gpio_data.n_values = mux_config->n_values; 1404 gpio_data.classes = mux_config->classes; 1405 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1406 1407 /* Register GPIO descriptor lookup table */ 1408 lookup = devm_kzalloc(dev, 1409 struct_size(lookup, table, mux_config->n_gpios + 1), 1410 GFP_KERNEL); 1411 if (!lookup) 1412 return; 1413 lookup->dev_id = "i2c-mux-gpio"; 1414 for (i = 0; i < mux_config->n_gpios; i++) 1415 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1416 mux_config->gpios[i], "mux", 0); 1417 gpiod_add_lookup_table(lookup); 1418 priv->lookup = lookup; 1419 1420 /* 1421 * Register the mux device, we use PLATFORM_DEVID_NONE here 1422 * because since we are referring to the GPIO chip by name we are 1423 * anyways in deep trouble if there is more than one of these 1424 * devices, and there should likely only be one platform controller 1425 * hub. 1426 */ 1427 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1428 PLATFORM_DEVID_NONE, &gpio_data, 1429 sizeof(struct i2c_mux_gpio_platform_data)); 1430 if (IS_ERR(priv->mux_pdev)) { 1431 gpiod_remove_lookup_table(lookup); 1432 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1433 } 1434 } 1435 1436 static void i801_del_mux(struct i801_priv *priv) 1437 { 1438 platform_device_unregister(priv->mux_pdev); 1439 gpiod_remove_lookup_table(priv->lookup); 1440 } 1441 #else 1442 static inline void i801_add_mux(struct i801_priv *priv) { } 1443 static inline void i801_del_mux(struct i801_priv *priv) { } 1444 #endif 1445 1446 static struct platform_device * 1447 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1448 struct resource *tco_res) 1449 { 1450 static const struct itco_wdt_platform_data pldata = { 1451 .name = "Intel PCH", 1452 .version = 4, 1453 }; 1454 struct resource *res; 1455 int ret; 1456 1457 /* 1458 * We must access the NO_REBOOT bit over the Primary to Sideband 1459 * (P2SB) bridge. 1460 */ 1461 1462 res = &tco_res[1]; 1463 ret = p2sb_bar(pci_dev->bus, 0, res); 1464 if (ret) 1465 return ERR_PTR(ret); 1466 1467 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1468 res->start += SBREG_SMBCTRL_DNV; 1469 else 1470 res->start += SBREG_SMBCTRL; 1471 1472 res->end = res->start + 3; 1473 1474 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1475 tco_res, 2, &pldata, sizeof(pldata)); 1476 } 1477 1478 static struct platform_device * 1479 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1480 struct resource *tco_res) 1481 { 1482 static const struct itco_wdt_platform_data pldata = { 1483 .name = "Intel PCH", 1484 .version = 6, 1485 }; 1486 1487 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1488 tco_res, 1, &pldata, sizeof(pldata)); 1489 } 1490 1491 static void i801_add_tco(struct i801_priv *priv) 1492 { 1493 struct pci_dev *pci_dev = priv->pci_dev; 1494 struct resource tco_res[2], *res; 1495 u32 tco_base, tco_ctl; 1496 1497 /* If we have ACPI based watchdog use that instead */ 1498 if (acpi_has_watchdog()) 1499 return; 1500 1501 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1502 return; 1503 1504 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1505 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1506 if (!(tco_ctl & TCOCTL_EN)) 1507 return; 1508 1509 memset(tco_res, 0, sizeof(tco_res)); 1510 /* 1511 * Always populate the main iTCO IO resource here. The second entry 1512 * for NO_REBOOT MMIO is filled by the SPT specific function. 1513 */ 1514 res = &tco_res[0]; 1515 res->start = tco_base & ~1; 1516 res->end = res->start + 32 - 1; 1517 res->flags = IORESOURCE_IO; 1518 1519 if (priv->features & FEATURE_TCO_CNL) 1520 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1521 else 1522 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1523 1524 if (IS_ERR(priv->tco_pdev)) 1525 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1526 } 1527 1528 #ifdef CONFIG_ACPI 1529 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1530 acpi_physical_address address) 1531 { 1532 return address >= priv->smba && 1533 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1534 } 1535 1536 static acpi_status 1537 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1538 u64 *value, void *handler_context, void *region_context) 1539 { 1540 struct i801_priv *priv = handler_context; 1541 struct pci_dev *pdev = priv->pci_dev; 1542 acpi_status status; 1543 1544 /* 1545 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1546 * further access from the driver itself. This device is now owned 1547 * by the system firmware. 1548 */ 1549 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1550 1551 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1552 priv->acpi_reserved = true; 1553 1554 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1555 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1556 1557 /* 1558 * BIOS is accessing the host controller so prevent it from 1559 * suspending automatically from now on. 1560 */ 1561 pm_runtime_get_sync(&pdev->dev); 1562 } 1563 1564 if ((function & ACPI_IO_MASK) == ACPI_READ) 1565 status = acpi_os_read_port(address, (u32 *)value, bits); 1566 else 1567 status = acpi_os_write_port(address, (u32)*value, bits); 1568 1569 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1570 1571 return status; 1572 } 1573 1574 static int i801_acpi_probe(struct i801_priv *priv) 1575 { 1576 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1577 acpi_status status; 1578 1579 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1580 i801_acpi_io_handler, NULL, priv); 1581 if (ACPI_SUCCESS(status)) 1582 return 0; 1583 1584 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1585 } 1586 1587 static void i801_acpi_remove(struct i801_priv *priv) 1588 { 1589 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1590 1591 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1592 } 1593 #else 1594 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1595 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1596 #endif 1597 1598 static void i801_setup_hstcfg(struct i801_priv *priv) 1599 { 1600 unsigned char hstcfg = priv->original_hstcfg; 1601 1602 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1603 hstcfg |= SMBHSTCFG_HST_EN; 1604 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1605 } 1606 1607 static void i801_restore_regs(struct i801_priv *priv) 1608 { 1609 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1610 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1611 } 1612 1613 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1614 { 1615 int err, i; 1616 struct i801_priv *priv; 1617 1618 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1619 if (!priv) 1620 return -ENOMEM; 1621 1622 i2c_set_adapdata(&priv->adapter, priv); 1623 priv->adapter.owner = THIS_MODULE; 1624 priv->adapter.class = I2C_CLASS_HWMON; 1625 priv->adapter.algo = &smbus_algorithm; 1626 priv->adapter.dev.parent = &dev->dev; 1627 acpi_use_parent_companion(&priv->adapter.dev); 1628 priv->adapter.retries = 3; 1629 1630 priv->pci_dev = dev; 1631 priv->features = id->driver_data; 1632 1633 /* Disable features on user request */ 1634 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1635 if (priv->features & disable_features & (1 << i)) 1636 dev_notice(&dev->dev, "%s disabled by user\n", 1637 i801_feature_names[i]); 1638 } 1639 priv->features &= ~disable_features; 1640 1641 /* The block process call uses block buffer mode */ 1642 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1643 priv->features &= ~FEATURE_BLOCK_PROC; 1644 1645 err = pcim_enable_device(dev); 1646 if (err) { 1647 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1648 err); 1649 return err; 1650 } 1651 pcim_pin_device(dev); 1652 1653 /* Determine the address of the SMBus area */ 1654 priv->smba = pci_resource_start(dev, SMBBAR); 1655 if (!priv->smba) { 1656 dev_err(&dev->dev, 1657 "SMBus base address uninitialized, upgrade BIOS\n"); 1658 return -ENODEV; 1659 } 1660 1661 if (i801_acpi_probe(priv)) 1662 return -ENODEV; 1663 1664 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1665 if (err) { 1666 dev_err(&dev->dev, 1667 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1668 priv->smba, 1669 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1670 i801_acpi_remove(priv); 1671 return err; 1672 } 1673 1674 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1675 i801_setup_hstcfg(priv); 1676 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1677 dev_info(&dev->dev, "Enabling SMBus device\n"); 1678 1679 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1680 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1681 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1682 priv->features &= ~FEATURE_IRQ; 1683 } 1684 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1685 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1686 1687 /* Clear special mode bits */ 1688 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1689 outb_p(inb_p(SMBAUXCTL(priv)) & 1690 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1691 1692 /* Default timeout in interrupt mode: 200 ms */ 1693 priv->adapter.timeout = HZ / 5; 1694 1695 if (dev->irq == IRQ_NOTCONNECTED) 1696 priv->features &= ~FEATURE_IRQ; 1697 1698 if (priv->features & FEATURE_IRQ) { 1699 u16 pcists; 1700 1701 /* Complain if an interrupt is already pending */ 1702 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1703 if (pcists & PCI_STATUS_INTERRUPT) 1704 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1705 } 1706 1707 if (priv->features & FEATURE_IRQ) { 1708 init_completion(&priv->done); 1709 1710 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1711 IRQF_SHARED, DRV_NAME, priv); 1712 if (err) { 1713 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1714 dev->irq, err); 1715 priv->features &= ~FEATURE_IRQ; 1716 } 1717 } 1718 dev_info(&dev->dev, "SMBus using %s\n", 1719 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1720 1721 /* Host notification uses an interrupt */ 1722 if (!(priv->features & FEATURE_IRQ)) 1723 priv->features &= ~FEATURE_HOST_NOTIFY; 1724 1725 /* Remember original Interrupt and Host Notify settings */ 1726 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1727 if (priv->features & FEATURE_HOST_NOTIFY) 1728 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1729 1730 i801_add_tco(priv); 1731 1732 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1733 "SMBus I801 adapter at %04lx", priv->smba); 1734 err = i2c_add_adapter(&priv->adapter); 1735 if (err) { 1736 platform_device_unregister(priv->tco_pdev); 1737 i801_acpi_remove(priv); 1738 i801_restore_regs(priv); 1739 return err; 1740 } 1741 1742 i801_enable_host_notify(&priv->adapter); 1743 1744 i801_probe_optional_slaves(priv); 1745 /* We ignore errors - multiplexing is optional */ 1746 i801_add_mux(priv); 1747 1748 pci_set_drvdata(dev, priv); 1749 1750 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1751 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1752 pm_runtime_use_autosuspend(&dev->dev); 1753 pm_runtime_put_autosuspend(&dev->dev); 1754 pm_runtime_allow(&dev->dev); 1755 1756 return 0; 1757 } 1758 1759 static void i801_remove(struct pci_dev *dev) 1760 { 1761 struct i801_priv *priv = pci_get_drvdata(dev); 1762 1763 i801_disable_host_notify(priv); 1764 i801_del_mux(priv); 1765 i2c_del_adapter(&priv->adapter); 1766 i801_acpi_remove(priv); 1767 1768 platform_device_unregister(priv->tco_pdev); 1769 1770 /* if acpi_reserved is set then usage_count is incremented already */ 1771 if (!priv->acpi_reserved) 1772 pm_runtime_get_noresume(&dev->dev); 1773 1774 i801_restore_regs(priv); 1775 1776 /* 1777 * do not call pci_disable_device(dev) since it can cause hard hangs on 1778 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1779 */ 1780 } 1781 1782 static void i801_shutdown(struct pci_dev *dev) 1783 { 1784 struct i801_priv *priv = pci_get_drvdata(dev); 1785 1786 i801_disable_host_notify(priv); 1787 /* Restore config registers to avoid hard hang on some systems */ 1788 i801_restore_regs(priv); 1789 } 1790 1791 static int i801_suspend(struct device *dev) 1792 { 1793 struct i801_priv *priv = dev_get_drvdata(dev); 1794 1795 i2c_mark_adapter_suspended(&priv->adapter); 1796 i801_restore_regs(priv); 1797 1798 return 0; 1799 } 1800 1801 static int i801_resume(struct device *dev) 1802 { 1803 struct i801_priv *priv = dev_get_drvdata(dev); 1804 1805 i801_setup_hstcfg(priv); 1806 i801_enable_host_notify(&priv->adapter); 1807 i2c_mark_adapter_resumed(&priv->adapter); 1808 1809 return 0; 1810 } 1811 1812 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1813 1814 static struct pci_driver i801_driver = { 1815 .name = DRV_NAME, 1816 .id_table = i801_ids, 1817 .probe = i801_probe, 1818 .remove = i801_remove, 1819 .shutdown = i801_shutdown, 1820 .driver = { 1821 .pm = pm_sleep_ptr(&i801_pm_ops), 1822 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1823 }, 1824 }; 1825 1826 static int __init i2c_i801_init(struct pci_driver *drv) 1827 { 1828 if (dmi_name_in_vendors("FUJITSU")) 1829 input_apanel_init(); 1830 return pci_register_driver(drv); 1831 } 1832 1833 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1834 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1835 MODULE_DESCRIPTION("I801 SMBus driver"); 1836 MODULE_LICENSE("GPL"); 1837 1838 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver); 1839