1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Ice Lake-N (PCH) 0x38a3 32 hard yes yes yes 68 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 69 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 70 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 71 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 72 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 73 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 74 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 75 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 76 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes 77 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes 78 * Raptor Lake-S (PCH) 0x7a23 32 hard yes yes yes 79 * Meteor Lake-P (SOC) 0x7e22 32 hard yes yes yes 80 * Meteor Lake SoC-S (SOC) 0xae22 32 hard yes yes yes 81 * Meteor Lake PCH-S (PCH) 0x7f23 32 hard yes yes yes 82 * Birch Stream (SOC) 0x5796 32 hard yes yes yes 83 * 84 * Features supported by this driver: 85 * Software PEC no 86 * Hardware PEC yes 87 * Block buffer yes 88 * Block process call transaction yes 89 * I2C block read transaction yes (doesn't use the block buffer) 90 * Slave mode no 91 * SMBus Host Notify yes 92 * Interrupt processing yes 93 * 94 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 95 */ 96 97 #define DRV_NAME "i801_smbus" 98 99 #include <linux/interrupt.h> 100 #include <linux/module.h> 101 #include <linux/pci.h> 102 #include <linux/kernel.h> 103 #include <linux/stddef.h> 104 #include <linux/delay.h> 105 #include <linux/ioport.h> 106 #include <linux/init.h> 107 #include <linux/i2c.h> 108 #include <linux/i2c-mux.h> 109 #include <linux/i2c-smbus.h> 110 #include <linux/acpi.h> 111 #include <linux/io.h> 112 #include <linux/dmi.h> 113 #include <linux/slab.h> 114 #include <linux/string.h> 115 #include <linux/completion.h> 116 #include <linux/err.h> 117 #include <linux/platform_device.h> 118 #include <linux/platform_data/itco_wdt.h> 119 #include <linux/platform_data/x86/p2sb.h> 120 #include <linux/pm_runtime.h> 121 #include <linux/mutex.h> 122 123 #ifdef CONFIG_I2C_I801_MUX 124 #include <linux/gpio/machine.h> 125 #include <linux/platform_data/i2c-mux-gpio.h> 126 #endif 127 128 /* I801 SMBus address offsets */ 129 #define SMBHSTSTS(p) (0 + (p)->smba) 130 #define SMBHSTCNT(p) (2 + (p)->smba) 131 #define SMBHSTCMD(p) (3 + (p)->smba) 132 #define SMBHSTADD(p) (4 + (p)->smba) 133 #define SMBHSTDAT0(p) (5 + (p)->smba) 134 #define SMBHSTDAT1(p) (6 + (p)->smba) 135 #define SMBBLKDAT(p) (7 + (p)->smba) 136 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 137 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 138 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 139 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 140 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 141 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 142 143 /* PCI Address Constants */ 144 #define SMBBAR 4 145 #define SMBHSTCFG 0x040 146 #define TCOBASE 0x050 147 #define TCOCTL 0x054 148 149 #define SBREG_SMBCTRL 0xc6000c 150 #define SBREG_SMBCTRL_DNV 0xcf000c 151 152 /* Host configuration bits for SMBHSTCFG */ 153 #define SMBHSTCFG_HST_EN BIT(0) 154 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 155 #define SMBHSTCFG_I2C_EN BIT(2) 156 #define SMBHSTCFG_SPD_WD BIT(4) 157 158 /* TCO configuration bits for TCOCTL */ 159 #define TCOCTL_EN BIT(8) 160 161 /* Auxiliary status register bits, ICH4+ only */ 162 #define SMBAUXSTS_CRCE BIT(0) 163 #define SMBAUXSTS_STCO BIT(1) 164 165 /* Auxiliary control register bits, ICH4+ only */ 166 #define SMBAUXCTL_CRC BIT(0) 167 #define SMBAUXCTL_E32B BIT(1) 168 169 /* I801 command constants */ 170 #define I801_QUICK 0x00 171 #define I801_BYTE 0x04 172 #define I801_BYTE_DATA 0x08 173 #define I801_WORD_DATA 0x0C 174 #define I801_PROC_CALL 0x10 175 #define I801_BLOCK_DATA 0x14 176 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 177 #define I801_BLOCK_PROC_CALL 0x1C 178 179 /* I801 Host Control register bits */ 180 #define SMBHSTCNT_INTREN BIT(0) 181 #define SMBHSTCNT_KILL BIT(1) 182 #define SMBHSTCNT_LAST_BYTE BIT(5) 183 #define SMBHSTCNT_START BIT(6) 184 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 185 186 /* I801 Hosts Status register bits */ 187 #define SMBHSTSTS_BYTE_DONE BIT(7) 188 #define SMBHSTSTS_INUSE_STS BIT(6) 189 #define SMBHSTSTS_SMBALERT_STS BIT(5) 190 #define SMBHSTSTS_FAILED BIT(4) 191 #define SMBHSTSTS_BUS_ERR BIT(3) 192 #define SMBHSTSTS_DEV_ERR BIT(2) 193 #define SMBHSTSTS_INTR BIT(1) 194 #define SMBHSTSTS_HOST_BUSY BIT(0) 195 196 /* Host Notify Status register bits */ 197 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 198 199 /* Host Notify Command register bits */ 200 #define SMBSLVCMD_SMBALERT_DISABLE BIT(2) 201 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 202 203 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 204 SMBHSTSTS_DEV_ERR) 205 206 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 207 STATUS_ERROR_FLAGS) 208 209 #define SMBUS_LEN_SENTINEL (I2C_SMBUS_BLOCK_MAX + 1) 210 211 /* Older devices have their ID defined in <linux/pci_ids.h> */ 212 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 213 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 214 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 215 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 216 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 217 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 218 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 220 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 221 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 222 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 223 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 224 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 225 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 226 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 227 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 228 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 229 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 230 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 231 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS 0x38a3 232 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 233 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 234 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 235 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 236 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3 237 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3 238 #define PCI_DEVICE_ID_INTEL_BIRCH_STREAM_SMBUS 0x5796 239 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 240 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS 0x7a23 241 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 242 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS 0x7e22 243 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_PCH_S_SMBUS 0x7f23 244 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 245 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 246 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 247 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 248 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 249 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 250 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 251 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 252 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 253 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 254 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 255 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 256 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 257 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 258 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 259 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 260 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 261 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_SOC_S_SMBUS 0xae22 262 263 struct i801_mux_config { 264 char *gpio_chip; 265 unsigned values[3]; 266 int n_values; 267 unsigned classes[3]; 268 unsigned gpios[2]; /* Relative to gpio_chip->base */ 269 int n_gpios; 270 }; 271 272 struct i801_priv { 273 struct i2c_adapter adapter; 274 unsigned long smba; 275 unsigned char original_hstcfg; 276 unsigned char original_hstcnt; 277 unsigned char original_slvcmd; 278 struct pci_dev *pci_dev; 279 unsigned int features; 280 281 /* isr processing */ 282 struct completion done; 283 u8 status; 284 285 /* Command state used by isr for byte-by-byte block transactions */ 286 u8 cmd; 287 bool is_read; 288 int count; 289 int len; 290 u8 *data; 291 292 #ifdef CONFIG_I2C_I801_MUX 293 struct platform_device *mux_pdev; 294 struct gpiod_lookup_table *lookup; 295 struct notifier_block mux_notifier_block; 296 #endif 297 struct platform_device *tco_pdev; 298 299 /* 300 * If set to true the host controller registers are reserved for 301 * ACPI AML use. 302 */ 303 bool acpi_reserved; 304 }; 305 306 #define FEATURE_SMBUS_PEC BIT(0) 307 #define FEATURE_BLOCK_BUFFER BIT(1) 308 #define FEATURE_BLOCK_PROC BIT(2) 309 #define FEATURE_I2C_BLOCK_READ BIT(3) 310 #define FEATURE_IRQ BIT(4) 311 #define FEATURE_HOST_NOTIFY BIT(5) 312 /* Not really a feature, but it's convenient to handle it as such */ 313 #define FEATURE_IDF BIT(15) 314 #define FEATURE_TCO_SPT BIT(16) 315 #define FEATURE_TCO_CNL BIT(17) 316 317 static const char *i801_feature_names[] = { 318 "SMBus PEC", 319 "Block buffer", 320 "Block process call", 321 "I2C block read", 322 "Interrupt", 323 "SMBus Host Notify", 324 }; 325 326 static unsigned int disable_features; 327 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 328 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 329 "\t\t 0x01 disable SMBus PEC\n" 330 "\t\t 0x02 disable the block buffer\n" 331 "\t\t 0x08 disable the I2C block read functionality\n" 332 "\t\t 0x10 don't use interrupts\n" 333 "\t\t 0x20 disable SMBus Host Notify "); 334 335 static int i801_get_block_len(struct i801_priv *priv) 336 { 337 u8 len = inb_p(SMBHSTDAT0(priv)); 338 339 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 340 pci_err(priv->pci_dev, "Illegal SMBus block read size %u\n", len); 341 return -EPROTO; 342 } 343 344 return len; 345 } 346 347 static int i801_check_and_clear_pec_error(struct i801_priv *priv) 348 { 349 u8 status; 350 351 if (!(priv->features & FEATURE_SMBUS_PEC)) 352 return 0; 353 354 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 355 if (status) { 356 outb_p(status, SMBAUXSTS(priv)); 357 return -EBADMSG; 358 } 359 360 return 0; 361 } 362 363 /* Make sure the SMBus host is ready to start transmitting. 364 Return 0 if it is, -EBUSY if it is not. */ 365 static int i801_check_pre(struct i801_priv *priv) 366 { 367 int status, result; 368 369 status = inb_p(SMBHSTSTS(priv)); 370 if (status & SMBHSTSTS_HOST_BUSY) { 371 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n"); 372 return -EBUSY; 373 } 374 375 status &= STATUS_FLAGS; 376 if (status) { 377 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status); 378 outb_p(status, SMBHSTSTS(priv)); 379 } 380 381 /* 382 * Clear CRC status if needed. 383 * During normal operation, i801_check_post() takes care 384 * of it after every operation. We do it here only in case 385 * the hardware was already in this state when the driver 386 * started. 387 */ 388 result = i801_check_and_clear_pec_error(priv); 389 if (result) 390 pci_dbg(priv->pci_dev, "Clearing aux status flag CRCE\n"); 391 392 return 0; 393 } 394 395 static int i801_check_post(struct i801_priv *priv, int status) 396 { 397 int result = 0; 398 399 /* 400 * If the SMBus is still busy, we give up 401 */ 402 if (unlikely(status < 0)) { 403 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 404 /* try to stop the current command */ 405 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 406 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 407 usleep_range(1000, 2000); 408 outb_p(0, SMBHSTCNT(priv)); 409 410 /* Check if it worked */ 411 status = inb_p(SMBHSTSTS(priv)); 412 if ((status & SMBHSTSTS_HOST_BUSY) || 413 !(status & SMBHSTSTS_FAILED)) 414 dev_err(&priv->pci_dev->dev, 415 "Failed terminating the transaction\n"); 416 return -ETIMEDOUT; 417 } 418 419 if (status & SMBHSTSTS_FAILED) { 420 result = -EIO; 421 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 422 } 423 if (status & SMBHSTSTS_DEV_ERR) { 424 /* 425 * This may be a PEC error, check and clear it. 426 * 427 * AUXSTS is handled differently from HSTSTS. 428 * For HSTSTS, i801_isr() or i801_wait_intr() 429 * has already cleared the error bits in hardware, 430 * and we are passed a copy of the original value 431 * in "status". 432 * For AUXSTS, the hardware register is left 433 * for us to handle here. 434 * This is asymmetric, slightly iffy, but safe, 435 * since all this code is serialized and the CRCE 436 * bit is harmless as long as it's cleared before 437 * the next operation. 438 */ 439 result = i801_check_and_clear_pec_error(priv); 440 if (result) { 441 pci_dbg(priv->pci_dev, "PEC error\n"); 442 } else { 443 result = -ENXIO; 444 pci_dbg(priv->pci_dev, "No response\n"); 445 } 446 } 447 if (status & SMBHSTSTS_BUS_ERR) { 448 result = -EAGAIN; 449 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 450 } 451 452 return result; 453 } 454 455 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 456 static int i801_wait_intr(struct i801_priv *priv) 457 { 458 unsigned long timeout = jiffies + priv->adapter.timeout; 459 int status, busy; 460 461 do { 462 usleep_range(250, 500); 463 status = inb_p(SMBHSTSTS(priv)); 464 busy = status & SMBHSTSTS_HOST_BUSY; 465 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 466 if (!busy && status) 467 return status & STATUS_ERROR_FLAGS; 468 } while (time_is_after_eq_jiffies(timeout)); 469 470 return -ETIMEDOUT; 471 } 472 473 /* Wait for either BYTE_DONE or an error flag being set */ 474 static int i801_wait_byte_done(struct i801_priv *priv) 475 { 476 unsigned long timeout = jiffies + priv->adapter.timeout; 477 int status; 478 479 do { 480 usleep_range(250, 500); 481 status = inb_p(SMBHSTSTS(priv)); 482 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) 483 return status & STATUS_ERROR_FLAGS; 484 } while (time_is_after_eq_jiffies(timeout)); 485 486 return -ETIMEDOUT; 487 } 488 489 static int i801_transaction(struct i801_priv *priv, int xact) 490 { 491 unsigned long result; 492 const struct i2c_adapter *adap = &priv->adapter; 493 494 if (priv->features & FEATURE_IRQ) { 495 reinit_completion(&priv->done); 496 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 497 SMBHSTCNT(priv)); 498 result = wait_for_completion_timeout(&priv->done, adap->timeout); 499 return result ? priv->status : -ETIMEDOUT; 500 } 501 502 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 503 504 return i801_wait_intr(priv); 505 } 506 507 static int i801_block_transaction_by_block(struct i801_priv *priv, 508 union i2c_smbus_data *data, 509 char read_write, int command) 510 { 511 int i, len, status, xact; 512 513 switch (command) { 514 case I2C_SMBUS_BLOCK_PROC_CALL: 515 xact = I801_BLOCK_PROC_CALL; 516 break; 517 case I2C_SMBUS_BLOCK_DATA: 518 xact = I801_BLOCK_DATA; 519 break; 520 default: 521 return -EOPNOTSUPP; 522 } 523 524 /* Set block buffer mode */ 525 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 526 527 if (read_write == I2C_SMBUS_WRITE) { 528 len = data->block[0]; 529 outb_p(len, SMBHSTDAT0(priv)); 530 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 531 for (i = 0; i < len; i++) 532 outb_p(data->block[i+1], SMBBLKDAT(priv)); 533 } 534 535 status = i801_transaction(priv, xact); 536 if (status) 537 goto out; 538 539 if (read_write == I2C_SMBUS_READ || 540 command == I2C_SMBUS_BLOCK_PROC_CALL) { 541 len = i801_get_block_len(priv); 542 if (len < 0) { 543 status = len; 544 goto out; 545 } 546 547 data->block[0] = len; 548 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 549 for (i = 0; i < len; i++) 550 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 551 } 552 out: 553 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv)); 554 return status; 555 } 556 557 static void i801_isr_byte_done(struct i801_priv *priv) 558 { 559 if (priv->is_read) { 560 /* 561 * At transfer start i801_smbus_block_transaction() marks 562 * the block length as invalid. Check for this sentinel value 563 * and read the block length from SMBHSTDAT0. 564 */ 565 if (priv->len == SMBUS_LEN_SENTINEL) { 566 priv->len = i801_get_block_len(priv); 567 if (priv->len < 0) 568 /* FIXME: Recover */ 569 priv->len = I2C_SMBUS_BLOCK_MAX; 570 571 priv->data[-1] = priv->len; 572 } 573 574 /* Read next byte */ 575 if (priv->count < priv->len) 576 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 577 else 578 dev_dbg(&priv->pci_dev->dev, 579 "Discarding extra byte on block read\n"); 580 581 /* Set LAST_BYTE for last byte of read transaction */ 582 if (priv->count == priv->len - 1) 583 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 584 SMBHSTCNT(priv)); 585 } else if (priv->count < priv->len - 1) { 586 /* Write next byte, except for IRQ after last byte */ 587 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 588 } 589 } 590 591 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 592 { 593 unsigned short addr; 594 595 addr = inb_p(SMBNTFDADD(priv)) >> 1; 596 597 /* 598 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 599 * always returns 0. Our current implementation doesn't provide 600 * data, so we just ignore it. 601 */ 602 i2c_handle_smbus_host_notify(&priv->adapter, addr); 603 604 /* clear Host Notify bit and return */ 605 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 606 return IRQ_HANDLED; 607 } 608 609 /* 610 * There are three kinds of interrupts: 611 * 612 * 1) i801 signals transaction completion with one of these interrupts: 613 * INTR - Success 614 * DEV_ERR - Invalid command, NAK or communication timeout 615 * BUS_ERR - SMI# transaction collision 616 * FAILED - transaction was canceled due to a KILL request 617 * When any of these occur, update ->status and signal completion. 618 * 619 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 620 * occurs for each byte of a byte-by-byte to prepare the next byte. 621 * 622 * 3) Host Notify interrupts 623 */ 624 static irqreturn_t i801_isr(int irq, void *dev_id) 625 { 626 struct i801_priv *priv = dev_id; 627 u16 pcists; 628 u8 status; 629 630 /* Confirm this is our interrupt */ 631 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 632 if (!(pcists & PCI_STATUS_INTERRUPT)) 633 return IRQ_NONE; 634 635 if (priv->features & FEATURE_HOST_NOTIFY) { 636 status = inb_p(SMBSLVSTS(priv)); 637 if (status & SMBSLVSTS_HST_NTFY_STS) 638 return i801_host_notify_isr(priv); 639 } 640 641 status = inb_p(SMBHSTSTS(priv)); 642 if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE) 643 i801_isr_byte_done(priv); 644 645 /* 646 * Clear IRQ sources: SMB_ALERT status is set after signal assertion 647 * independently of the interrupt generation being blocked or not 648 * so clear it always when the status is set. 649 */ 650 status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS; 651 outb_p(status, SMBHSTSTS(priv)); 652 653 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR; 654 if (status) { 655 priv->status = status & STATUS_ERROR_FLAGS; 656 complete(&priv->done); 657 } 658 659 return IRQ_HANDLED; 660 } 661 662 /* 663 * For "byte-by-byte" block transactions: 664 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 665 * I2C read uses cmd=I801_I2C_BLOCK_DATA 666 */ 667 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 668 union i2c_smbus_data *data, 669 char read_write, int command) 670 { 671 int i, len; 672 int smbcmd; 673 int status; 674 unsigned long result; 675 const struct i2c_adapter *adap = &priv->adapter; 676 677 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 678 return -EOPNOTSUPP; 679 680 len = data->block[0]; 681 682 if (read_write == I2C_SMBUS_WRITE) { 683 outb_p(len, SMBHSTDAT0(priv)); 684 outb_p(data->block[1], SMBBLKDAT(priv)); 685 } 686 687 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 688 read_write == I2C_SMBUS_READ) 689 smbcmd = I801_I2C_BLOCK_DATA; 690 else 691 smbcmd = I801_BLOCK_DATA; 692 693 if (priv->features & FEATURE_IRQ) { 694 priv->is_read = (read_write == I2C_SMBUS_READ); 695 if (len == 1 && priv->is_read) 696 smbcmd |= SMBHSTCNT_LAST_BYTE; 697 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 698 priv->len = len; 699 priv->count = 0; 700 priv->data = &data->block[1]; 701 702 reinit_completion(&priv->done); 703 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 704 result = wait_for_completion_timeout(&priv->done, adap->timeout); 705 return result ? priv->status : -ETIMEDOUT; 706 } 707 708 if (len == 1 && read_write == I2C_SMBUS_READ) 709 smbcmd |= SMBHSTCNT_LAST_BYTE; 710 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 711 712 for (i = 1; i <= len; i++) { 713 status = i801_wait_byte_done(priv); 714 if (status) 715 return status; 716 717 /* 718 * At transfer start i801_smbus_block_transaction() marks 719 * the block length as invalid. Check for this sentinel value 720 * and read the block length from SMBHSTDAT0. 721 */ 722 if (len == SMBUS_LEN_SENTINEL) { 723 len = i801_get_block_len(priv); 724 if (len < 0) { 725 /* Recover */ 726 while (inb_p(SMBHSTSTS(priv)) & 727 SMBHSTSTS_HOST_BUSY) 728 outb_p(SMBHSTSTS_BYTE_DONE, 729 SMBHSTSTS(priv)); 730 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 731 return -EPROTO; 732 } 733 data->block[0] = len; 734 } 735 736 if (read_write == I2C_SMBUS_READ) { 737 data->block[i] = inb_p(SMBBLKDAT(priv)); 738 if (i == len - 1) 739 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 740 } 741 742 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 743 outb_p(data->block[i+1], SMBBLKDAT(priv)); 744 745 /* signals SMBBLKDAT ready */ 746 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 747 } 748 749 return i801_wait_intr(priv); 750 } 751 752 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 753 { 754 outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 755 } 756 757 /* Single value transaction function */ 758 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 759 u8 addr, u8 hstcmd, char read_write, int command) 760 { 761 int xact, ret; 762 763 switch (command) { 764 case I2C_SMBUS_QUICK: 765 i801_set_hstadd(priv, addr, read_write); 766 xact = I801_QUICK; 767 break; 768 case I2C_SMBUS_BYTE: 769 i801_set_hstadd(priv, addr, read_write); 770 if (read_write == I2C_SMBUS_WRITE) 771 outb_p(hstcmd, SMBHSTCMD(priv)); 772 xact = I801_BYTE; 773 break; 774 case I2C_SMBUS_BYTE_DATA: 775 i801_set_hstadd(priv, addr, read_write); 776 if (read_write == I2C_SMBUS_WRITE) 777 outb_p(data->byte, SMBHSTDAT0(priv)); 778 outb_p(hstcmd, SMBHSTCMD(priv)); 779 xact = I801_BYTE_DATA; 780 break; 781 case I2C_SMBUS_WORD_DATA: 782 i801_set_hstadd(priv, addr, read_write); 783 if (read_write == I2C_SMBUS_WRITE) { 784 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 785 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 786 } 787 outb_p(hstcmd, SMBHSTCMD(priv)); 788 xact = I801_WORD_DATA; 789 break; 790 case I2C_SMBUS_PROC_CALL: 791 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 792 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 793 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 794 outb_p(hstcmd, SMBHSTCMD(priv)); 795 read_write = I2C_SMBUS_READ; 796 xact = I801_PROC_CALL; 797 break; 798 default: 799 pci_err(priv->pci_dev, "Unsupported transaction %d\n", command); 800 return -EOPNOTSUPP; 801 } 802 803 ret = i801_transaction(priv, xact); 804 if (ret || read_write == I2C_SMBUS_WRITE) 805 return ret; 806 807 switch (command) { 808 case I2C_SMBUS_BYTE: 809 case I2C_SMBUS_BYTE_DATA: 810 data->byte = inb_p(SMBHSTDAT0(priv)); 811 break; 812 case I2C_SMBUS_WORD_DATA: 813 case I2C_SMBUS_PROC_CALL: 814 data->word = inb_p(SMBHSTDAT0(priv)) + 815 (inb_p(SMBHSTDAT1(priv)) << 8); 816 break; 817 } 818 819 return 0; 820 } 821 822 static int i801_smbus_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 823 u8 addr, u8 hstcmd, char read_write, int command) 824 { 825 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 826 /* Mark block length as invalid */ 827 data->block[0] = SMBUS_LEN_SENTINEL; 828 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 829 return -EPROTO; 830 831 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 832 /* Needs to be flagged as write transaction */ 833 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 834 else 835 i801_set_hstadd(priv, addr, read_write); 836 outb_p(hstcmd, SMBHSTCMD(priv)); 837 838 if (priv->features & FEATURE_BLOCK_BUFFER) 839 return i801_block_transaction_by_block(priv, data, read_write, command); 840 else 841 return i801_block_transaction_byte_by_byte(priv, data, read_write, command); 842 } 843 844 static int i801_i2c_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 845 u8 addr, u8 hstcmd, char read_write, int command) 846 { 847 int result; 848 u8 hostc; 849 850 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 851 return -EPROTO; 852 /* 853 * NB: page 240 of ICH5 datasheet shows that the R/#W bit should be cleared here, 854 * even when reading. However if SPD Write Disable is set (Lynx Point and later), 855 * the read will fail if we don't set the R/#W bit. 856 */ 857 i801_set_hstadd(priv, addr, 858 priv->original_hstcfg & SMBHSTCFG_SPD_WD ? read_write : I2C_SMBUS_WRITE); 859 860 /* NB: page 240 of ICH5 datasheet shows that DATA1 is the cmd field when reading */ 861 if (read_write == I2C_SMBUS_READ) 862 outb_p(hstcmd, SMBHSTDAT1(priv)); 863 else 864 outb_p(hstcmd, SMBHSTCMD(priv)); 865 866 if (read_write == I2C_SMBUS_WRITE) { 867 /* set I2C_EN bit in configuration register */ 868 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 869 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc | SMBHSTCFG_I2C_EN); 870 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 871 pci_err(priv->pci_dev, "I2C block read is unsupported!\n"); 872 return -EOPNOTSUPP; 873 } 874 875 /* Block buffer isn't supported for I2C block transactions */ 876 result = i801_block_transaction_byte_by_byte(priv, data, read_write, command); 877 878 /* restore saved configuration register value */ 879 if (read_write == I2C_SMBUS_WRITE) 880 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 881 882 return result; 883 } 884 885 /* Return negative errno on error. */ 886 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 887 unsigned short flags, char read_write, u8 command, 888 int size, union i2c_smbus_data *data) 889 { 890 int hwpec, ret; 891 struct i801_priv *priv = i2c_get_adapdata(adap); 892 893 if (priv->acpi_reserved) 894 return -EBUSY; 895 896 pm_runtime_get_sync(&priv->pci_dev->dev); 897 898 ret = i801_check_pre(priv); 899 if (ret) 900 goto out; 901 902 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 903 && size != I2C_SMBUS_QUICK 904 && size != I2C_SMBUS_I2C_BLOCK_DATA; 905 906 if (hwpec) /* enable/disable hardware PEC */ 907 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 908 else 909 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 910 SMBAUXCTL(priv)); 911 912 if (size == I2C_SMBUS_BLOCK_DATA || size == I2C_SMBUS_BLOCK_PROC_CALL) 913 ret = i801_smbus_block_transaction(priv, data, addr, command, read_write, size); 914 else if (size == I2C_SMBUS_I2C_BLOCK_DATA) 915 ret = i801_i2c_block_transaction(priv, data, addr, command, read_write, size); 916 else 917 ret = i801_simple_transaction(priv, data, addr, command, read_write, size); 918 919 ret = i801_check_post(priv, ret); 920 921 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 922 * time, so we forcibly disable it after every transaction. 923 */ 924 if (hwpec) 925 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv)); 926 out: 927 /* 928 * Unlock the SMBus device for use by BIOS/ACPI, 929 * and clear status flags if not done already. 930 */ 931 outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv)); 932 933 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 934 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 935 return ret; 936 } 937 938 939 static u32 i801_func(struct i2c_adapter *adapter) 940 { 941 struct i801_priv *priv = i2c_get_adapdata(adapter); 942 943 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 944 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 945 I2C_FUNC_SMBUS_PROC_CALL | 946 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 947 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 948 ((priv->features & FEATURE_BLOCK_PROC) ? 949 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 950 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 951 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 952 ((priv->features & FEATURE_HOST_NOTIFY) ? 953 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 954 } 955 956 static void i801_enable_host_notify(struct i2c_adapter *adapter) 957 { 958 struct i801_priv *priv = i2c_get_adapdata(adapter); 959 960 if (!(priv->features & FEATURE_HOST_NOTIFY)) 961 return; 962 963 /* 964 * Enable host notify interrupt and block the generation of interrupt 965 * from the SMB_ALERT signal because the driver does not support 966 * SMBus Alert. 967 */ 968 outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE | 969 priv->original_slvcmd, SMBSLVCMD(priv)); 970 971 /* clear Host Notify bit to allow a new notification */ 972 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 973 } 974 975 static void i801_disable_host_notify(struct i801_priv *priv) 976 { 977 if (!(priv->features & FEATURE_HOST_NOTIFY)) 978 return; 979 980 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 981 } 982 983 static const struct i2c_algorithm smbus_algorithm = { 984 .smbus_xfer = i801_access, 985 .functionality = i801_func, 986 }; 987 988 #define FEATURES_ICH4 (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \ 989 FEATURE_HOST_NOTIFY) 990 #define FEATURES_ICH5 (FEATURES_ICH4 | FEATURE_BLOCK_PROC | \ 991 FEATURE_I2C_BLOCK_READ | FEATURE_IRQ) 992 993 static const struct pci_device_id i801_ids[] = { 994 { PCI_DEVICE_DATA(INTEL, 82801AA_3, 0) }, 995 { PCI_DEVICE_DATA(INTEL, 82801AB_3, 0) }, 996 { PCI_DEVICE_DATA(INTEL, 82801BA_2, 0) }, 997 { PCI_DEVICE_DATA(INTEL, 82801CA_3, FEATURE_HOST_NOTIFY) }, 998 { PCI_DEVICE_DATA(INTEL, 82801DB_3, FEATURES_ICH4) }, 999 { PCI_DEVICE_DATA(INTEL, 82801EB_3, FEATURES_ICH5) }, 1000 { PCI_DEVICE_DATA(INTEL, ESB_4, FEATURES_ICH5) }, 1001 { PCI_DEVICE_DATA(INTEL, ICH6_16, FEATURES_ICH5) }, 1002 { PCI_DEVICE_DATA(INTEL, ICH7_17, FEATURES_ICH5) }, 1003 { PCI_DEVICE_DATA(INTEL, ESB2_17, FEATURES_ICH5) }, 1004 { PCI_DEVICE_DATA(INTEL, ICH8_5, FEATURES_ICH5) }, 1005 { PCI_DEVICE_DATA(INTEL, ICH9_6, FEATURES_ICH5) }, 1006 { PCI_DEVICE_DATA(INTEL, EP80579_1, FEATURES_ICH5) }, 1007 { PCI_DEVICE_DATA(INTEL, ICH10_4, FEATURES_ICH5) }, 1008 { PCI_DEVICE_DATA(INTEL, ICH10_5, FEATURES_ICH5) }, 1009 { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS, FEATURES_ICH5) }, 1010 { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5) }, 1011 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS, FEATURES_ICH5) }, 1012 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0, FEATURES_ICH5 | FEATURE_IDF) }, 1013 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1, FEATURES_ICH5 | FEATURE_IDF) }, 1014 { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2, FEATURES_ICH5 | FEATURE_IDF) }, 1015 { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS, FEATURES_ICH5) }, 1016 { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS, FEATURES_ICH5) }, 1017 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS, FEATURES_ICH5) }, 1018 { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS, FEATURES_ICH5) }, 1019 { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS, FEATURES_ICH5) }, 1020 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS, FEATURES_ICH5) }, 1021 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0, FEATURES_ICH5 | FEATURE_IDF) }, 1022 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1, FEATURES_ICH5 | FEATURE_IDF) }, 1023 { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2, FEATURES_ICH5 | FEATURE_IDF) }, 1024 { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5) }, 1025 { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS, FEATURES_ICH5) }, 1026 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS, FEATURES_ICH5) }, 1027 { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5) }, 1028 { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS, FEATURES_ICH5) }, 1029 { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS, FEATURES_ICH5) }, 1030 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1031 { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1032 { PCI_DEVICE_DATA(INTEL, CDF_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1033 { PCI_DEVICE_DATA(INTEL, DNV_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1034 { PCI_DEVICE_DATA(INTEL, EBG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1035 { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS, FEATURES_ICH5) }, 1036 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1037 { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1038 { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1039 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1040 { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1041 { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1042 { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1043 { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1044 { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1045 { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) }, 1046 { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1047 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1048 { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1049 { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1050 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1051 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1052 { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1053 { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1054 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1055 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_SOC_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1056 { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_PCH_S_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1057 { PCI_DEVICE_DATA(INTEL, BIRCH_STREAM_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) }, 1058 { 0, } 1059 }; 1060 1061 MODULE_DEVICE_TABLE(pci, i801_ids); 1062 1063 #if defined CONFIG_X86 && defined CONFIG_DMI 1064 static unsigned char apanel_addr; 1065 1066 /* Scan the system ROM for the signature "FJKEYINF" */ 1067 static __init const void __iomem *bios_signature(const void __iomem *bios) 1068 { 1069 ssize_t offset; 1070 const unsigned char signature[] = "FJKEYINF"; 1071 1072 for (offset = 0; offset < 0x10000; offset += 0x10) { 1073 if (check_signature(bios + offset, signature, 1074 sizeof(signature)-1)) 1075 return bios + offset; 1076 } 1077 return NULL; 1078 } 1079 1080 static void __init input_apanel_init(void) 1081 { 1082 void __iomem *bios; 1083 const void __iomem *p; 1084 1085 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1086 p = bios_signature(bios); 1087 if (p) { 1088 /* just use the first address */ 1089 apanel_addr = readb(p + 8 + 3) >> 1; 1090 } 1091 iounmap(bios); 1092 } 1093 1094 struct dmi_onboard_device_info { 1095 const char *name; 1096 u8 type; 1097 unsigned short i2c_addr; 1098 const char *i2c_type; 1099 }; 1100 1101 static const struct dmi_onboard_device_info dmi_devices[] = { 1102 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1103 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1104 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1105 }; 1106 1107 static void dmi_check_onboard_device(u8 type, const char *name, 1108 struct i2c_adapter *adap) 1109 { 1110 int i; 1111 struct i2c_board_info info; 1112 1113 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1114 /* & ~0x80, ignore enabled/disabled bit */ 1115 if ((type & ~0x80) != dmi_devices[i].type) 1116 continue; 1117 if (strcasecmp(name, dmi_devices[i].name)) 1118 continue; 1119 1120 memset(&info, 0, sizeof(struct i2c_board_info)); 1121 info.addr = dmi_devices[i].i2c_addr; 1122 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1123 i2c_new_client_device(adap, &info); 1124 break; 1125 } 1126 } 1127 1128 /* We use our own function to check for onboard devices instead of 1129 dmi_find_device() as some buggy BIOS's have the devices we are interested 1130 in marked as disabled */ 1131 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1132 { 1133 int i, count; 1134 1135 if (dm->type != DMI_ENTRY_ONBOARD_DEVICE) 1136 return; 1137 1138 count = (dm->length - sizeof(struct dmi_header)) / 2; 1139 for (i = 0; i < count; i++) { 1140 const u8 *d = (char *)(dm + 1) + (i * 2); 1141 const char *name = ((char *) dm) + dm->length; 1142 u8 type = d[0]; 1143 u8 s = d[1]; 1144 1145 if (!s) 1146 continue; 1147 s--; 1148 while (s > 0 && name[0]) { 1149 name += strlen(name) + 1; 1150 s--; 1151 } 1152 if (name[0] == 0) /* Bogus string reference */ 1153 continue; 1154 1155 dmi_check_onboard_device(type, name, adap); 1156 } 1157 } 1158 1159 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1160 static const char *const acpi_smo8800_ids[] = { 1161 "SMO8800", 1162 "SMO8801", 1163 "SMO8810", 1164 "SMO8811", 1165 "SMO8820", 1166 "SMO8821", 1167 "SMO8830", 1168 "SMO8831", 1169 }; 1170 1171 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1172 u32 nesting_level, 1173 void *context, 1174 void **return_value) 1175 { 1176 struct acpi_device_info *info; 1177 acpi_status status; 1178 char *hid; 1179 int i; 1180 1181 status = acpi_get_object_info(obj_handle, &info); 1182 if (ACPI_FAILURE(status)) 1183 return AE_OK; 1184 1185 if (!(info->valid & ACPI_VALID_HID)) 1186 goto smo88xx_not_found; 1187 1188 hid = info->hardware_id.string; 1189 if (!hid) 1190 goto smo88xx_not_found; 1191 1192 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1193 if (i < 0) 1194 goto smo88xx_not_found; 1195 1196 kfree(info); 1197 1198 *return_value = NULL; 1199 return AE_CTRL_TERMINATE; 1200 1201 smo88xx_not_found: 1202 kfree(info); 1203 return AE_OK; 1204 } 1205 1206 static bool is_dell_system_with_lis3lv02d(void) 1207 { 1208 void *err = ERR_PTR(-ENOENT); 1209 1210 if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc.")) 1211 return false; 1212 1213 /* 1214 * Check that ACPI device SMO88xx is present and is functioning. 1215 * Function acpi_get_devices() already filters all ACPI devices 1216 * which are not present or are not functioning. 1217 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1218 * accelerometer but unfortunately ACPI does not provide any other 1219 * information (like I2C address). 1220 */ 1221 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err); 1222 1223 return !IS_ERR(err); 1224 } 1225 1226 /* 1227 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1228 * so it is needed to define mapping table based on DMI product names. 1229 */ 1230 static const struct { 1231 const char *dmi_product_name; 1232 unsigned short i2c_addr; 1233 } dell_lis3lv02d_devices[] = { 1234 /* 1235 * Dell platform team told us that these Latitude devices have 1236 * ST microelectronics accelerometer at I2C address 0x29. 1237 */ 1238 { "Latitude E5250", 0x29 }, 1239 { "Latitude E5450", 0x29 }, 1240 { "Latitude E5550", 0x29 }, 1241 { "Latitude E6440", 0x29 }, 1242 { "Latitude E6440 ATG", 0x29 }, 1243 { "Latitude E6540", 0x29 }, 1244 /* 1245 * Additional individual entries were added after verification. 1246 */ 1247 { "Latitude 5480", 0x29 }, 1248 { "Precision 3540", 0x29 }, 1249 { "Vostro V131", 0x1d }, 1250 { "Vostro 5568", 0x29 }, 1251 { "XPS 15 7590", 0x29 }, 1252 }; 1253 1254 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1255 { 1256 struct i2c_board_info info; 1257 const char *dmi_product_name; 1258 int i; 1259 1260 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1261 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1262 if (strcmp(dmi_product_name, 1263 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1264 break; 1265 } 1266 1267 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1268 dev_warn(&priv->pci_dev->dev, 1269 "Accelerometer lis3lv02d is present on SMBus but its" 1270 " address is unknown, skipping registration\n"); 1271 return; 1272 } 1273 1274 memset(&info, 0, sizeof(struct i2c_board_info)); 1275 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1276 strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1277 i2c_new_client_device(&priv->adapter, &info); 1278 } 1279 1280 /* Register optional slaves */ 1281 static void i801_probe_optional_slaves(struct i801_priv *priv) 1282 { 1283 /* Only register slaves on main SMBus channel */ 1284 if (priv->features & FEATURE_IDF) 1285 return; 1286 1287 if (apanel_addr) { 1288 struct i2c_board_info info = { 1289 .addr = apanel_addr, 1290 .type = "fujitsu_apanel", 1291 }; 1292 1293 i2c_new_client_device(&priv->adapter, &info); 1294 } 1295 1296 if (dmi_name_in_vendors("FUJITSU")) 1297 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1298 1299 if (is_dell_system_with_lis3lv02d()) 1300 register_dell_lis3lv02d_i2c_device(priv); 1301 1302 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1303 #ifdef CONFIG_I2C_I801_MUX 1304 if (!priv->mux_pdev) 1305 #endif 1306 i2c_register_spd(&priv->adapter); 1307 } 1308 #else 1309 static void __init input_apanel_init(void) {} 1310 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1311 #endif /* CONFIG_X86 && CONFIG_DMI */ 1312 1313 #ifdef CONFIG_I2C_I801_MUX 1314 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1315 .gpio_chip = "gpio_ich", 1316 .values = { 0x02, 0x03 }, 1317 .n_values = 2, 1318 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1319 .gpios = { 52, 53 }, 1320 .n_gpios = 2, 1321 }; 1322 1323 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1324 .gpio_chip = "gpio_ich", 1325 .values = { 0x02, 0x03, 0x01 }, 1326 .n_values = 3, 1327 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1328 .gpios = { 52, 53 }, 1329 .n_gpios = 2, 1330 }; 1331 1332 static const struct dmi_system_id mux_dmi_table[] = { 1333 { 1334 .matches = { 1335 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1336 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1337 }, 1338 .driver_data = &i801_mux_config_asus_z8_d12, 1339 }, 1340 { 1341 .matches = { 1342 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1343 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1344 }, 1345 .driver_data = &i801_mux_config_asus_z8_d12, 1346 }, 1347 { 1348 .matches = { 1349 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1350 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1351 }, 1352 .driver_data = &i801_mux_config_asus_z8_d12, 1353 }, 1354 { 1355 .matches = { 1356 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1357 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1358 }, 1359 .driver_data = &i801_mux_config_asus_z8_d12, 1360 }, 1361 { 1362 .matches = { 1363 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1364 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1365 }, 1366 .driver_data = &i801_mux_config_asus_z8_d12, 1367 }, 1368 { 1369 .matches = { 1370 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1371 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1372 }, 1373 .driver_data = &i801_mux_config_asus_z8_d12, 1374 }, 1375 { 1376 .matches = { 1377 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1378 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1379 }, 1380 .driver_data = &i801_mux_config_asus_z8_d18, 1381 }, 1382 { 1383 .matches = { 1384 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1385 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1386 }, 1387 .driver_data = &i801_mux_config_asus_z8_d18, 1388 }, 1389 { 1390 .matches = { 1391 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1392 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1393 }, 1394 .driver_data = &i801_mux_config_asus_z8_d12, 1395 }, 1396 { } 1397 }; 1398 1399 static int i801_notifier_call(struct notifier_block *nb, unsigned long action, 1400 void *data) 1401 { 1402 struct i801_priv *priv = container_of(nb, struct i801_priv, mux_notifier_block); 1403 struct device *dev = data; 1404 1405 if (action != BUS_NOTIFY_ADD_DEVICE || 1406 dev->type != &i2c_adapter_type || 1407 i2c_root_adapter(dev) != &priv->adapter) 1408 return NOTIFY_DONE; 1409 1410 /* Call i2c_register_spd for muxed child segments */ 1411 i2c_register_spd(to_i2c_adapter(dev)); 1412 1413 return NOTIFY_OK; 1414 } 1415 1416 /* Setup multiplexing if needed */ 1417 static void i801_add_mux(struct i801_priv *priv) 1418 { 1419 struct device *dev = &priv->adapter.dev; 1420 const struct i801_mux_config *mux_config; 1421 struct i2c_mux_gpio_platform_data gpio_data; 1422 struct gpiod_lookup_table *lookup; 1423 const struct dmi_system_id *id; 1424 int i; 1425 1426 id = dmi_first_match(mux_dmi_table); 1427 if (!id) 1428 return; 1429 1430 mux_config = id->driver_data; 1431 1432 /* Prepare the platform data */ 1433 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1434 gpio_data.parent = priv->adapter.nr; 1435 gpio_data.values = mux_config->values; 1436 gpio_data.n_values = mux_config->n_values; 1437 gpio_data.classes = mux_config->classes; 1438 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1439 1440 /* Register GPIO descriptor lookup table */ 1441 lookup = devm_kzalloc(dev, 1442 struct_size(lookup, table, mux_config->n_gpios + 1), 1443 GFP_KERNEL); 1444 if (!lookup) 1445 return; 1446 lookup->dev_id = "i2c-mux-gpio"; 1447 for (i = 0; i < mux_config->n_gpios; i++) 1448 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip, 1449 mux_config->gpios[i], "mux", 0); 1450 gpiod_add_lookup_table(lookup); 1451 1452 priv->mux_notifier_block.notifier_call = i801_notifier_call; 1453 if (bus_register_notifier(&i2c_bus_type, &priv->mux_notifier_block)) 1454 return; 1455 /* 1456 * Register the mux device, we use PLATFORM_DEVID_NONE here 1457 * because since we are referring to the GPIO chip by name we are 1458 * anyways in deep trouble if there is more than one of these 1459 * devices, and there should likely only be one platform controller 1460 * hub. 1461 */ 1462 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1463 PLATFORM_DEVID_NONE, &gpio_data, 1464 sizeof(struct i2c_mux_gpio_platform_data)); 1465 if (IS_ERR(priv->mux_pdev)) { 1466 gpiod_remove_lookup_table(lookup); 1467 devm_kfree(dev, lookup); 1468 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1469 } else { 1470 priv->lookup = lookup; 1471 } 1472 } 1473 1474 static void i801_del_mux(struct i801_priv *priv) 1475 { 1476 bus_unregister_notifier(&i2c_bus_type, &priv->mux_notifier_block); 1477 platform_device_unregister(priv->mux_pdev); 1478 gpiod_remove_lookup_table(priv->lookup); 1479 } 1480 #else 1481 static inline void i801_add_mux(struct i801_priv *priv) { } 1482 static inline void i801_del_mux(struct i801_priv *priv) { } 1483 #endif 1484 1485 static struct platform_device * 1486 i801_add_tco_spt(struct pci_dev *pci_dev, struct resource *tco_res) 1487 { 1488 static const struct itco_wdt_platform_data pldata = { 1489 .name = "Intel PCH", 1490 .version = 4, 1491 }; 1492 struct resource *res; 1493 int ret; 1494 1495 /* 1496 * We must access the NO_REBOOT bit over the Primary to Sideband 1497 * (P2SB) bridge. 1498 */ 1499 1500 res = &tco_res[1]; 1501 ret = p2sb_bar(pci_dev->bus, 0, res); 1502 if (ret) 1503 return ERR_PTR(ret); 1504 1505 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1506 res->start += SBREG_SMBCTRL_DNV; 1507 else 1508 res->start += SBREG_SMBCTRL; 1509 1510 res->end = res->start + 3; 1511 1512 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1513 tco_res, 2, &pldata, sizeof(pldata)); 1514 } 1515 1516 static struct platform_device * 1517 i801_add_tco_cnl(struct pci_dev *pci_dev, struct resource *tco_res) 1518 { 1519 static const struct itco_wdt_platform_data pldata = { 1520 .name = "Intel PCH", 1521 .version = 6, 1522 }; 1523 1524 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1525 tco_res, 1, &pldata, sizeof(pldata)); 1526 } 1527 1528 static void i801_add_tco(struct i801_priv *priv) 1529 { 1530 struct pci_dev *pci_dev = priv->pci_dev; 1531 struct resource tco_res[2], *res; 1532 u32 tco_base, tco_ctl; 1533 1534 /* If we have ACPI based watchdog use that instead */ 1535 if (acpi_has_watchdog()) 1536 return; 1537 1538 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1539 return; 1540 1541 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1542 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1543 if (!(tco_ctl & TCOCTL_EN)) 1544 return; 1545 1546 memset(tco_res, 0, sizeof(tco_res)); 1547 /* 1548 * Always populate the main iTCO IO resource here. The second entry 1549 * for NO_REBOOT MMIO is filled by the SPT specific function. 1550 */ 1551 res = &tco_res[0]; 1552 res->start = tco_base & ~1; 1553 res->end = res->start + 32 - 1; 1554 res->flags = IORESOURCE_IO; 1555 1556 if (priv->features & FEATURE_TCO_CNL) 1557 priv->tco_pdev = i801_add_tco_cnl(pci_dev, tco_res); 1558 else 1559 priv->tco_pdev = i801_add_tco_spt(pci_dev, tco_res); 1560 1561 if (IS_ERR(priv->tco_pdev)) 1562 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1563 } 1564 1565 #ifdef CONFIG_ACPI 1566 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1567 acpi_physical_address address) 1568 { 1569 return address >= priv->smba && 1570 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1571 } 1572 1573 static acpi_status 1574 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1575 u64 *value, void *handler_context, void *region_context) 1576 { 1577 struct i801_priv *priv = handler_context; 1578 struct pci_dev *pdev = priv->pci_dev; 1579 acpi_status status; 1580 1581 /* 1582 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1583 * further access from the driver itself. This device is now owned 1584 * by the system firmware. 1585 */ 1586 i2c_lock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1587 1588 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1589 priv->acpi_reserved = true; 1590 1591 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1592 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1593 1594 /* 1595 * BIOS is accessing the host controller so prevent it from 1596 * suspending automatically from now on. 1597 */ 1598 pm_runtime_get_sync(&pdev->dev); 1599 } 1600 1601 if ((function & ACPI_IO_MASK) == ACPI_READ) 1602 status = acpi_os_read_port(address, (u32 *)value, bits); 1603 else 1604 status = acpi_os_write_port(address, (u32)*value, bits); 1605 1606 i2c_unlock_bus(&priv->adapter, I2C_LOCK_SEGMENT); 1607 1608 return status; 1609 } 1610 1611 static int i801_acpi_probe(struct i801_priv *priv) 1612 { 1613 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1614 acpi_status status; 1615 1616 status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, 1617 i801_acpi_io_handler, NULL, priv); 1618 if (ACPI_SUCCESS(status)) 1619 return 0; 1620 1621 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1622 } 1623 1624 static void i801_acpi_remove(struct i801_priv *priv) 1625 { 1626 acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev); 1627 1628 acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1629 } 1630 #else 1631 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1632 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1633 #endif 1634 1635 static void i801_setup_hstcfg(struct i801_priv *priv) 1636 { 1637 unsigned char hstcfg = priv->original_hstcfg; 1638 1639 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1640 hstcfg |= SMBHSTCFG_HST_EN; 1641 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1642 } 1643 1644 static void i801_restore_regs(struct i801_priv *priv) 1645 { 1646 outb_p(priv->original_hstcnt, SMBHSTCNT(priv)); 1647 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1648 } 1649 1650 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1651 { 1652 int err, i; 1653 struct i801_priv *priv; 1654 1655 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1656 if (!priv) 1657 return -ENOMEM; 1658 1659 i2c_set_adapdata(&priv->adapter, priv); 1660 priv->adapter.owner = THIS_MODULE; 1661 priv->adapter.class = I2C_CLASS_HWMON; 1662 priv->adapter.algo = &smbus_algorithm; 1663 priv->adapter.dev.parent = &dev->dev; 1664 acpi_use_parent_companion(&priv->adapter.dev); 1665 priv->adapter.retries = 3; 1666 1667 priv->pci_dev = dev; 1668 priv->features = id->driver_data; 1669 1670 /* Disable features on user request */ 1671 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1672 if (priv->features & disable_features & (1 << i)) 1673 dev_notice(&dev->dev, "%s disabled by user\n", 1674 i801_feature_names[i]); 1675 } 1676 priv->features &= ~disable_features; 1677 1678 /* The block process call uses block buffer mode */ 1679 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1680 priv->features &= ~FEATURE_BLOCK_PROC; 1681 1682 err = pcim_enable_device(dev); 1683 if (err) { 1684 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1685 err); 1686 return err; 1687 } 1688 pcim_pin_device(dev); 1689 1690 /* Determine the address of the SMBus area */ 1691 priv->smba = pci_resource_start(dev, SMBBAR); 1692 if (!priv->smba) { 1693 dev_err(&dev->dev, 1694 "SMBus base address uninitialized, upgrade BIOS\n"); 1695 return -ENODEV; 1696 } 1697 1698 if (i801_acpi_probe(priv)) 1699 return -ENODEV; 1700 1701 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME); 1702 if (err) { 1703 dev_err(&dev->dev, 1704 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1705 priv->smba, 1706 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1707 i801_acpi_remove(priv); 1708 return err; 1709 } 1710 1711 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1712 i801_setup_hstcfg(priv); 1713 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1714 dev_info(&dev->dev, "Enabling SMBus device\n"); 1715 1716 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) { 1717 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1718 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1719 priv->features &= ~FEATURE_IRQ; 1720 } 1721 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD) 1722 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1723 1724 /* Clear special mode bits */ 1725 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1726 outb_p(inb_p(SMBAUXCTL(priv)) & 1727 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1728 1729 /* Default timeout in interrupt mode: 200 ms */ 1730 priv->adapter.timeout = HZ / 5; 1731 1732 if (dev->irq == IRQ_NOTCONNECTED) 1733 priv->features &= ~FEATURE_IRQ; 1734 1735 if (priv->features & FEATURE_IRQ) { 1736 u16 pcists; 1737 1738 /* Complain if an interrupt is already pending */ 1739 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists); 1740 if (pcists & PCI_STATUS_INTERRUPT) 1741 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1742 } 1743 1744 if (priv->features & FEATURE_IRQ) { 1745 init_completion(&priv->done); 1746 1747 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1748 IRQF_SHARED, DRV_NAME, priv); 1749 if (err) { 1750 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1751 dev->irq, err); 1752 priv->features &= ~FEATURE_IRQ; 1753 } 1754 } 1755 dev_info(&dev->dev, "SMBus using %s\n", 1756 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1757 1758 /* Host notification uses an interrupt */ 1759 if (!(priv->features & FEATURE_IRQ)) 1760 priv->features &= ~FEATURE_HOST_NOTIFY; 1761 1762 /* Remember original Interrupt and Host Notify settings */ 1763 priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL; 1764 if (priv->features & FEATURE_HOST_NOTIFY) 1765 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1766 1767 i801_add_tco(priv); 1768 1769 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1770 "SMBus I801 adapter at %04lx", priv->smba); 1771 err = i2c_add_adapter(&priv->adapter); 1772 if (err) { 1773 platform_device_unregister(priv->tco_pdev); 1774 i801_acpi_remove(priv); 1775 i801_restore_regs(priv); 1776 return err; 1777 } 1778 1779 i801_enable_host_notify(&priv->adapter); 1780 1781 /* We ignore errors - multiplexing is optional */ 1782 i801_add_mux(priv); 1783 i801_probe_optional_slaves(priv); 1784 1785 pci_set_drvdata(dev, priv); 1786 1787 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1788 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1789 pm_runtime_use_autosuspend(&dev->dev); 1790 pm_runtime_put_autosuspend(&dev->dev); 1791 pm_runtime_allow(&dev->dev); 1792 1793 return 0; 1794 } 1795 1796 static void i801_remove(struct pci_dev *dev) 1797 { 1798 struct i801_priv *priv = pci_get_drvdata(dev); 1799 1800 i801_disable_host_notify(priv); 1801 i801_del_mux(priv); 1802 i2c_del_adapter(&priv->adapter); 1803 i801_acpi_remove(priv); 1804 1805 platform_device_unregister(priv->tco_pdev); 1806 1807 /* if acpi_reserved is set then usage_count is incremented already */ 1808 if (!priv->acpi_reserved) 1809 pm_runtime_get_noresume(&dev->dev); 1810 1811 i801_restore_regs(priv); 1812 1813 /* 1814 * do not call pci_disable_device(dev) since it can cause hard hangs on 1815 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1816 */ 1817 } 1818 1819 static void i801_shutdown(struct pci_dev *dev) 1820 { 1821 struct i801_priv *priv = pci_get_drvdata(dev); 1822 1823 i801_disable_host_notify(priv); 1824 /* Restore config registers to avoid hard hang on some systems */ 1825 i801_restore_regs(priv); 1826 } 1827 1828 static int i801_suspend(struct device *dev) 1829 { 1830 struct i801_priv *priv = dev_get_drvdata(dev); 1831 1832 i2c_mark_adapter_suspended(&priv->adapter); 1833 i801_restore_regs(priv); 1834 1835 return 0; 1836 } 1837 1838 static int i801_resume(struct device *dev) 1839 { 1840 struct i801_priv *priv = dev_get_drvdata(dev); 1841 1842 i801_setup_hstcfg(priv); 1843 i801_enable_host_notify(&priv->adapter); 1844 i2c_mark_adapter_resumed(&priv->adapter); 1845 1846 return 0; 1847 } 1848 1849 static DEFINE_SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1850 1851 static struct pci_driver i801_driver = { 1852 .name = DRV_NAME, 1853 .id_table = i801_ids, 1854 .probe = i801_probe, 1855 .remove = i801_remove, 1856 .shutdown = i801_shutdown, 1857 .driver = { 1858 .pm = pm_sleep_ptr(&i801_pm_ops), 1859 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1860 }, 1861 }; 1862 1863 static int __init i2c_i801_init(struct pci_driver *drv) 1864 { 1865 if (dmi_name_in_vendors("FUJITSU")) 1866 input_apanel_init(); 1867 return pci_register_driver(drv); 1868 } 1869 1870 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 1871 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 1872 MODULE_DESCRIPTION("I801 SMBus driver"); 1873 MODULE_LICENSE("GPL"); 1874 1875 module_driver(i801_driver, i2c_i801_init, pci_unregister_driver); 1876