1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10 */ 11 12 /* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 58 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 59 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 60 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 61 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 62 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 63 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 64 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 65 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 66 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 67 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 68 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 69 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 70 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 71 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 72 * 73 * Features supported by this driver: 74 * Software PEC no 75 * Hardware PEC yes 76 * Block buffer yes 77 * Block process call transaction yes 78 * I2C block read transaction yes (doesn't use the block buffer) 79 * Slave mode no 80 * SMBus Host Notify yes 81 * Interrupt processing yes 82 * 83 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 84 */ 85 86 #include <linux/interrupt.h> 87 #include <linux/module.h> 88 #include <linux/pci.h> 89 #include <linux/kernel.h> 90 #include <linux/stddef.h> 91 #include <linux/delay.h> 92 #include <linux/ioport.h> 93 #include <linux/init.h> 94 #include <linux/i2c.h> 95 #include <linux/i2c-smbus.h> 96 #include <linux/acpi.h> 97 #include <linux/io.h> 98 #include <linux/dmi.h> 99 #include <linux/slab.h> 100 #include <linux/string.h> 101 #include <linux/wait.h> 102 #include <linux/err.h> 103 #include <linux/platform_device.h> 104 #include <linux/platform_data/itco_wdt.h> 105 #include <linux/pm_runtime.h> 106 107 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 108 #include <linux/gpio/machine.h> 109 #include <linux/platform_data/i2c-mux-gpio.h> 110 #endif 111 112 /* I801 SMBus address offsets */ 113 #define SMBHSTSTS(p) (0 + (p)->smba) 114 #define SMBHSTCNT(p) (2 + (p)->smba) 115 #define SMBHSTCMD(p) (3 + (p)->smba) 116 #define SMBHSTADD(p) (4 + (p)->smba) 117 #define SMBHSTDAT0(p) (5 + (p)->smba) 118 #define SMBHSTDAT1(p) (6 + (p)->smba) 119 #define SMBBLKDAT(p) (7 + (p)->smba) 120 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 121 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 122 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 123 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 124 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 125 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 126 127 /* PCI Address Constants */ 128 #define SMBBAR 4 129 #define SMBPCICTL 0x004 130 #define SMBPCISTS 0x006 131 #define SMBHSTCFG 0x040 132 #define TCOBASE 0x050 133 #define TCOCTL 0x054 134 135 #define ACPIBASE 0x040 136 #define ACPIBASE_SMI_OFF 0x030 137 #define ACPICTRL 0x044 138 #define ACPICTRL_EN 0x080 139 140 #define SBREG_BAR 0x10 141 #define SBREG_SMBCTRL 0xc6000c 142 #define SBREG_SMBCTRL_DNV 0xcf000c 143 144 /* Host status bits for SMBPCISTS */ 145 #define SMBPCISTS_INTS BIT(3) 146 147 /* Control bits for SMBPCICTL */ 148 #define SMBPCICTL_INTDIS BIT(10) 149 150 /* Host configuration bits for SMBHSTCFG */ 151 #define SMBHSTCFG_HST_EN BIT(0) 152 #define SMBHSTCFG_SMB_SMI_EN BIT(1) 153 #define SMBHSTCFG_I2C_EN BIT(2) 154 #define SMBHSTCFG_SPD_WD BIT(4) 155 156 /* TCO configuration bits for TCOCTL */ 157 #define TCOCTL_EN BIT(8) 158 159 /* Auxiliary status register bits, ICH4+ only */ 160 #define SMBAUXSTS_CRCE BIT(0) 161 #define SMBAUXSTS_STCO BIT(1) 162 163 /* Auxiliary control register bits, ICH4+ only */ 164 #define SMBAUXCTL_CRC BIT(0) 165 #define SMBAUXCTL_E32B BIT(1) 166 167 /* Other settings */ 168 #define MAX_RETRIES 400 169 170 /* I801 command constants */ 171 #define I801_QUICK 0x00 172 #define I801_BYTE 0x04 173 #define I801_BYTE_DATA 0x08 174 #define I801_WORD_DATA 0x0C 175 #define I801_PROC_CALL 0x10 /* unimplemented */ 176 #define I801_BLOCK_DATA 0x14 177 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 178 #define I801_BLOCK_PROC_CALL 0x1C 179 180 /* I801 Host Control register bits */ 181 #define SMBHSTCNT_INTREN BIT(0) 182 #define SMBHSTCNT_KILL BIT(1) 183 #define SMBHSTCNT_LAST_BYTE BIT(5) 184 #define SMBHSTCNT_START BIT(6) 185 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 186 187 /* I801 Hosts Status register bits */ 188 #define SMBHSTSTS_BYTE_DONE BIT(7) 189 #define SMBHSTSTS_INUSE_STS BIT(6) 190 #define SMBHSTSTS_SMBALERT_STS BIT(5) 191 #define SMBHSTSTS_FAILED BIT(4) 192 #define SMBHSTSTS_BUS_ERR BIT(3) 193 #define SMBHSTSTS_DEV_ERR BIT(2) 194 #define SMBHSTSTS_INTR BIT(1) 195 #define SMBHSTSTS_HOST_BUSY BIT(0) 196 197 /* Host Notify Status register bits */ 198 #define SMBSLVSTS_HST_NTFY_STS BIT(0) 199 200 /* Host Notify Command register bits */ 201 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 202 203 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 204 SMBHSTSTS_DEV_ERR) 205 206 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 207 STATUS_ERROR_FLAGS) 208 209 /* Older devices have their ID defined in <linux/pci_ids.h> */ 210 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 211 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 212 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 213 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 214 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 215 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 217 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 220 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 221 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 222 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 223 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 224 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 225 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 226 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 227 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 228 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 229 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 230 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 231 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 232 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 233 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 238 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 239 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 240 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 241 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 242 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 243 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 245 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 246 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 247 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 248 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 249 250 struct i801_mux_config { 251 char *gpio_chip; 252 unsigned values[3]; 253 int n_values; 254 unsigned classes[3]; 255 unsigned gpios[2]; /* Relative to gpio_chip->base */ 256 int n_gpios; 257 }; 258 259 struct i801_priv { 260 struct i2c_adapter adapter; 261 unsigned long smba; 262 unsigned char original_hstcfg; 263 unsigned char original_slvcmd; 264 struct pci_dev *pci_dev; 265 unsigned int features; 266 267 /* isr processing */ 268 wait_queue_head_t waitq; 269 u8 status; 270 271 /* Command state used by isr for byte-by-byte block transactions */ 272 u8 cmd; 273 bool is_read; 274 int count; 275 int len; 276 u8 *data; 277 278 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 279 const struct i801_mux_config *mux_drvdata; 280 struct platform_device *mux_pdev; 281 struct gpiod_lookup_table *lookup; 282 #endif 283 struct platform_device *tco_pdev; 284 285 /* 286 * If set to true the host controller registers are reserved for 287 * ACPI AML use. Protected by acpi_lock. 288 */ 289 bool acpi_reserved; 290 struct mutex acpi_lock; 291 }; 292 293 #define FEATURE_SMBUS_PEC BIT(0) 294 #define FEATURE_BLOCK_BUFFER BIT(1) 295 #define FEATURE_BLOCK_PROC BIT(2) 296 #define FEATURE_I2C_BLOCK_READ BIT(3) 297 #define FEATURE_IRQ BIT(4) 298 #define FEATURE_HOST_NOTIFY BIT(5) 299 /* Not really a feature, but it's convenient to handle it as such */ 300 #define FEATURE_IDF BIT(15) 301 #define FEATURE_TCO_SPT BIT(16) 302 #define FEATURE_TCO_CNL BIT(17) 303 304 static const char *i801_feature_names[] = { 305 "SMBus PEC", 306 "Block buffer", 307 "Block process call", 308 "I2C block read", 309 "Interrupt", 310 "SMBus Host Notify", 311 }; 312 313 static unsigned int disable_features; 314 module_param(disable_features, uint, S_IRUGO | S_IWUSR); 315 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 316 "\t\t 0x01 disable SMBus PEC\n" 317 "\t\t 0x02 disable the block buffer\n" 318 "\t\t 0x08 disable the I2C block read functionality\n" 319 "\t\t 0x10 don't use interrupts\n" 320 "\t\t 0x20 disable SMBus Host Notify "); 321 322 /* Make sure the SMBus host is ready to start transmitting. 323 Return 0 if it is, -EBUSY if it is not. */ 324 static int i801_check_pre(struct i801_priv *priv) 325 { 326 int status; 327 328 status = inb_p(SMBHSTSTS(priv)); 329 if (status & SMBHSTSTS_HOST_BUSY) { 330 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 331 return -EBUSY; 332 } 333 334 status &= STATUS_FLAGS; 335 if (status) { 336 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 337 status); 338 outb_p(status, SMBHSTSTS(priv)); 339 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 340 if (status) { 341 dev_err(&priv->pci_dev->dev, 342 "Failed clearing status flags (%02x)\n", 343 status); 344 return -EBUSY; 345 } 346 } 347 348 /* 349 * Clear CRC status if needed. 350 * During normal operation, i801_check_post() takes care 351 * of it after every operation. We do it here only in case 352 * the hardware was already in this state when the driver 353 * started. 354 */ 355 if (priv->features & FEATURE_SMBUS_PEC) { 356 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 357 if (status) { 358 dev_dbg(&priv->pci_dev->dev, 359 "Clearing aux status flags (%02x)\n", status); 360 outb_p(status, SMBAUXSTS(priv)); 361 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 362 if (status) { 363 dev_err(&priv->pci_dev->dev, 364 "Failed clearing aux status flags (%02x)\n", 365 status); 366 return -EBUSY; 367 } 368 } 369 } 370 371 return 0; 372 } 373 374 /* 375 * Convert the status register to an error code, and clear it. 376 * Note that status only contains the bits we want to clear, not the 377 * actual register value. 378 */ 379 static int i801_check_post(struct i801_priv *priv, int status) 380 { 381 int result = 0; 382 383 /* 384 * If the SMBus is still busy, we give up 385 * Note: This timeout condition only happens when using polling 386 * transactions. For interrupt operation, NAK/timeout is indicated by 387 * DEV_ERR. 388 */ 389 if (unlikely(status < 0)) { 390 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 391 /* try to stop the current command */ 392 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 393 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, 394 SMBHSTCNT(priv)); 395 usleep_range(1000, 2000); 396 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), 397 SMBHSTCNT(priv)); 398 399 /* Check if it worked */ 400 status = inb_p(SMBHSTSTS(priv)); 401 if ((status & SMBHSTSTS_HOST_BUSY) || 402 !(status & SMBHSTSTS_FAILED)) 403 dev_err(&priv->pci_dev->dev, 404 "Failed terminating the transaction\n"); 405 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 406 return -ETIMEDOUT; 407 } 408 409 if (status & SMBHSTSTS_FAILED) { 410 result = -EIO; 411 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 412 } 413 if (status & SMBHSTSTS_DEV_ERR) { 414 /* 415 * This may be a PEC error, check and clear it. 416 * 417 * AUXSTS is handled differently from HSTSTS. 418 * For HSTSTS, i801_isr() or i801_wait_intr() 419 * has already cleared the error bits in hardware, 420 * and we are passed a copy of the original value 421 * in "status". 422 * For AUXSTS, the hardware register is left 423 * for us to handle here. 424 * This is asymmetric, slightly iffy, but safe, 425 * since all this code is serialized and the CRCE 426 * bit is harmless as long as it's cleared before 427 * the next operation. 428 */ 429 if ((priv->features & FEATURE_SMBUS_PEC) && 430 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 431 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 432 result = -EBADMSG; 433 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 434 } else { 435 result = -ENXIO; 436 dev_dbg(&priv->pci_dev->dev, "No response\n"); 437 } 438 } 439 if (status & SMBHSTSTS_BUS_ERR) { 440 result = -EAGAIN; 441 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 442 } 443 444 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 445 outb_p(status, SMBHSTSTS(priv)); 446 447 return result; 448 } 449 450 /* Wait for BUSY being cleared and either INTR or an error flag being set */ 451 static int i801_wait_intr(struct i801_priv *priv) 452 { 453 int timeout = 0; 454 int status; 455 456 /* We will always wait for a fraction of a second! */ 457 do { 458 usleep_range(250, 500); 459 status = inb_p(SMBHSTSTS(priv)); 460 } while (((status & SMBHSTSTS_HOST_BUSY) || 461 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 462 (timeout++ < MAX_RETRIES)); 463 464 if (timeout > MAX_RETRIES) { 465 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 466 return -ETIMEDOUT; 467 } 468 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 469 } 470 471 /* Wait for either BYTE_DONE or an error flag being set */ 472 static int i801_wait_byte_done(struct i801_priv *priv) 473 { 474 int timeout = 0; 475 int status; 476 477 /* We will always wait for a fraction of a second! */ 478 do { 479 usleep_range(250, 500); 480 status = inb_p(SMBHSTSTS(priv)); 481 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 482 (timeout++ < MAX_RETRIES)); 483 484 if (timeout > MAX_RETRIES) { 485 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 486 return -ETIMEDOUT; 487 } 488 return status & STATUS_ERROR_FLAGS; 489 } 490 491 static int i801_transaction(struct i801_priv *priv, int xact) 492 { 493 int status; 494 int result; 495 const struct i2c_adapter *adap = &priv->adapter; 496 497 result = i801_check_pre(priv); 498 if (result < 0) 499 return result; 500 501 if (priv->features & FEATURE_IRQ) { 502 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 503 SMBHSTCNT(priv)); 504 result = wait_event_timeout(priv->waitq, 505 (status = priv->status), 506 adap->timeout); 507 if (!result) { 508 status = -ETIMEDOUT; 509 dev_warn(&priv->pci_dev->dev, 510 "Timeout waiting for interrupt!\n"); 511 } 512 priv->status = 0; 513 return i801_check_post(priv, status); 514 } 515 516 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 517 * SMBSCMD are passed in xact */ 518 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 519 520 status = i801_wait_intr(priv); 521 return i801_check_post(priv, status); 522 } 523 524 static int i801_block_transaction_by_block(struct i801_priv *priv, 525 union i2c_smbus_data *data, 526 char read_write, int command, 527 int hwpec) 528 { 529 int i, len; 530 int status; 531 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 532 533 switch (command) { 534 case I2C_SMBUS_BLOCK_PROC_CALL: 535 xact |= I801_BLOCK_PROC_CALL; 536 break; 537 case I2C_SMBUS_BLOCK_DATA: 538 xact |= I801_BLOCK_DATA; 539 break; 540 default: 541 return -EOPNOTSUPP; 542 } 543 544 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 545 546 /* Use 32-byte buffer to process this transaction */ 547 if (read_write == I2C_SMBUS_WRITE) { 548 len = data->block[0]; 549 outb_p(len, SMBHSTDAT0(priv)); 550 for (i = 0; i < len; i++) 551 outb_p(data->block[i+1], SMBBLKDAT(priv)); 552 } 553 554 status = i801_transaction(priv, xact); 555 if (status) 556 return status; 557 558 if (read_write == I2C_SMBUS_READ || 559 command == I2C_SMBUS_BLOCK_PROC_CALL) { 560 len = inb_p(SMBHSTDAT0(priv)); 561 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 562 return -EPROTO; 563 564 data->block[0] = len; 565 for (i = 0; i < len; i++) 566 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 567 } 568 return 0; 569 } 570 571 static void i801_isr_byte_done(struct i801_priv *priv) 572 { 573 if (priv->is_read) { 574 /* For SMBus block reads, length is received with first byte */ 575 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 576 (priv->count == 0)) { 577 priv->len = inb_p(SMBHSTDAT0(priv)); 578 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 579 dev_err(&priv->pci_dev->dev, 580 "Illegal SMBus block read size %d\n", 581 priv->len); 582 /* FIXME: Recover */ 583 priv->len = I2C_SMBUS_BLOCK_MAX; 584 } else { 585 dev_dbg(&priv->pci_dev->dev, 586 "SMBus block read size is %d\n", 587 priv->len); 588 } 589 priv->data[-1] = priv->len; 590 } 591 592 /* Read next byte */ 593 if (priv->count < priv->len) 594 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 595 else 596 dev_dbg(&priv->pci_dev->dev, 597 "Discarding extra byte on block read\n"); 598 599 /* Set LAST_BYTE for last byte of read transaction */ 600 if (priv->count == priv->len - 1) 601 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 602 SMBHSTCNT(priv)); 603 } else if (priv->count < priv->len - 1) { 604 /* Write next byte, except for IRQ after last byte */ 605 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 606 } 607 608 /* Clear BYTE_DONE to continue with next byte */ 609 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 610 } 611 612 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 613 { 614 unsigned short addr; 615 616 addr = inb_p(SMBNTFDADD(priv)) >> 1; 617 618 /* 619 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 620 * always returns 0. Our current implementation doesn't provide 621 * data, so we just ignore it. 622 */ 623 i2c_handle_smbus_host_notify(&priv->adapter, addr); 624 625 /* clear Host Notify bit and return */ 626 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 627 return IRQ_HANDLED; 628 } 629 630 /* 631 * There are three kinds of interrupts: 632 * 633 * 1) i801 signals transaction completion with one of these interrupts: 634 * INTR - Success 635 * DEV_ERR - Invalid command, NAK or communication timeout 636 * BUS_ERR - SMI# transaction collision 637 * FAILED - transaction was canceled due to a KILL request 638 * When any of these occur, update ->status and wake up the waitq. 639 * ->status must be cleared before kicking off the next transaction. 640 * 641 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 642 * occurs for each byte of a byte-by-byte to prepare the next byte. 643 * 644 * 3) Host Notify interrupts 645 */ 646 static irqreturn_t i801_isr(int irq, void *dev_id) 647 { 648 struct i801_priv *priv = dev_id; 649 u16 pcists; 650 u8 status; 651 652 /* Confirm this is our interrupt */ 653 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 654 if (!(pcists & SMBPCISTS_INTS)) 655 return IRQ_NONE; 656 657 if (priv->features & FEATURE_HOST_NOTIFY) { 658 status = inb_p(SMBSLVSTS(priv)); 659 if (status & SMBSLVSTS_HST_NTFY_STS) 660 return i801_host_notify_isr(priv); 661 } 662 663 status = inb_p(SMBHSTSTS(priv)); 664 if (status & SMBHSTSTS_BYTE_DONE) 665 i801_isr_byte_done(priv); 666 667 /* 668 * Clear irq sources and report transaction result. 669 * ->status must be cleared before the next transaction is started. 670 */ 671 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 672 if (status) { 673 outb_p(status, SMBHSTSTS(priv)); 674 priv->status = status; 675 wake_up(&priv->waitq); 676 } 677 678 return IRQ_HANDLED; 679 } 680 681 /* 682 * For "byte-by-byte" block transactions: 683 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 684 * I2C read uses cmd=I801_I2C_BLOCK_DATA 685 */ 686 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 687 union i2c_smbus_data *data, 688 char read_write, int command, 689 int hwpec) 690 { 691 int i, len; 692 int smbcmd; 693 int status; 694 int result; 695 const struct i2c_adapter *adap = &priv->adapter; 696 697 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 698 return -EOPNOTSUPP; 699 700 result = i801_check_pre(priv); 701 if (result < 0) 702 return result; 703 704 len = data->block[0]; 705 706 if (read_write == I2C_SMBUS_WRITE) { 707 outb_p(len, SMBHSTDAT0(priv)); 708 outb_p(data->block[1], SMBBLKDAT(priv)); 709 } 710 711 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 712 read_write == I2C_SMBUS_READ) 713 smbcmd = I801_I2C_BLOCK_DATA; 714 else 715 smbcmd = I801_BLOCK_DATA; 716 717 if (priv->features & FEATURE_IRQ) { 718 priv->is_read = (read_write == I2C_SMBUS_READ); 719 if (len == 1 && priv->is_read) 720 smbcmd |= SMBHSTCNT_LAST_BYTE; 721 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 722 priv->len = len; 723 priv->count = 0; 724 priv->data = &data->block[1]; 725 726 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 727 result = wait_event_timeout(priv->waitq, 728 (status = priv->status), 729 adap->timeout); 730 if (!result) { 731 status = -ETIMEDOUT; 732 dev_warn(&priv->pci_dev->dev, 733 "Timeout waiting for interrupt!\n"); 734 } 735 priv->status = 0; 736 return i801_check_post(priv, status); 737 } 738 739 for (i = 1; i <= len; i++) { 740 if (i == len && read_write == I2C_SMBUS_READ) 741 smbcmd |= SMBHSTCNT_LAST_BYTE; 742 outb_p(smbcmd, SMBHSTCNT(priv)); 743 744 if (i == 1) 745 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, 746 SMBHSTCNT(priv)); 747 748 status = i801_wait_byte_done(priv); 749 if (status) 750 goto exit; 751 752 if (i == 1 && read_write == I2C_SMBUS_READ 753 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 754 len = inb_p(SMBHSTDAT0(priv)); 755 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 756 dev_err(&priv->pci_dev->dev, 757 "Illegal SMBus block read size %d\n", 758 len); 759 /* Recover */ 760 while (inb_p(SMBHSTSTS(priv)) & 761 SMBHSTSTS_HOST_BUSY) 762 outb_p(SMBHSTSTS_BYTE_DONE, 763 SMBHSTSTS(priv)); 764 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 765 return -EPROTO; 766 } 767 data->block[0] = len; 768 } 769 770 /* Retrieve/store value in SMBBLKDAT */ 771 if (read_write == I2C_SMBUS_READ) 772 data->block[i] = inb_p(SMBBLKDAT(priv)); 773 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 774 outb_p(data->block[i+1], SMBBLKDAT(priv)); 775 776 /* signals SMBBLKDAT ready */ 777 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 778 } 779 780 status = i801_wait_intr(priv); 781 exit: 782 return i801_check_post(priv, status); 783 } 784 785 static int i801_set_block_buffer_mode(struct i801_priv *priv) 786 { 787 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 788 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) 789 return -EIO; 790 return 0; 791 } 792 793 /* Block transaction function */ 794 static int i801_block_transaction(struct i801_priv *priv, 795 union i2c_smbus_data *data, char read_write, 796 int command, int hwpec) 797 { 798 int result = 0; 799 unsigned char hostc; 800 801 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 802 if (read_write == I2C_SMBUS_WRITE) { 803 /* set I2C_EN bit in configuration register */ 804 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 805 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 806 hostc | SMBHSTCFG_I2C_EN); 807 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 808 dev_err(&priv->pci_dev->dev, 809 "I2C block read is unsupported!\n"); 810 return -EOPNOTSUPP; 811 } 812 } 813 814 if (read_write == I2C_SMBUS_WRITE 815 || command == I2C_SMBUS_I2C_BLOCK_DATA) { 816 if (data->block[0] < 1) 817 data->block[0] = 1; 818 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 819 data->block[0] = I2C_SMBUS_BLOCK_MAX; 820 } else { 821 data->block[0] = 32; /* max for SMBus block reads */ 822 } 823 824 /* Experience has shown that the block buffer can only be used for 825 SMBus (not I2C) block transactions, even though the datasheet 826 doesn't mention this limitation. */ 827 if ((priv->features & FEATURE_BLOCK_BUFFER) 828 && command != I2C_SMBUS_I2C_BLOCK_DATA 829 && i801_set_block_buffer_mode(priv) == 0) 830 result = i801_block_transaction_by_block(priv, data, 831 read_write, 832 command, hwpec); 833 else 834 result = i801_block_transaction_byte_by_byte(priv, data, 835 read_write, 836 command, hwpec); 837 838 if (command == I2C_SMBUS_I2C_BLOCK_DATA 839 && read_write == I2C_SMBUS_WRITE) { 840 /* restore saved configuration register value */ 841 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 842 } 843 return result; 844 } 845 846 /* Return negative errno on error. */ 847 static s32 i801_access(struct i2c_adapter *adap, u16 addr, 848 unsigned short flags, char read_write, u8 command, 849 int size, union i2c_smbus_data *data) 850 { 851 int hwpec; 852 int block = 0; 853 int ret = 0, xact = 0; 854 struct i801_priv *priv = i2c_get_adapdata(adap); 855 856 mutex_lock(&priv->acpi_lock); 857 if (priv->acpi_reserved) { 858 mutex_unlock(&priv->acpi_lock); 859 return -EBUSY; 860 } 861 862 pm_runtime_get_sync(&priv->pci_dev->dev); 863 864 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 865 && size != I2C_SMBUS_QUICK 866 && size != I2C_SMBUS_I2C_BLOCK_DATA; 867 868 switch (size) { 869 case I2C_SMBUS_QUICK: 870 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 871 SMBHSTADD(priv)); 872 xact = I801_QUICK; 873 break; 874 case I2C_SMBUS_BYTE: 875 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 876 SMBHSTADD(priv)); 877 if (read_write == I2C_SMBUS_WRITE) 878 outb_p(command, SMBHSTCMD(priv)); 879 xact = I801_BYTE; 880 break; 881 case I2C_SMBUS_BYTE_DATA: 882 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 883 SMBHSTADD(priv)); 884 outb_p(command, SMBHSTCMD(priv)); 885 if (read_write == I2C_SMBUS_WRITE) 886 outb_p(data->byte, SMBHSTDAT0(priv)); 887 xact = I801_BYTE_DATA; 888 break; 889 case I2C_SMBUS_WORD_DATA: 890 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 891 SMBHSTADD(priv)); 892 outb_p(command, SMBHSTCMD(priv)); 893 if (read_write == I2C_SMBUS_WRITE) { 894 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 895 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 896 } 897 xact = I801_WORD_DATA; 898 break; 899 case I2C_SMBUS_BLOCK_DATA: 900 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 901 SMBHSTADD(priv)); 902 outb_p(command, SMBHSTCMD(priv)); 903 block = 1; 904 break; 905 case I2C_SMBUS_I2C_BLOCK_DATA: 906 /* 907 * NB: page 240 of ICH5 datasheet shows that the R/#W 908 * bit should be cleared here, even when reading. 909 * However if SPD Write Disable is set (Lynx Point and later), 910 * the read will fail if we don't set the R/#W bit. 911 */ 912 outb_p(((addr & 0x7f) << 1) | 913 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 914 (read_write & 0x01) : 0), 915 SMBHSTADD(priv)); 916 if (read_write == I2C_SMBUS_READ) { 917 /* NB: page 240 of ICH5 datasheet also shows 918 * that DATA1 is the cmd field when reading */ 919 outb_p(command, SMBHSTDAT1(priv)); 920 } else 921 outb_p(command, SMBHSTCMD(priv)); 922 block = 1; 923 break; 924 case I2C_SMBUS_BLOCK_PROC_CALL: 925 /* 926 * Bit 0 of the slave address register always indicate a write 927 * command. 928 */ 929 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 930 outb_p(command, SMBHSTCMD(priv)); 931 block = 1; 932 break; 933 default: 934 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 935 size); 936 ret = -EOPNOTSUPP; 937 goto out; 938 } 939 940 if (hwpec) /* enable/disable hardware PEC */ 941 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 942 else 943 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 944 SMBAUXCTL(priv)); 945 946 if (block) 947 ret = i801_block_transaction(priv, data, read_write, size, 948 hwpec); 949 else 950 ret = i801_transaction(priv, xact); 951 952 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 953 time, so we forcibly disable it after every transaction. Turn off 954 E32B for the same reason. */ 955 if (hwpec || block) 956 outb_p(inb_p(SMBAUXCTL(priv)) & 957 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 958 959 if (block) 960 goto out; 961 if (ret) 962 goto out; 963 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 964 goto out; 965 966 switch (xact & 0x7f) { 967 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 968 case I801_BYTE_DATA: 969 data->byte = inb_p(SMBHSTDAT0(priv)); 970 break; 971 case I801_WORD_DATA: 972 data->word = inb_p(SMBHSTDAT0(priv)) + 973 (inb_p(SMBHSTDAT1(priv)) << 8); 974 break; 975 } 976 977 out: 978 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 979 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 980 mutex_unlock(&priv->acpi_lock); 981 return ret; 982 } 983 984 985 static u32 i801_func(struct i2c_adapter *adapter) 986 { 987 struct i801_priv *priv = i2c_get_adapdata(adapter); 988 989 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 990 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 991 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 992 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 993 ((priv->features & FEATURE_BLOCK_PROC) ? 994 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 995 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 996 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 997 ((priv->features & FEATURE_HOST_NOTIFY) ? 998 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 999 } 1000 1001 static void i801_enable_host_notify(struct i2c_adapter *adapter) 1002 { 1003 struct i801_priv *priv = i2c_get_adapdata(adapter); 1004 1005 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1006 return; 1007 1008 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 1009 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 1010 SMBSLVCMD(priv)); 1011 1012 /* clear Host Notify bit to allow a new notification */ 1013 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 1014 } 1015 1016 static void i801_disable_host_notify(struct i801_priv *priv) 1017 { 1018 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1019 return; 1020 1021 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 1022 } 1023 1024 static const struct i2c_algorithm smbus_algorithm = { 1025 .smbus_xfer = i801_access, 1026 .functionality = i801_func, 1027 }; 1028 1029 static const struct pci_device_id i801_ids[] = { 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1075 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1076 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1077 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1078 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1079 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1080 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1081 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1082 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1083 { 0, } 1084 }; 1085 1086 MODULE_DEVICE_TABLE(pci, i801_ids); 1087 1088 #if defined CONFIG_X86 && defined CONFIG_DMI 1089 static unsigned char apanel_addr; 1090 1091 /* Scan the system ROM for the signature "FJKEYINF" */ 1092 static __init const void __iomem *bios_signature(const void __iomem *bios) 1093 { 1094 ssize_t offset; 1095 const unsigned char signature[] = "FJKEYINF"; 1096 1097 for (offset = 0; offset < 0x10000; offset += 0x10) { 1098 if (check_signature(bios + offset, signature, 1099 sizeof(signature)-1)) 1100 return bios + offset; 1101 } 1102 return NULL; 1103 } 1104 1105 static void __init input_apanel_init(void) 1106 { 1107 void __iomem *bios; 1108 const void __iomem *p; 1109 1110 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1111 p = bios_signature(bios); 1112 if (p) { 1113 /* just use the first address */ 1114 apanel_addr = readb(p + 8 + 3) >> 1; 1115 } 1116 iounmap(bios); 1117 } 1118 1119 struct dmi_onboard_device_info { 1120 const char *name; 1121 u8 type; 1122 unsigned short i2c_addr; 1123 const char *i2c_type; 1124 }; 1125 1126 static const struct dmi_onboard_device_info dmi_devices[] = { 1127 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1128 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1129 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1130 }; 1131 1132 static void dmi_check_onboard_device(u8 type, const char *name, 1133 struct i2c_adapter *adap) 1134 { 1135 int i; 1136 struct i2c_board_info info; 1137 1138 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1139 /* & ~0x80, ignore enabled/disabled bit */ 1140 if ((type & ~0x80) != dmi_devices[i].type) 1141 continue; 1142 if (strcasecmp(name, dmi_devices[i].name)) 1143 continue; 1144 1145 memset(&info, 0, sizeof(struct i2c_board_info)); 1146 info.addr = dmi_devices[i].i2c_addr; 1147 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1148 i2c_new_client_device(adap, &info); 1149 break; 1150 } 1151 } 1152 1153 /* We use our own function to check for onboard devices instead of 1154 dmi_find_device() as some buggy BIOS's have the devices we are interested 1155 in marked as disabled */ 1156 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1157 { 1158 int i, count; 1159 1160 if (dm->type != 10) 1161 return; 1162 1163 count = (dm->length - sizeof(struct dmi_header)) / 2; 1164 for (i = 0; i < count; i++) { 1165 const u8 *d = (char *)(dm + 1) + (i * 2); 1166 const char *name = ((char *) dm) + dm->length; 1167 u8 type = d[0]; 1168 u8 s = d[1]; 1169 1170 if (!s) 1171 continue; 1172 s--; 1173 while (s > 0 && name[0]) { 1174 name += strlen(name) + 1; 1175 s--; 1176 } 1177 if (name[0] == 0) /* Bogus string reference */ 1178 continue; 1179 1180 dmi_check_onboard_device(type, name, adap); 1181 } 1182 } 1183 1184 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1185 static const char *const acpi_smo8800_ids[] = { 1186 "SMO8800", 1187 "SMO8801", 1188 "SMO8810", 1189 "SMO8811", 1190 "SMO8820", 1191 "SMO8821", 1192 "SMO8830", 1193 "SMO8831", 1194 }; 1195 1196 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1197 u32 nesting_level, 1198 void *context, 1199 void **return_value) 1200 { 1201 struct acpi_device_info *info; 1202 acpi_status status; 1203 char *hid; 1204 int i; 1205 1206 status = acpi_get_object_info(obj_handle, &info); 1207 if (ACPI_FAILURE(status)) 1208 return AE_OK; 1209 1210 if (!(info->valid & ACPI_VALID_HID)) 1211 goto smo88xx_not_found; 1212 1213 hid = info->hardware_id.string; 1214 if (!hid) 1215 goto smo88xx_not_found; 1216 1217 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1218 if (i < 0) 1219 goto smo88xx_not_found; 1220 1221 kfree(info); 1222 1223 *((bool *)return_value) = true; 1224 return AE_CTRL_TERMINATE; 1225 1226 smo88xx_not_found: 1227 kfree(info); 1228 return AE_OK; 1229 } 1230 1231 static bool is_dell_system_with_lis3lv02d(void) 1232 { 1233 bool found; 1234 const char *vendor; 1235 1236 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1237 if (!vendor || strcmp(vendor, "Dell Inc.")) 1238 return false; 1239 1240 /* 1241 * Check that ACPI device SMO88xx is present and is functioning. 1242 * Function acpi_get_devices() already filters all ACPI devices 1243 * which are not present or are not functioning. 1244 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1245 * accelerometer but unfortunately ACPI does not provide any other 1246 * information (like I2C address). 1247 */ 1248 found = false; 1249 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1250 (void **)&found); 1251 1252 return found; 1253 } 1254 1255 /* 1256 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1257 * so it is needed to define mapping table based on DMI product names. 1258 */ 1259 static const struct { 1260 const char *dmi_product_name; 1261 unsigned short i2c_addr; 1262 } dell_lis3lv02d_devices[] = { 1263 /* 1264 * Dell platform team told us that these Latitude devices have 1265 * ST microelectronics accelerometer at I2C address 0x29. 1266 */ 1267 { "Latitude E5250", 0x29 }, 1268 { "Latitude E5450", 0x29 }, 1269 { "Latitude E5550", 0x29 }, 1270 { "Latitude E6440", 0x29 }, 1271 { "Latitude E6440 ATG", 0x29 }, 1272 { "Latitude E6540", 0x29 }, 1273 /* 1274 * Additional individual entries were added after verification. 1275 */ 1276 { "Vostro V131", 0x1d }, 1277 }; 1278 1279 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1280 { 1281 struct i2c_board_info info; 1282 const char *dmi_product_name; 1283 int i; 1284 1285 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1286 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1287 if (strcmp(dmi_product_name, 1288 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1289 break; 1290 } 1291 1292 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1293 dev_warn(&priv->pci_dev->dev, 1294 "Accelerometer lis3lv02d is present on SMBus but its" 1295 " address is unknown, skipping registration\n"); 1296 return; 1297 } 1298 1299 memset(&info, 0, sizeof(struct i2c_board_info)); 1300 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1301 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1302 i2c_new_client_device(&priv->adapter, &info); 1303 } 1304 1305 /* Register optional slaves */ 1306 static void i801_probe_optional_slaves(struct i801_priv *priv) 1307 { 1308 /* Only register slaves on main SMBus channel */ 1309 if (priv->features & FEATURE_IDF) 1310 return; 1311 1312 if (apanel_addr) { 1313 struct i2c_board_info info; 1314 1315 memset(&info, 0, sizeof(struct i2c_board_info)); 1316 info.addr = apanel_addr; 1317 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1318 i2c_new_client_device(&priv->adapter, &info); 1319 } 1320 1321 if (dmi_name_in_vendors("FUJITSU")) 1322 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1323 1324 if (is_dell_system_with_lis3lv02d()) 1325 register_dell_lis3lv02d_i2c_device(priv); 1326 } 1327 #else 1328 static void __init input_apanel_init(void) {} 1329 static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1330 #endif /* CONFIG_X86 && CONFIG_DMI */ 1331 1332 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1333 static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1334 .gpio_chip = "gpio_ich", 1335 .values = { 0x02, 0x03 }, 1336 .n_values = 2, 1337 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1338 .gpios = { 52, 53 }, 1339 .n_gpios = 2, 1340 }; 1341 1342 static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1343 .gpio_chip = "gpio_ich", 1344 .values = { 0x02, 0x03, 0x01 }, 1345 .n_values = 3, 1346 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1347 .gpios = { 52, 53 }, 1348 .n_gpios = 2, 1349 }; 1350 1351 static const struct dmi_system_id mux_dmi_table[] = { 1352 { 1353 .matches = { 1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1355 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1356 }, 1357 .driver_data = &i801_mux_config_asus_z8_d12, 1358 }, 1359 { 1360 .matches = { 1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1362 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1363 }, 1364 .driver_data = &i801_mux_config_asus_z8_d12, 1365 }, 1366 { 1367 .matches = { 1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1369 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1370 }, 1371 .driver_data = &i801_mux_config_asus_z8_d12, 1372 }, 1373 { 1374 .matches = { 1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1377 }, 1378 .driver_data = &i801_mux_config_asus_z8_d12, 1379 }, 1380 { 1381 .matches = { 1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1383 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1384 }, 1385 .driver_data = &i801_mux_config_asus_z8_d12, 1386 }, 1387 { 1388 .matches = { 1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1390 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1391 }, 1392 .driver_data = &i801_mux_config_asus_z8_d12, 1393 }, 1394 { 1395 .matches = { 1396 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1397 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1398 }, 1399 .driver_data = &i801_mux_config_asus_z8_d18, 1400 }, 1401 { 1402 .matches = { 1403 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1404 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1405 }, 1406 .driver_data = &i801_mux_config_asus_z8_d18, 1407 }, 1408 { 1409 .matches = { 1410 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1411 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1412 }, 1413 .driver_data = &i801_mux_config_asus_z8_d12, 1414 }, 1415 { } 1416 }; 1417 1418 /* Setup multiplexing if needed */ 1419 static int i801_add_mux(struct i801_priv *priv) 1420 { 1421 struct device *dev = &priv->adapter.dev; 1422 const struct i801_mux_config *mux_config; 1423 struct i2c_mux_gpio_platform_data gpio_data; 1424 struct gpiod_lookup_table *lookup; 1425 int err, i; 1426 1427 if (!priv->mux_drvdata) 1428 return 0; 1429 mux_config = priv->mux_drvdata; 1430 1431 /* Prepare the platform data */ 1432 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1433 gpio_data.parent = priv->adapter.nr; 1434 gpio_data.values = mux_config->values; 1435 gpio_data.n_values = mux_config->n_values; 1436 gpio_data.classes = mux_config->classes; 1437 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1438 1439 /* Register GPIO descriptor lookup table */ 1440 lookup = devm_kzalloc(dev, 1441 struct_size(lookup, table, mux_config->n_gpios), 1442 GFP_KERNEL); 1443 if (!lookup) 1444 return -ENOMEM; 1445 lookup->dev_id = "i2c-mux-gpio"; 1446 for (i = 0; i < mux_config->n_gpios; i++) { 1447 lookup->table[i].chip_label = mux_config->gpio_chip; 1448 lookup->table[i].chip_hwnum = mux_config->gpios[i]; 1449 lookup->table[i].con_id = "mux"; 1450 } 1451 gpiod_add_lookup_table(lookup); 1452 priv->lookup = lookup; 1453 1454 /* 1455 * Register the mux device, we use PLATFORM_DEVID_NONE here 1456 * because since we are referring to the GPIO chip by name we are 1457 * anyways in deep trouble if there is more than one of these 1458 * devices, and there should likely only be one platform controller 1459 * hub. 1460 */ 1461 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1462 PLATFORM_DEVID_NONE, &gpio_data, 1463 sizeof(struct i2c_mux_gpio_platform_data)); 1464 if (IS_ERR(priv->mux_pdev)) { 1465 err = PTR_ERR(priv->mux_pdev); 1466 gpiod_remove_lookup_table(lookup); 1467 priv->mux_pdev = NULL; 1468 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1469 return err; 1470 } 1471 1472 return 0; 1473 } 1474 1475 static void i801_del_mux(struct i801_priv *priv) 1476 { 1477 if (priv->mux_pdev) 1478 platform_device_unregister(priv->mux_pdev); 1479 if (priv->lookup) 1480 gpiod_remove_lookup_table(priv->lookup); 1481 } 1482 1483 static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1484 { 1485 const struct dmi_system_id *id; 1486 const struct i801_mux_config *mux_config; 1487 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1488 int i; 1489 1490 id = dmi_first_match(mux_dmi_table); 1491 if (id) { 1492 /* Remove branch classes from trunk */ 1493 mux_config = id->driver_data; 1494 for (i = 0; i < mux_config->n_values; i++) 1495 class &= ~mux_config->classes[i]; 1496 1497 /* Remember for later */ 1498 priv->mux_drvdata = mux_config; 1499 } 1500 1501 return class; 1502 } 1503 #else 1504 static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1505 static inline void i801_del_mux(struct i801_priv *priv) { } 1506 1507 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1508 { 1509 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1510 } 1511 #endif 1512 1513 static const struct itco_wdt_platform_data spt_tco_platform_data = { 1514 .name = "Intel PCH", 1515 .version = 4, 1516 }; 1517 1518 static DEFINE_SPINLOCK(p2sb_spinlock); 1519 1520 static struct platform_device * 1521 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1522 struct resource *tco_res) 1523 { 1524 struct resource *res; 1525 unsigned int devfn; 1526 u64 base64_addr; 1527 u32 base_addr; 1528 u8 hidden; 1529 1530 /* 1531 * We must access the NO_REBOOT bit over the Primary to Sideband 1532 * bridge (P2SB). The BIOS prevents the P2SB device from being 1533 * enumerated by the PCI subsystem, so we need to unhide/hide it 1534 * to lookup the P2SB BAR. 1535 */ 1536 spin_lock(&p2sb_spinlock); 1537 1538 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1539 1540 /* Unhide the P2SB device, if it is hidden */ 1541 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1542 if (hidden) 1543 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1544 1545 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1546 base64_addr = base_addr & 0xfffffff0; 1547 1548 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1549 base64_addr |= (u64)base_addr << 32; 1550 1551 /* Hide the P2SB device, if it was hidden before */ 1552 if (hidden) 1553 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1554 spin_unlock(&p2sb_spinlock); 1555 1556 res = &tco_res[ICH_RES_MEM_OFF]; 1557 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1558 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1559 else 1560 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1561 1562 res->end = res->start + 3; 1563 res->flags = IORESOURCE_MEM; 1564 1565 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1566 tco_res, 3, &spt_tco_platform_data, 1567 sizeof(spt_tco_platform_data)); 1568 } 1569 1570 static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1571 .name = "Intel PCH", 1572 .version = 6, 1573 }; 1574 1575 static struct platform_device * 1576 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1577 struct resource *tco_res) 1578 { 1579 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1580 tco_res, 2, &cnl_tco_platform_data, 1581 sizeof(cnl_tco_platform_data)); 1582 } 1583 1584 static void i801_add_tco(struct i801_priv *priv) 1585 { 1586 u32 base_addr, tco_base, tco_ctl, ctrl_val; 1587 struct pci_dev *pci_dev = priv->pci_dev; 1588 struct resource tco_res[3], *res; 1589 unsigned int devfn; 1590 1591 /* If we have ACPI based watchdog use that instead */ 1592 if (acpi_has_watchdog()) 1593 return; 1594 1595 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1596 return; 1597 1598 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1599 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1600 if (!(tco_ctl & TCOCTL_EN)) 1601 return; 1602 1603 memset(tco_res, 0, sizeof(tco_res)); 1604 1605 res = &tco_res[ICH_RES_IO_TCO]; 1606 res->start = tco_base & ~1; 1607 res->end = res->start + 32 - 1; 1608 res->flags = IORESOURCE_IO; 1609 1610 /* 1611 * Power Management registers. 1612 */ 1613 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2); 1614 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr); 1615 1616 res = &tco_res[ICH_RES_IO_SMI]; 1617 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF; 1618 res->end = res->start + 3; 1619 res->flags = IORESOURCE_IO; 1620 1621 /* 1622 * Enable the ACPI I/O space. 1623 */ 1624 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val); 1625 ctrl_val |= ACPICTRL_EN; 1626 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val); 1627 1628 if (priv->features & FEATURE_TCO_CNL) 1629 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1630 else 1631 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1632 1633 if (IS_ERR(priv->tco_pdev)) 1634 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1635 } 1636 1637 #ifdef CONFIG_ACPI 1638 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1639 acpi_physical_address address) 1640 { 1641 return address >= priv->smba && 1642 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1643 } 1644 1645 static acpi_status 1646 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1647 u64 *value, void *handler_context, void *region_context) 1648 { 1649 struct i801_priv *priv = handler_context; 1650 struct pci_dev *pdev = priv->pci_dev; 1651 acpi_status status; 1652 1653 /* 1654 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1655 * further access from the driver itself. This device is now owned 1656 * by the system firmware. 1657 */ 1658 mutex_lock(&priv->acpi_lock); 1659 1660 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1661 priv->acpi_reserved = true; 1662 1663 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1664 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1665 1666 /* 1667 * BIOS is accessing the host controller so prevent it from 1668 * suspending automatically from now on. 1669 */ 1670 pm_runtime_get_sync(&pdev->dev); 1671 } 1672 1673 if ((function & ACPI_IO_MASK) == ACPI_READ) 1674 status = acpi_os_read_port(address, (u32 *)value, bits); 1675 else 1676 status = acpi_os_write_port(address, (u32)*value, bits); 1677 1678 mutex_unlock(&priv->acpi_lock); 1679 1680 return status; 1681 } 1682 1683 static int i801_acpi_probe(struct i801_priv *priv) 1684 { 1685 struct acpi_device *adev; 1686 acpi_status status; 1687 1688 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1689 if (adev) { 1690 status = acpi_install_address_space_handler(adev->handle, 1691 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1692 NULL, priv); 1693 if (ACPI_SUCCESS(status)) 1694 return 0; 1695 } 1696 1697 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1698 } 1699 1700 static void i801_acpi_remove(struct i801_priv *priv) 1701 { 1702 struct acpi_device *adev; 1703 1704 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1705 if (!adev) 1706 return; 1707 1708 acpi_remove_address_space_handler(adev->handle, 1709 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1710 1711 mutex_lock(&priv->acpi_lock); 1712 if (priv->acpi_reserved) 1713 pm_runtime_put(&priv->pci_dev->dev); 1714 mutex_unlock(&priv->acpi_lock); 1715 } 1716 #else 1717 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1718 static inline void i801_acpi_remove(struct i801_priv *priv) { } 1719 #endif 1720 1721 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1722 { 1723 unsigned char temp; 1724 int err, i; 1725 struct i801_priv *priv; 1726 1727 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1728 if (!priv) 1729 return -ENOMEM; 1730 1731 i2c_set_adapdata(&priv->adapter, priv); 1732 priv->adapter.owner = THIS_MODULE; 1733 priv->adapter.class = i801_get_adapter_class(priv); 1734 priv->adapter.algo = &smbus_algorithm; 1735 priv->adapter.dev.parent = &dev->dev; 1736 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1737 priv->adapter.retries = 3; 1738 mutex_init(&priv->acpi_lock); 1739 1740 priv->pci_dev = dev; 1741 switch (dev->device) { 1742 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1743 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1744 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1745 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1746 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1747 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1748 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1749 priv->features |= FEATURE_BLOCK_PROC; 1750 priv->features |= FEATURE_I2C_BLOCK_READ; 1751 priv->features |= FEATURE_IRQ; 1752 priv->features |= FEATURE_SMBUS_PEC; 1753 priv->features |= FEATURE_BLOCK_BUFFER; 1754 priv->features |= FEATURE_TCO_SPT; 1755 priv->features |= FEATURE_HOST_NOTIFY; 1756 break; 1757 1758 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1759 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1760 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1761 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1762 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1763 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1764 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1765 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1766 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1767 priv->features |= FEATURE_BLOCK_PROC; 1768 priv->features |= FEATURE_I2C_BLOCK_READ; 1769 priv->features |= FEATURE_IRQ; 1770 priv->features |= FEATURE_SMBUS_PEC; 1771 priv->features |= FEATURE_BLOCK_BUFFER; 1772 priv->features |= FEATURE_TCO_CNL; 1773 priv->features |= FEATURE_HOST_NOTIFY; 1774 break; 1775 1776 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1777 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1778 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1779 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1780 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1781 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1782 priv->features |= FEATURE_IDF; 1783 /* fall through */ 1784 default: 1785 priv->features |= FEATURE_BLOCK_PROC; 1786 priv->features |= FEATURE_I2C_BLOCK_READ; 1787 priv->features |= FEATURE_IRQ; 1788 /* fall through */ 1789 case PCI_DEVICE_ID_INTEL_82801DB_3: 1790 priv->features |= FEATURE_SMBUS_PEC; 1791 priv->features |= FEATURE_BLOCK_BUFFER; 1792 /* fall through */ 1793 case PCI_DEVICE_ID_INTEL_82801CA_3: 1794 priv->features |= FEATURE_HOST_NOTIFY; 1795 /* fall through */ 1796 case PCI_DEVICE_ID_INTEL_82801BA_2: 1797 case PCI_DEVICE_ID_INTEL_82801AB_3: 1798 case PCI_DEVICE_ID_INTEL_82801AA_3: 1799 break; 1800 } 1801 1802 /* Disable features on user request */ 1803 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1804 if (priv->features & disable_features & (1 << i)) 1805 dev_notice(&dev->dev, "%s disabled by user\n", 1806 i801_feature_names[i]); 1807 } 1808 priv->features &= ~disable_features; 1809 1810 err = pcim_enable_device(dev); 1811 if (err) { 1812 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1813 err); 1814 return err; 1815 } 1816 pcim_pin_device(dev); 1817 1818 /* Determine the address of the SMBus area */ 1819 priv->smba = pci_resource_start(dev, SMBBAR); 1820 if (!priv->smba) { 1821 dev_err(&dev->dev, 1822 "SMBus base address uninitialized, upgrade BIOS\n"); 1823 return -ENODEV; 1824 } 1825 1826 if (i801_acpi_probe(priv)) 1827 return -ENODEV; 1828 1829 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1830 dev_driver_string(&dev->dev)); 1831 if (err) { 1832 dev_err(&dev->dev, 1833 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1834 priv->smba, 1835 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1836 i801_acpi_remove(priv); 1837 return err; 1838 } 1839 1840 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); 1841 priv->original_hstcfg = temp; 1842 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1843 if (!(temp & SMBHSTCFG_HST_EN)) { 1844 dev_info(&dev->dev, "Enabling SMBus device\n"); 1845 temp |= SMBHSTCFG_HST_EN; 1846 } 1847 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); 1848 1849 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1850 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1851 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1852 priv->features &= ~FEATURE_IRQ; 1853 } 1854 if (temp & SMBHSTCFG_SPD_WD) 1855 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1856 1857 /* Clear special mode bits */ 1858 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1859 outb_p(inb_p(SMBAUXCTL(priv)) & 1860 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1861 1862 /* Remember original Host Notify setting */ 1863 if (priv->features & FEATURE_HOST_NOTIFY) 1864 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1865 1866 /* Default timeout in interrupt mode: 200 ms */ 1867 priv->adapter.timeout = HZ / 5; 1868 1869 if (dev->irq == IRQ_NOTCONNECTED) 1870 priv->features &= ~FEATURE_IRQ; 1871 1872 if (priv->features & FEATURE_IRQ) { 1873 u16 pcictl, pcists; 1874 1875 /* Complain if an interrupt is already pending */ 1876 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1877 if (pcists & SMBPCISTS_INTS) 1878 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1879 1880 /* Check if interrupts have been disabled */ 1881 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1882 if (pcictl & SMBPCICTL_INTDIS) { 1883 dev_info(&dev->dev, "Interrupts are disabled\n"); 1884 priv->features &= ~FEATURE_IRQ; 1885 } 1886 } 1887 1888 if (priv->features & FEATURE_IRQ) { 1889 init_waitqueue_head(&priv->waitq); 1890 1891 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1892 IRQF_SHARED, 1893 dev_driver_string(&dev->dev), priv); 1894 if (err) { 1895 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1896 dev->irq, err); 1897 priv->features &= ~FEATURE_IRQ; 1898 } 1899 } 1900 dev_info(&dev->dev, "SMBus using %s\n", 1901 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1902 1903 i801_add_tco(priv); 1904 1905 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1906 "SMBus I801 adapter at %04lx", priv->smba); 1907 err = i2c_add_adapter(&priv->adapter); 1908 if (err) { 1909 i801_acpi_remove(priv); 1910 return err; 1911 } 1912 1913 i801_enable_host_notify(&priv->adapter); 1914 1915 i801_probe_optional_slaves(priv); 1916 /* We ignore errors - multiplexing is optional */ 1917 i801_add_mux(priv); 1918 1919 pci_set_drvdata(dev, priv); 1920 1921 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1922 pm_runtime_use_autosuspend(&dev->dev); 1923 pm_runtime_put_autosuspend(&dev->dev); 1924 pm_runtime_allow(&dev->dev); 1925 1926 return 0; 1927 } 1928 1929 static void i801_remove(struct pci_dev *dev) 1930 { 1931 struct i801_priv *priv = pci_get_drvdata(dev); 1932 1933 pm_runtime_forbid(&dev->dev); 1934 pm_runtime_get_noresume(&dev->dev); 1935 1936 i801_disable_host_notify(priv); 1937 i801_del_mux(priv); 1938 i2c_del_adapter(&priv->adapter); 1939 i801_acpi_remove(priv); 1940 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1941 1942 platform_device_unregister(priv->tco_pdev); 1943 1944 /* 1945 * do not call pci_disable_device(dev) since it can cause hard hangs on 1946 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1947 */ 1948 } 1949 1950 static void i801_shutdown(struct pci_dev *dev) 1951 { 1952 struct i801_priv *priv = pci_get_drvdata(dev); 1953 1954 /* Restore config registers to avoid hard hang on some systems */ 1955 i801_disable_host_notify(priv); 1956 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1957 } 1958 1959 #ifdef CONFIG_PM_SLEEP 1960 static int i801_suspend(struct device *dev) 1961 { 1962 struct pci_dev *pci_dev = to_pci_dev(dev); 1963 struct i801_priv *priv = pci_get_drvdata(pci_dev); 1964 1965 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg); 1966 return 0; 1967 } 1968 1969 static int i801_resume(struct device *dev) 1970 { 1971 struct i801_priv *priv = dev_get_drvdata(dev); 1972 1973 i801_enable_host_notify(&priv->adapter); 1974 1975 return 0; 1976 } 1977 #endif 1978 1979 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1980 1981 static struct pci_driver i801_driver = { 1982 .name = "i801_smbus", 1983 .id_table = i801_ids, 1984 .probe = i801_probe, 1985 .remove = i801_remove, 1986 .shutdown = i801_shutdown, 1987 .driver = { 1988 .pm = &i801_pm_ops, 1989 }, 1990 }; 1991 1992 static int __init i2c_i801_init(void) 1993 { 1994 if (dmi_name_in_vendors("FUJITSU")) 1995 input_apanel_init(); 1996 return pci_register_driver(&i801_driver); 1997 } 1998 1999 static void __exit i2c_i801_exit(void) 2000 { 2001 pci_unregister_driver(&i801_driver); 2002 } 2003 2004 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>"); 2005 MODULE_DESCRIPTION("I801 SMBus driver"); 2006 MODULE_LICENSE("GPL"); 2007 2008 module_init(i2c_i801_init); 2009 module_exit(i2c_i801_exit); 2010