1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 * 8 * Inspired from: fsl-imx25-tsadc 9 * 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/interrupt.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdesc.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 25 #include "stm32-adc-core.h" 26 27 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 28 29 /* SYSCFG registers */ 30 #define STM32MP1_SYSCFG_PMCSETR 0x04 31 #define STM32MP1_SYSCFG_PMCCLRR 0x44 32 33 /* SYSCFG bit fields */ 34 #define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9) 35 36 /* SYSCFG capability flags */ 37 #define HAS_VBOOSTER BIT(0) 38 #define HAS_ANASWVDD BIT(1) 39 40 /** 41 * stm32_adc_common_regs - stm32 common registers, compatible dependent data 42 * @csr: common status register offset 43 * @ccr: common control register offset 44 * @eoc1: adc1 end of conversion flag in @csr 45 * @eoc2: adc2 end of conversion flag in @csr 46 * @eoc3: adc3 end of conversion flag in @csr 47 * @ier: interrupt enable register offset for each adc 48 * @eocie_msk: end of conversion interrupt enable mask in @ier 49 */ 50 struct stm32_adc_common_regs { 51 u32 csr; 52 u32 ccr; 53 u32 eoc1_msk; 54 u32 eoc2_msk; 55 u32 eoc3_msk; 56 u32 ier; 57 u32 eocie_msk; 58 }; 59 60 struct stm32_adc_priv; 61 62 /** 63 * stm32_adc_priv_cfg - stm32 core compatible configuration data 64 * @regs: common registers for all instances 65 * @clk_sel: clock selection routine 66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) 67 * @has_syscfg: SYSCFG capability flags 68 */ 69 struct stm32_adc_priv_cfg { 70 const struct stm32_adc_common_regs *regs; 71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); 72 u32 max_clk_rate_hz; 73 unsigned int has_syscfg; 74 }; 75 76 /** 77 * struct stm32_adc_priv - stm32 ADC core private data 78 * @irq: irq(s) for ADC block 79 * @domain: irq domain reference 80 * @aclk: clock reference for the analog circuitry 81 * @bclk: bus clock common for all ADCs, depends on part used 82 * @booster: booster supply reference 83 * @vdd: vdd supply reference 84 * @vdda: vdda analog supply reference 85 * @vref: regulator reference 86 * @vdd_uv: vdd supply voltage (microvolts) 87 * @vdda_uv: vdda supply voltage (microvolts) 88 * @cfg: compatible configuration data 89 * @common: common data for all ADC instances 90 * @ccr_bak: backup CCR in low power mode 91 * @syscfg: reference to syscon, system control registers 92 */ 93 struct stm32_adc_priv { 94 int irq[STM32_ADC_MAX_ADCS]; 95 struct irq_domain *domain; 96 struct clk *aclk; 97 struct clk *bclk; 98 struct regulator *booster; 99 struct regulator *vdd; 100 struct regulator *vdda; 101 struct regulator *vref; 102 int vdd_uv; 103 int vdda_uv; 104 const struct stm32_adc_priv_cfg *cfg; 105 struct stm32_adc_common common; 106 u32 ccr_bak; 107 struct regmap *syscfg; 108 }; 109 110 static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com) 111 { 112 return container_of(com, struct stm32_adc_priv, common); 113 } 114 115 /* STM32F4 ADC internal common clock prescaler division ratios */ 116 static int stm32f4_pclk_div[] = {2, 4, 6, 8}; 117 118 /** 119 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler 120 * @priv: stm32 ADC core private data 121 * Select clock prescaler used for analog conversions, before using ADC. 122 */ 123 static int stm32f4_adc_clk_sel(struct platform_device *pdev, 124 struct stm32_adc_priv *priv) 125 { 126 unsigned long rate; 127 u32 val; 128 int i; 129 130 /* stm32f4 has one clk input for analog (mandatory), enforce it here */ 131 if (!priv->aclk) { 132 dev_err(&pdev->dev, "No 'adc' clock found\n"); 133 return -ENOENT; 134 } 135 136 rate = clk_get_rate(priv->aclk); 137 if (!rate) { 138 dev_err(&pdev->dev, "Invalid clock rate: 0\n"); 139 return -EINVAL; 140 } 141 142 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { 143 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz) 144 break; 145 } 146 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { 147 dev_err(&pdev->dev, "adc clk selection failed\n"); 148 return -EINVAL; 149 } 150 151 priv->common.rate = rate / stm32f4_pclk_div[i]; 152 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); 153 val &= ~STM32F4_ADC_ADCPRE_MASK; 154 val |= i << STM32F4_ADC_ADCPRE_SHIFT; 155 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR); 156 157 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n", 158 priv->common.rate / 1000); 159 160 return 0; 161 } 162 163 /** 164 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock 165 * @ckmode: ADC clock mode, Async or sync with prescaler. 166 * @presc: prescaler bitfield for async clock mode 167 * @div: prescaler division ratio 168 */ 169 struct stm32h7_adc_ck_spec { 170 u32 ckmode; 171 u32 presc; 172 int div; 173 }; 174 175 static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { 176 /* 00: CK_ADC[1..3]: Asynchronous clock modes */ 177 { 0, 0, 1 }, 178 { 0, 1, 2 }, 179 { 0, 2, 4 }, 180 { 0, 3, 6 }, 181 { 0, 4, 8 }, 182 { 0, 5, 10 }, 183 { 0, 6, 12 }, 184 { 0, 7, 16 }, 185 { 0, 8, 32 }, 186 { 0, 9, 64 }, 187 { 0, 10, 128 }, 188 { 0, 11, 256 }, 189 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ 190 { 1, 0, 1 }, 191 { 2, 0, 2 }, 192 { 3, 0, 4 }, 193 }; 194 195 static int stm32h7_adc_clk_sel(struct platform_device *pdev, 196 struct stm32_adc_priv *priv) 197 { 198 u32 ckmode, presc, val; 199 unsigned long rate; 200 int i, div; 201 202 /* stm32h7 bus clock is common for all ADC instances (mandatory) */ 203 if (!priv->bclk) { 204 dev_err(&pdev->dev, "No 'bus' clock found\n"); 205 return -ENOENT; 206 } 207 208 /* 209 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. 210 * So, choice is to have bus clock mandatory and adc clock optional. 211 * If optional 'adc' clock has been found, then try to use it first. 212 */ 213 if (priv->aclk) { 214 /* 215 * Asynchronous clock modes (e.g. ckmode == 0) 216 * From spec: PLL output musn't exceed max rate 217 */ 218 rate = clk_get_rate(priv->aclk); 219 if (!rate) { 220 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n"); 221 return -EINVAL; 222 } 223 224 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 225 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 226 presc = stm32h7_adc_ckmodes_spec[i].presc; 227 div = stm32h7_adc_ckmodes_spec[i].div; 228 229 if (ckmode) 230 continue; 231 232 if ((rate / div) <= priv->cfg->max_clk_rate_hz) 233 goto out; 234 } 235 } 236 237 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ 238 rate = clk_get_rate(priv->bclk); 239 if (!rate) { 240 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n"); 241 return -EINVAL; 242 } 243 244 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { 245 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; 246 presc = stm32h7_adc_ckmodes_spec[i].presc; 247 div = stm32h7_adc_ckmodes_spec[i].div; 248 249 if (!ckmode) 250 continue; 251 252 if ((rate / div) <= priv->cfg->max_clk_rate_hz) 253 goto out; 254 } 255 256 dev_err(&pdev->dev, "adc clk selection failed\n"); 257 return -EINVAL; 258 259 out: 260 /* rate used later by each ADC instance to control BOOST mode */ 261 priv->common.rate = rate / div; 262 263 /* Set common clock mode and prescaler */ 264 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); 265 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); 266 val |= ckmode << STM32H7_CKMODE_SHIFT; 267 val |= presc << STM32H7_PRESC_SHIFT; 268 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); 269 270 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", 271 ckmode ? "bus" : "adc", div, priv->common.rate / 1000); 272 273 return 0; 274 } 275 276 /* STM32F4 common registers definitions */ 277 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 278 .csr = STM32F4_ADC_CSR, 279 .ccr = STM32F4_ADC_CCR, 280 .eoc1_msk = STM32F4_EOC1, 281 .eoc2_msk = STM32F4_EOC2, 282 .eoc3_msk = STM32F4_EOC3, 283 .ier = STM32F4_ADC_CR1, 284 .eocie_msk = STM32F4_EOCIE, 285 }; 286 287 /* STM32H7 common registers definitions */ 288 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 289 .csr = STM32H7_ADC_CSR, 290 .ccr = STM32H7_ADC_CCR, 291 .eoc1_msk = STM32H7_EOC_MST, 292 .eoc2_msk = STM32H7_EOC_SLV, 293 .ier = STM32H7_ADC_IER, 294 .eocie_msk = STM32H7_EOCIE, 295 }; 296 297 static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { 298 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, 299 }; 300 301 static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, 302 unsigned int adc) 303 { 304 u32 ier, offset = stm32_adc_offset[adc]; 305 306 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); 307 308 return ier & priv->cfg->regs->eocie_msk; 309 } 310 311 /* ADC common interrupt for all instances */ 312 static void stm32_adc_irq_handler(struct irq_desc *desc) 313 { 314 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc); 315 struct irq_chip *chip = irq_desc_get_chip(desc); 316 u32 status; 317 318 chained_irq_enter(chip, desc); 319 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); 320 321 /* 322 * End of conversion may be handled by using IRQ or DMA. There may be a 323 * race here when two conversions complete at the same time on several 324 * ADCs. EOC may be read 'set' for several ADCs, with: 325 * - an ADC configured to use DMA (EOC triggers the DMA request, and 326 * is then automatically cleared by DR read in hardware) 327 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must 328 * be called in this case) 329 * So both EOC status bit in CSR and EOCIE control bit must be checked 330 * before invoking the interrupt handler (e.g. call ISR only for 331 * IRQ-enabled ADCs). 332 */ 333 if (status & priv->cfg->regs->eoc1_msk && 334 stm32_adc_eoc_enabled(priv, 0)) 335 generic_handle_irq(irq_find_mapping(priv->domain, 0)); 336 337 if (status & priv->cfg->regs->eoc2_msk && 338 stm32_adc_eoc_enabled(priv, 1)) 339 generic_handle_irq(irq_find_mapping(priv->domain, 1)); 340 341 if (status & priv->cfg->regs->eoc3_msk && 342 stm32_adc_eoc_enabled(priv, 2)) 343 generic_handle_irq(irq_find_mapping(priv->domain, 2)); 344 345 chained_irq_exit(chip, desc); 346 }; 347 348 static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq, 349 irq_hw_number_t hwirq) 350 { 351 irq_set_chip_data(irq, d->host_data); 352 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq); 353 354 return 0; 355 } 356 357 static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq) 358 { 359 irq_set_chip_and_handler(irq, NULL, NULL); 360 irq_set_chip_data(irq, NULL); 361 } 362 363 static const struct irq_domain_ops stm32_adc_domain_ops = { 364 .map = stm32_adc_domain_map, 365 .unmap = stm32_adc_domain_unmap, 366 .xlate = irq_domain_xlate_onecell, 367 }; 368 369 static int stm32_adc_irq_probe(struct platform_device *pdev, 370 struct stm32_adc_priv *priv) 371 { 372 struct device_node *np = pdev->dev.of_node; 373 unsigned int i; 374 375 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 376 priv->irq[i] = platform_get_irq(pdev, i); 377 if (priv->irq[i] < 0) { 378 /* 379 * At least one interrupt must be provided, make others 380 * optional: 381 * - stm32f4/h7 shares a common interrupt. 382 * - stm32mp1, has one line per ADC (either for ADC1, 383 * ADC2 or both). 384 */ 385 if (i && priv->irq[i] == -ENXIO) 386 continue; 387 388 return priv->irq[i]; 389 } 390 } 391 392 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0, 393 &stm32_adc_domain_ops, 394 priv); 395 if (!priv->domain) { 396 dev_err(&pdev->dev, "Failed to add irq domain\n"); 397 return -ENOMEM; 398 } 399 400 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 401 if (priv->irq[i] < 0) 402 continue; 403 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler); 404 irq_set_handler_data(priv->irq[i], priv); 405 } 406 407 return 0; 408 } 409 410 static void stm32_adc_irq_remove(struct platform_device *pdev, 411 struct stm32_adc_priv *priv) 412 { 413 int hwirq; 414 unsigned int i; 415 416 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++) 417 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq)); 418 irq_domain_remove(priv->domain); 419 420 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) { 421 if (priv->irq[i] < 0) 422 continue; 423 irq_set_chained_handler(priv->irq[i], NULL); 424 } 425 } 426 427 static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv, 428 struct device *dev) 429 { 430 int ret; 431 432 /* 433 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog 434 * switches (via PCSEL) which have reduced performances when their 435 * supply is below 2.7V (vdda by default): 436 * - Voltage booster can be used, to get full ADC performances 437 * (increases power consumption). 438 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only). 439 * 440 * Recommended settings for ANASWVDD and EN_BOOSTER: 441 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1) 442 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1 443 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default) 444 */ 445 if (priv->vdda_uv < 2700000) { 446 if (priv->syscfg && priv->vdd_uv > 2700000) { 447 ret = regulator_enable(priv->vdd); 448 if (ret < 0) { 449 dev_err(dev, "vdd enable failed %d\n", ret); 450 return ret; 451 } 452 453 ret = regmap_write(priv->syscfg, 454 STM32MP1_SYSCFG_PMCSETR, 455 STM32MP1_SYSCFG_ANASWVDD_MASK); 456 if (ret < 0) { 457 regulator_disable(priv->vdd); 458 dev_err(dev, "vdd select failed, %d\n", ret); 459 return ret; 460 } 461 dev_dbg(dev, "analog switches supplied by vdd\n"); 462 463 return 0; 464 } 465 466 if (priv->booster) { 467 /* 468 * This is optional, as this is a trade-off between 469 * analog performance and power consumption. 470 */ 471 ret = regulator_enable(priv->booster); 472 if (ret < 0) { 473 dev_err(dev, "booster enable failed %d\n", ret); 474 return ret; 475 } 476 dev_dbg(dev, "analog switches supplied by booster\n"); 477 478 return 0; 479 } 480 } 481 482 /* Fallback using vdda (default), nothing to do */ 483 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n", 484 priv->vdda_uv); 485 486 return 0; 487 } 488 489 static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv) 490 { 491 if (priv->vdda_uv < 2700000) { 492 if (priv->syscfg && priv->vdd_uv > 2700000) { 493 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR, 494 STM32MP1_SYSCFG_ANASWVDD_MASK); 495 regulator_disable(priv->vdd); 496 return; 497 } 498 if (priv->booster) 499 regulator_disable(priv->booster); 500 } 501 } 502 503 static int stm32_adc_core_hw_start(struct device *dev) 504 { 505 struct stm32_adc_common *common = dev_get_drvdata(dev); 506 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 507 int ret; 508 509 ret = regulator_enable(priv->vdda); 510 if (ret < 0) { 511 dev_err(dev, "vdda enable failed %d\n", ret); 512 return ret; 513 } 514 515 ret = regulator_get_voltage(priv->vdda); 516 if (ret < 0) { 517 dev_err(dev, "vdda get voltage failed, %d\n", ret); 518 goto err_vdda_disable; 519 } 520 priv->vdda_uv = ret; 521 522 ret = stm32_adc_core_switches_supply_en(priv, dev); 523 if (ret < 0) 524 goto err_vdda_disable; 525 526 ret = regulator_enable(priv->vref); 527 if (ret < 0) { 528 dev_err(dev, "vref enable failed\n"); 529 goto err_switches_dis; 530 } 531 532 if (priv->bclk) { 533 ret = clk_prepare_enable(priv->bclk); 534 if (ret < 0) { 535 dev_err(dev, "bus clk enable failed\n"); 536 goto err_regulator_disable; 537 } 538 } 539 540 if (priv->aclk) { 541 ret = clk_prepare_enable(priv->aclk); 542 if (ret < 0) { 543 dev_err(dev, "adc clk enable failed\n"); 544 goto err_bclk_disable; 545 } 546 } 547 548 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr); 549 550 return 0; 551 552 err_bclk_disable: 553 if (priv->bclk) 554 clk_disable_unprepare(priv->bclk); 555 err_regulator_disable: 556 regulator_disable(priv->vref); 557 err_switches_dis: 558 stm32_adc_core_switches_supply_dis(priv); 559 err_vdda_disable: 560 regulator_disable(priv->vdda); 561 562 return ret; 563 } 564 565 static void stm32_adc_core_hw_stop(struct device *dev) 566 { 567 struct stm32_adc_common *common = dev_get_drvdata(dev); 568 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 569 570 /* Backup CCR that may be lost (depends on power state to achieve) */ 571 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr); 572 if (priv->aclk) 573 clk_disable_unprepare(priv->aclk); 574 if (priv->bclk) 575 clk_disable_unprepare(priv->bclk); 576 regulator_disable(priv->vref); 577 stm32_adc_core_switches_supply_dis(priv); 578 regulator_disable(priv->vdda); 579 } 580 581 static int stm32_adc_core_switches_probe(struct device *dev, 582 struct stm32_adc_priv *priv) 583 { 584 struct device_node *np = dev->of_node; 585 int ret; 586 587 /* Analog switches supply can be controlled by syscfg (optional) */ 588 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 589 if (IS_ERR(priv->syscfg)) { 590 ret = PTR_ERR(priv->syscfg); 591 if (ret != -ENODEV) { 592 if (ret != -EPROBE_DEFER) 593 dev_err(dev, "Can't probe syscfg: %d\n", ret); 594 return ret; 595 } 596 priv->syscfg = NULL; 597 } 598 599 /* Booster can be used to supply analog switches (optional) */ 600 if (priv->cfg->has_syscfg & HAS_VBOOSTER && 601 of_property_read_bool(np, "booster-supply")) { 602 priv->booster = devm_regulator_get_optional(dev, "booster"); 603 if (IS_ERR(priv->booster)) { 604 ret = PTR_ERR(priv->booster); 605 if (ret != -ENODEV) { 606 if (ret != -EPROBE_DEFER) 607 dev_err(dev, "can't get booster %d\n", 608 ret); 609 return ret; 610 } 611 priv->booster = NULL; 612 } 613 } 614 615 /* Vdd can be used to supply analog switches (optional) */ 616 if (priv->cfg->has_syscfg & HAS_ANASWVDD && 617 of_property_read_bool(np, "vdd-supply")) { 618 priv->vdd = devm_regulator_get_optional(dev, "vdd"); 619 if (IS_ERR(priv->vdd)) { 620 ret = PTR_ERR(priv->vdd); 621 if (ret != -ENODEV) { 622 if (ret != -EPROBE_DEFER) 623 dev_err(dev, "can't get vdd %d\n", ret); 624 return ret; 625 } 626 priv->vdd = NULL; 627 } 628 } 629 630 if (priv->vdd) { 631 ret = regulator_enable(priv->vdd); 632 if (ret < 0) { 633 dev_err(dev, "vdd enable failed %d\n", ret); 634 return ret; 635 } 636 637 ret = regulator_get_voltage(priv->vdd); 638 if (ret < 0) { 639 dev_err(dev, "vdd get voltage failed %d\n", ret); 640 regulator_disable(priv->vdd); 641 return ret; 642 } 643 priv->vdd_uv = ret; 644 645 regulator_disable(priv->vdd); 646 } 647 648 return 0; 649 } 650 651 static int stm32_adc_probe(struct platform_device *pdev) 652 { 653 struct stm32_adc_priv *priv; 654 struct device *dev = &pdev->dev; 655 struct device_node *np = pdev->dev.of_node; 656 struct resource *res; 657 int ret; 658 659 if (!pdev->dev.of_node) 660 return -ENODEV; 661 662 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 663 if (!priv) 664 return -ENOMEM; 665 platform_set_drvdata(pdev, &priv->common); 666 667 priv->cfg = (const struct stm32_adc_priv_cfg *) 668 of_match_device(dev->driver->of_match_table, dev)->data; 669 670 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 671 priv->common.base = devm_ioremap_resource(&pdev->dev, res); 672 if (IS_ERR(priv->common.base)) 673 return PTR_ERR(priv->common.base); 674 priv->common.phys_base = res->start; 675 676 priv->vdda = devm_regulator_get(&pdev->dev, "vdda"); 677 if (IS_ERR(priv->vdda)) { 678 ret = PTR_ERR(priv->vdda); 679 if (ret != -EPROBE_DEFER) 680 dev_err(&pdev->dev, "vdda get failed, %d\n", ret); 681 return ret; 682 } 683 684 priv->vref = devm_regulator_get(&pdev->dev, "vref"); 685 if (IS_ERR(priv->vref)) { 686 ret = PTR_ERR(priv->vref); 687 dev_err(&pdev->dev, "vref get failed, %d\n", ret); 688 return ret; 689 } 690 691 priv->aclk = devm_clk_get(&pdev->dev, "adc"); 692 if (IS_ERR(priv->aclk)) { 693 ret = PTR_ERR(priv->aclk); 694 if (ret != -ENOENT) { 695 dev_err(&pdev->dev, "Can't get 'adc' clock\n"); 696 return ret; 697 } 698 priv->aclk = NULL; 699 } 700 701 priv->bclk = devm_clk_get(&pdev->dev, "bus"); 702 if (IS_ERR(priv->bclk)) { 703 ret = PTR_ERR(priv->bclk); 704 if (ret != -ENOENT) { 705 dev_err(&pdev->dev, "Can't get 'bus' clock\n"); 706 return ret; 707 } 708 priv->bclk = NULL; 709 } 710 711 ret = stm32_adc_core_switches_probe(dev, priv); 712 if (ret) 713 return ret; 714 715 pm_runtime_get_noresume(dev); 716 pm_runtime_set_active(dev); 717 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS); 718 pm_runtime_use_autosuspend(dev); 719 pm_runtime_enable(dev); 720 721 ret = stm32_adc_core_hw_start(dev); 722 if (ret) 723 goto err_pm_stop; 724 725 ret = regulator_get_voltage(priv->vref); 726 if (ret < 0) { 727 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret); 728 goto err_hw_stop; 729 } 730 priv->common.vref_mv = ret / 1000; 731 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv); 732 733 ret = priv->cfg->clk_sel(pdev, priv); 734 if (ret < 0) 735 goto err_hw_stop; 736 737 ret = stm32_adc_irq_probe(pdev, priv); 738 if (ret < 0) 739 goto err_hw_stop; 740 741 ret = of_platform_populate(np, NULL, NULL, &pdev->dev); 742 if (ret < 0) { 743 dev_err(&pdev->dev, "failed to populate DT children\n"); 744 goto err_irq_remove; 745 } 746 747 pm_runtime_mark_last_busy(dev); 748 pm_runtime_put_autosuspend(dev); 749 750 return 0; 751 752 err_irq_remove: 753 stm32_adc_irq_remove(pdev, priv); 754 err_hw_stop: 755 stm32_adc_core_hw_stop(dev); 756 err_pm_stop: 757 pm_runtime_disable(dev); 758 pm_runtime_set_suspended(dev); 759 pm_runtime_put_noidle(dev); 760 761 return ret; 762 } 763 764 static int stm32_adc_remove(struct platform_device *pdev) 765 { 766 struct stm32_adc_common *common = platform_get_drvdata(pdev); 767 struct stm32_adc_priv *priv = to_stm32_adc_priv(common); 768 769 pm_runtime_get_sync(&pdev->dev); 770 of_platform_depopulate(&pdev->dev); 771 stm32_adc_irq_remove(pdev, priv); 772 stm32_adc_core_hw_stop(&pdev->dev); 773 pm_runtime_disable(&pdev->dev); 774 pm_runtime_set_suspended(&pdev->dev); 775 pm_runtime_put_noidle(&pdev->dev); 776 777 return 0; 778 } 779 780 #if defined(CONFIG_PM) 781 static int stm32_adc_core_runtime_suspend(struct device *dev) 782 { 783 stm32_adc_core_hw_stop(dev); 784 785 return 0; 786 } 787 788 static int stm32_adc_core_runtime_resume(struct device *dev) 789 { 790 return stm32_adc_core_hw_start(dev); 791 } 792 #endif 793 794 static const struct dev_pm_ops stm32_adc_core_pm_ops = { 795 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 796 pm_runtime_force_resume) 797 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend, 798 stm32_adc_core_runtime_resume, 799 NULL) 800 }; 801 802 static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { 803 .regs = &stm32f4_adc_common_regs, 804 .clk_sel = stm32f4_adc_clk_sel, 805 .max_clk_rate_hz = 36000000, 806 }; 807 808 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { 809 .regs = &stm32h7_adc_common_regs, 810 .clk_sel = stm32h7_adc_clk_sel, 811 .max_clk_rate_hz = 36000000, 812 .has_syscfg = HAS_VBOOSTER, 813 }; 814 815 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = { 816 .regs = &stm32h7_adc_common_regs, 817 .clk_sel = stm32h7_adc_clk_sel, 818 .max_clk_rate_hz = 40000000, 819 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD, 820 }; 821 822 static const struct of_device_id stm32_adc_of_match[] = { 823 { 824 .compatible = "st,stm32f4-adc-core", 825 .data = (void *)&stm32f4_adc_priv_cfg 826 }, { 827 .compatible = "st,stm32h7-adc-core", 828 .data = (void *)&stm32h7_adc_priv_cfg 829 }, { 830 .compatible = "st,stm32mp1-adc-core", 831 .data = (void *)&stm32mp1_adc_priv_cfg 832 }, { 833 }, 834 }; 835 MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 836 837 static struct platform_driver stm32_adc_driver = { 838 .probe = stm32_adc_probe, 839 .remove = stm32_adc_remove, 840 .driver = { 841 .name = "stm32-adc-core", 842 .of_match_table = stm32_adc_of_match, 843 .pm = &stm32_adc_core_pm_ops, 844 }, 845 }; 846 module_platform_driver(stm32_adc_driver); 847 848 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 849 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver"); 850 MODULE_LICENSE("GPL v2"); 851 MODULE_ALIAS("platform:stm32-adc-core"); 852