1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD5592R Digital <-> Analog converters driver 4 * 5 * Copyright 2014-2016 Analog Devices Inc. 6 * Author: Paul Cercueil <paul.cercueil@analog.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/delay.h> 11 #include <linux/iio/iio.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/property.h> 19 20 #include <dt-bindings/iio/adi,ad5592r.h> 21 22 #include "ad5592r-base.h" 23 24 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset) 25 { 26 struct ad5592r_state *st = gpiochip_get_data(chip); 27 int ret = 0; 28 u8 val; 29 30 mutex_lock(&st->gpio_lock); 31 32 if (st->gpio_out & BIT(offset)) 33 val = st->gpio_val; 34 else 35 ret = st->ops->gpio_read(st, &val); 36 37 mutex_unlock(&st->gpio_lock); 38 39 if (ret < 0) 40 return ret; 41 42 return !!(val & BIT(offset)); 43 } 44 45 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 46 { 47 struct ad5592r_state *st = gpiochip_get_data(chip); 48 49 mutex_lock(&st->gpio_lock); 50 51 if (value) 52 st->gpio_val |= BIT(offset); 53 else 54 st->gpio_val &= ~BIT(offset); 55 56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 57 58 mutex_unlock(&st->gpio_lock); 59 } 60 61 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 62 { 63 struct ad5592r_state *st = gpiochip_get_data(chip); 64 int ret; 65 66 mutex_lock(&st->gpio_lock); 67 68 st->gpio_out &= ~BIT(offset); 69 st->gpio_in |= BIT(offset); 70 71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 72 if (ret < 0) 73 goto err_unlock; 74 75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 76 77 err_unlock: 78 mutex_unlock(&st->gpio_lock); 79 80 return ret; 81 } 82 83 static int ad5592r_gpio_direction_output(struct gpio_chip *chip, 84 unsigned offset, int value) 85 { 86 struct ad5592r_state *st = gpiochip_get_data(chip); 87 int ret; 88 89 mutex_lock(&st->gpio_lock); 90 91 if (value) 92 st->gpio_val |= BIT(offset); 93 else 94 st->gpio_val &= ~BIT(offset); 95 96 st->gpio_in &= ~BIT(offset); 97 st->gpio_out |= BIT(offset); 98 99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 100 if (ret < 0) 101 goto err_unlock; 102 103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 104 if (ret < 0) 105 goto err_unlock; 106 107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 108 109 err_unlock: 110 mutex_unlock(&st->gpio_lock); 111 112 return ret; 113 } 114 115 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset) 116 { 117 struct ad5592r_state *st = gpiochip_get_data(chip); 118 119 if (!(st->gpio_map & BIT(offset))) { 120 dev_err(st->dev, "GPIO %d is reserved by alternate function\n", 121 offset); 122 return -ENODEV; 123 } 124 125 return 0; 126 } 127 128 static int ad5592r_gpio_init(struct ad5592r_state *st) 129 { 130 if (!st->gpio_map) 131 return 0; 132 133 st->gpiochip.label = dev_name(st->dev); 134 st->gpiochip.base = -1; 135 st->gpiochip.ngpio = 8; 136 st->gpiochip.parent = st->dev; 137 st->gpiochip.can_sleep = true; 138 st->gpiochip.direction_input = ad5592r_gpio_direction_input; 139 st->gpiochip.direction_output = ad5592r_gpio_direction_output; 140 st->gpiochip.get = ad5592r_gpio_get; 141 st->gpiochip.set = ad5592r_gpio_set; 142 st->gpiochip.request = ad5592r_gpio_request; 143 st->gpiochip.owner = THIS_MODULE; 144 145 mutex_init(&st->gpio_lock); 146 147 return gpiochip_add_data(&st->gpiochip, st); 148 } 149 150 static void ad5592r_gpio_cleanup(struct ad5592r_state *st) 151 { 152 if (st->gpio_map) 153 gpiochip_remove(&st->gpiochip); 154 } 155 156 static int ad5592r_reset(struct ad5592r_state *st) 157 { 158 struct gpio_desc *gpio; 159 struct iio_dev *iio_dev = iio_priv_to_dev(st); 160 161 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW); 162 if (IS_ERR(gpio)) 163 return PTR_ERR(gpio); 164 165 if (gpio) { 166 udelay(1); 167 gpiod_set_value(gpio, 1); 168 } else { 169 mutex_lock(&iio_dev->mlock); 170 /* Writing this magic value resets the device */ 171 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); 172 mutex_unlock(&iio_dev->mlock); 173 } 174 175 udelay(250); 176 177 return 0; 178 } 179 180 static int ad5592r_get_vref(struct ad5592r_state *st) 181 { 182 int ret; 183 184 if (st->reg) { 185 ret = regulator_get_voltage(st->reg); 186 if (ret < 0) 187 return ret; 188 189 return ret / 1000; 190 } else { 191 return 2500; 192 } 193 } 194 195 static int ad5592r_set_channel_modes(struct ad5592r_state *st) 196 { 197 const struct ad5592r_rw_ops *ops = st->ops; 198 int ret; 199 unsigned i; 200 struct iio_dev *iio_dev = iio_priv_to_dev(st); 201 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0; 202 u16 read_back; 203 204 for (i = 0; i < st->num_channels; i++) { 205 switch (st->channel_modes[i]) { 206 case CH_MODE_DAC: 207 dac |= BIT(i); 208 break; 209 210 case CH_MODE_ADC: 211 adc |= BIT(i); 212 break; 213 214 case CH_MODE_DAC_AND_ADC: 215 dac |= BIT(i); 216 adc |= BIT(i); 217 break; 218 219 case CH_MODE_GPIO: 220 st->gpio_map |= BIT(i); 221 st->gpio_in |= BIT(i); /* Default to input */ 222 break; 223 224 case CH_MODE_UNUSED: 225 /* fall-through */ 226 default: 227 switch (st->channel_offstate[i]) { 228 case CH_OFFSTATE_OUT_TRISTATE: 229 tristate |= BIT(i); 230 break; 231 232 case CH_OFFSTATE_OUT_LOW: 233 st->gpio_out |= BIT(i); 234 break; 235 236 case CH_OFFSTATE_OUT_HIGH: 237 st->gpio_out |= BIT(i); 238 st->gpio_val |= BIT(i); 239 break; 240 241 case CH_OFFSTATE_PULLDOWN: 242 /* fall-through */ 243 default: 244 pulldown |= BIT(i); 245 break; 246 } 247 } 248 } 249 250 mutex_lock(&iio_dev->mlock); 251 252 /* Pull down unused pins to GND */ 253 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); 254 if (ret) 255 goto err_unlock; 256 257 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); 258 if (ret) 259 goto err_unlock; 260 261 /* Configure pins that we use */ 262 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); 263 if (ret) 264 goto err_unlock; 265 266 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc); 267 if (ret) 268 goto err_unlock; 269 270 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); 271 if (ret) 272 goto err_unlock; 273 274 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); 275 if (ret) 276 goto err_unlock; 277 278 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); 279 if (ret) 280 goto err_unlock; 281 282 /* Verify that we can read back at least one register */ 283 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back); 284 if (!ret && (read_back & 0xff) != adc) 285 ret = -EIO; 286 287 err_unlock: 288 mutex_unlock(&iio_dev->mlock); 289 return ret; 290 } 291 292 static int ad5592r_reset_channel_modes(struct ad5592r_state *st) 293 { 294 int i; 295 296 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++) 297 st->channel_modes[i] = CH_MODE_UNUSED; 298 299 return ad5592r_set_channel_modes(st); 300 } 301 302 static int ad5592r_write_raw(struct iio_dev *iio_dev, 303 struct iio_chan_spec const *chan, int val, int val2, long mask) 304 { 305 struct ad5592r_state *st = iio_priv(iio_dev); 306 int ret; 307 308 switch (mask) { 309 case IIO_CHAN_INFO_RAW: 310 311 if (val >= (1 << chan->scan_type.realbits) || val < 0) 312 return -EINVAL; 313 314 if (!chan->output) 315 return -EINVAL; 316 317 mutex_lock(&iio_dev->mlock); 318 ret = st->ops->write_dac(st, chan->channel, val); 319 if (!ret) 320 st->cached_dac[chan->channel] = val; 321 mutex_unlock(&iio_dev->mlock); 322 return ret; 323 case IIO_CHAN_INFO_SCALE: 324 if (chan->type == IIO_VOLTAGE) { 325 bool gain; 326 327 if (val == st->scale_avail[0][0] && 328 val2 == st->scale_avail[0][1]) 329 gain = false; 330 else if (val == st->scale_avail[1][0] && 331 val2 == st->scale_avail[1][1]) 332 gain = true; 333 else 334 return -EINVAL; 335 336 mutex_lock(&iio_dev->mlock); 337 338 ret = st->ops->reg_read(st, AD5592R_REG_CTRL, 339 &st->cached_gp_ctrl); 340 if (ret < 0) { 341 mutex_unlock(&iio_dev->mlock); 342 return ret; 343 } 344 345 if (chan->output) { 346 if (gain) 347 st->cached_gp_ctrl |= 348 AD5592R_REG_CTRL_DAC_RANGE; 349 else 350 st->cached_gp_ctrl &= 351 ~AD5592R_REG_CTRL_DAC_RANGE; 352 } else { 353 if (gain) 354 st->cached_gp_ctrl |= 355 AD5592R_REG_CTRL_ADC_RANGE; 356 else 357 st->cached_gp_ctrl &= 358 ~AD5592R_REG_CTRL_ADC_RANGE; 359 } 360 361 ret = st->ops->reg_write(st, AD5592R_REG_CTRL, 362 st->cached_gp_ctrl); 363 mutex_unlock(&iio_dev->mlock); 364 365 return ret; 366 } 367 break; 368 default: 369 return -EINVAL; 370 } 371 372 return 0; 373 } 374 375 static int ad5592r_read_raw(struct iio_dev *iio_dev, 376 struct iio_chan_spec const *chan, 377 int *val, int *val2, long m) 378 { 379 struct ad5592r_state *st = iio_priv(iio_dev); 380 u16 read_val; 381 int ret; 382 383 switch (m) { 384 case IIO_CHAN_INFO_RAW: 385 mutex_lock(&iio_dev->mlock); 386 387 if (!chan->output) { 388 ret = st->ops->read_adc(st, chan->channel, &read_val); 389 if (ret) 390 goto unlock; 391 392 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) { 393 dev_err(st->dev, "Error while reading channel %u\n", 394 chan->channel); 395 ret = -EIO; 396 goto unlock; 397 } 398 399 read_val &= GENMASK(11, 0); 400 401 } else { 402 read_val = st->cached_dac[chan->channel]; 403 } 404 405 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n", 406 chan->channel, read_val); 407 408 *val = (int) read_val; 409 ret = IIO_VAL_INT; 410 break; 411 case IIO_CHAN_INFO_SCALE: 412 *val = ad5592r_get_vref(st); 413 414 if (chan->type == IIO_TEMP) { 415 s64 tmp = *val * (3767897513LL / 25LL); 416 *val = div_s64_rem(tmp, 1000000000LL, val2); 417 418 ret = IIO_VAL_INT_PLUS_MICRO; 419 } else { 420 int mult; 421 422 mutex_lock(&iio_dev->mlock); 423 424 if (chan->output) 425 mult = !!(st->cached_gp_ctrl & 426 AD5592R_REG_CTRL_DAC_RANGE); 427 else 428 mult = !!(st->cached_gp_ctrl & 429 AD5592R_REG_CTRL_ADC_RANGE); 430 431 *val *= ++mult; 432 433 *val2 = chan->scan_type.realbits; 434 ret = IIO_VAL_FRACTIONAL_LOG2; 435 } 436 break; 437 case IIO_CHAN_INFO_OFFSET: 438 ret = ad5592r_get_vref(st); 439 440 mutex_lock(&iio_dev->mlock); 441 442 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) 443 *val = (-34365 * 25) / ret; 444 else 445 *val = (-75365 * 25) / ret; 446 ret = IIO_VAL_INT; 447 break; 448 default: 449 ret = -EINVAL; 450 } 451 452 unlock: 453 mutex_unlock(&iio_dev->mlock); 454 return ret; 455 } 456 457 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev, 458 struct iio_chan_spec const *chan, long mask) 459 { 460 switch (mask) { 461 case IIO_CHAN_INFO_SCALE: 462 return IIO_VAL_INT_PLUS_NANO; 463 464 default: 465 return IIO_VAL_INT_PLUS_MICRO; 466 } 467 468 return -EINVAL; 469 } 470 471 static const struct iio_info ad5592r_info = { 472 .read_raw = ad5592r_read_raw, 473 .write_raw = ad5592r_write_raw, 474 .write_raw_get_fmt = ad5592r_write_raw_get_fmt, 475 }; 476 477 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev, 478 uintptr_t private, 479 const struct iio_chan_spec *chan, 480 char *buf) 481 { 482 struct ad5592r_state *st = iio_priv(iio_dev); 483 484 return sprintf(buf, "%d.%09u %d.%09u\n", 485 st->scale_avail[0][0], st->scale_avail[0][1], 486 st->scale_avail[1][0], st->scale_avail[1][1]); 487 } 488 489 static struct iio_chan_spec_ext_info ad5592r_ext_info[] = { 490 { 491 .name = "scale_available", 492 .read = ad5592r_show_scale_available, 493 .shared = true, 494 }, 495 {}, 496 }; 497 498 static void ad5592r_setup_channel(struct iio_dev *iio_dev, 499 struct iio_chan_spec *chan, bool output, unsigned id) 500 { 501 chan->type = IIO_VOLTAGE; 502 chan->indexed = 1; 503 chan->output = output; 504 chan->channel = id; 505 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 506 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 507 chan->scan_type.sign = 'u'; 508 chan->scan_type.realbits = 12; 509 chan->scan_type.storagebits = 16; 510 chan->ext_info = ad5592r_ext_info; 511 } 512 513 static int ad5592r_alloc_channels(struct ad5592r_state *st) 514 { 515 unsigned i, curr_channel = 0, 516 num_channels = st->num_channels; 517 struct iio_dev *iio_dev = iio_priv_to_dev(st); 518 struct iio_chan_spec *channels; 519 struct fwnode_handle *child; 520 u32 reg, tmp; 521 int ret; 522 523 device_for_each_child_node(st->dev, child) { 524 ret = fwnode_property_read_u32(child, "reg", ®); 525 if (ret || reg >= ARRAY_SIZE(st->channel_modes)) 526 continue; 527 528 ret = fwnode_property_read_u32(child, "adi,mode", &tmp); 529 if (!ret) 530 st->channel_modes[reg] = tmp; 531 532 fwnode_property_read_u32(child, "adi,off-state", &tmp); 533 if (!ret) 534 st->channel_offstate[reg] = tmp; 535 } 536 537 channels = devm_kcalloc(st->dev, 538 1 + 2 * num_channels, sizeof(*channels), 539 GFP_KERNEL); 540 if (!channels) 541 return -ENOMEM; 542 543 for (i = 0; i < num_channels; i++) { 544 switch (st->channel_modes[i]) { 545 case CH_MODE_DAC: 546 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 547 true, i); 548 curr_channel++; 549 break; 550 551 case CH_MODE_ADC: 552 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 553 false, i); 554 curr_channel++; 555 break; 556 557 case CH_MODE_DAC_AND_ADC: 558 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 559 true, i); 560 curr_channel++; 561 ad5592r_setup_channel(iio_dev, &channels[curr_channel], 562 false, i); 563 curr_channel++; 564 break; 565 566 default: 567 continue; 568 } 569 } 570 571 channels[curr_channel].type = IIO_TEMP; 572 channels[curr_channel].channel = 8; 573 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 574 BIT(IIO_CHAN_INFO_SCALE) | 575 BIT(IIO_CHAN_INFO_OFFSET); 576 curr_channel++; 577 578 iio_dev->num_channels = curr_channel; 579 iio_dev->channels = channels; 580 581 return 0; 582 } 583 584 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV) 585 { 586 s64 tmp = (s64)vref_mV * 1000000000LL >> 12; 587 588 st->scale_avail[0][0] = 589 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]); 590 st->scale_avail[1][0] = 591 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]); 592 } 593 594 int ad5592r_probe(struct device *dev, const char *name, 595 const struct ad5592r_rw_ops *ops) 596 { 597 struct iio_dev *iio_dev; 598 struct ad5592r_state *st; 599 int ret; 600 601 iio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 602 if (!iio_dev) 603 return -ENOMEM; 604 605 st = iio_priv(iio_dev); 606 st->dev = dev; 607 st->ops = ops; 608 st->num_channels = 8; 609 dev_set_drvdata(dev, iio_dev); 610 611 st->reg = devm_regulator_get_optional(dev, "vref"); 612 if (IS_ERR(st->reg)) { 613 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node) 614 return PTR_ERR(st->reg); 615 616 st->reg = NULL; 617 } else { 618 ret = regulator_enable(st->reg); 619 if (ret) 620 return ret; 621 } 622 623 iio_dev->dev.parent = dev; 624 iio_dev->name = name; 625 iio_dev->info = &ad5592r_info; 626 iio_dev->modes = INDIO_DIRECT_MODE; 627 628 ad5592r_init_scales(st, ad5592r_get_vref(st)); 629 630 ret = ad5592r_reset(st); 631 if (ret) 632 goto error_disable_reg; 633 634 ret = ops->reg_write(st, AD5592R_REG_PD, 635 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0); 636 if (ret) 637 goto error_disable_reg; 638 639 ret = ad5592r_alloc_channels(st); 640 if (ret) 641 goto error_disable_reg; 642 643 ret = ad5592r_set_channel_modes(st); 644 if (ret) 645 goto error_reset_ch_modes; 646 647 ret = iio_device_register(iio_dev); 648 if (ret) 649 goto error_reset_ch_modes; 650 651 ret = ad5592r_gpio_init(st); 652 if (ret) 653 goto error_dev_unregister; 654 655 return 0; 656 657 error_dev_unregister: 658 iio_device_unregister(iio_dev); 659 660 error_reset_ch_modes: 661 ad5592r_reset_channel_modes(st); 662 663 error_disable_reg: 664 if (st->reg) 665 regulator_disable(st->reg); 666 667 return ret; 668 } 669 EXPORT_SYMBOL_GPL(ad5592r_probe); 670 671 int ad5592r_remove(struct device *dev) 672 { 673 struct iio_dev *iio_dev = dev_get_drvdata(dev); 674 struct ad5592r_state *st = iio_priv(iio_dev); 675 676 iio_device_unregister(iio_dev); 677 ad5592r_reset_channel_modes(st); 678 ad5592r_gpio_cleanup(st); 679 680 if (st->reg) 681 regulator_disable(st->reg); 682 683 return 0; 684 } 685 EXPORT_SYMBOL_GPL(ad5592r_remove); 686 687 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>"); 688 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters"); 689 MODULE_LICENSE("GPL v2"); 690