1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2020 Invensense, Inc. 4 */ 5 6 #ifndef INV_ICM42600_H_ 7 #define INV_ICM42600_H_ 8 9 #include <linux/bits.h> 10 #include <linux/bitfield.h> 11 #include <linux/regmap.h> 12 #include <linux/mutex.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/pm.h> 15 #include <linux/iio/iio.h> 16 17 #include "inv_icm42600_buffer.h" 18 19 enum inv_icm42600_chip { 20 INV_CHIP_ICM42600, 21 INV_CHIP_ICM42602, 22 INV_CHIP_ICM42605, 23 INV_CHIP_ICM42622, 24 INV_CHIP_NB, 25 }; 26 27 /* serial bus slew rates */ 28 enum inv_icm42600_slew_rate { 29 INV_ICM42600_SLEW_RATE_20_60NS, 30 INV_ICM42600_SLEW_RATE_12_36NS, 31 INV_ICM42600_SLEW_RATE_6_18NS, 32 INV_ICM42600_SLEW_RATE_4_12NS, 33 INV_ICM42600_SLEW_RATE_2_6NS, 34 INV_ICM42600_SLEW_RATE_INF_2NS, 35 }; 36 37 enum inv_icm42600_sensor_mode { 38 INV_ICM42600_SENSOR_MODE_OFF, 39 INV_ICM42600_SENSOR_MODE_STANDBY, 40 INV_ICM42600_SENSOR_MODE_LOW_POWER, 41 INV_ICM42600_SENSOR_MODE_LOW_NOISE, 42 INV_ICM42600_SENSOR_MODE_NB, 43 }; 44 45 /* gyroscope fullscale values */ 46 enum inv_icm42600_gyro_fs { 47 INV_ICM42600_GYRO_FS_2000DPS, 48 INV_ICM42600_GYRO_FS_1000DPS, 49 INV_ICM42600_GYRO_FS_500DPS, 50 INV_ICM42600_GYRO_FS_250DPS, 51 INV_ICM42600_GYRO_FS_125DPS, 52 INV_ICM42600_GYRO_FS_62_5DPS, 53 INV_ICM42600_GYRO_FS_31_25DPS, 54 INV_ICM42600_GYRO_FS_15_625DPS, 55 INV_ICM42600_GYRO_FS_NB, 56 }; 57 58 /* accelerometer fullscale values */ 59 enum inv_icm42600_accel_fs { 60 INV_ICM42600_ACCEL_FS_16G, 61 INV_ICM42600_ACCEL_FS_8G, 62 INV_ICM42600_ACCEL_FS_4G, 63 INV_ICM42600_ACCEL_FS_2G, 64 INV_ICM42600_ACCEL_FS_NB, 65 }; 66 67 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */ 68 enum inv_icm42600_odr { 69 INV_ICM42600_ODR_8KHZ_LN = 3, 70 INV_ICM42600_ODR_4KHZ_LN, 71 INV_ICM42600_ODR_2KHZ_LN, 72 INV_ICM42600_ODR_1KHZ_LN, 73 INV_ICM42600_ODR_200HZ, 74 INV_ICM42600_ODR_100HZ, 75 INV_ICM42600_ODR_50HZ, 76 INV_ICM42600_ODR_25HZ, 77 INV_ICM42600_ODR_12_5HZ, 78 INV_ICM42600_ODR_6_25HZ_LP, 79 INV_ICM42600_ODR_3_125HZ_LP, 80 INV_ICM42600_ODR_1_5625HZ_LP, 81 INV_ICM42600_ODR_500HZ, 82 INV_ICM42600_ODR_NB, 83 }; 84 85 enum inv_icm42600_filter { 86 /* Low-Noise mode sensor data filter (3rd order filter by default) */ 87 INV_ICM42600_FILTER_BW_ODR_DIV_2, 88 89 /* Low-Power mode sensor data filter (averaging) */ 90 INV_ICM42600_FILTER_AVG_1X = 1, 91 INV_ICM42600_FILTER_AVG_16X = 6, 92 }; 93 94 struct inv_icm42600_sensor_conf { 95 int mode; 96 int fs; 97 int odr; 98 int filter; 99 }; 100 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1} 101 102 struct inv_icm42600_conf { 103 struct inv_icm42600_sensor_conf gyro; 104 struct inv_icm42600_sensor_conf accel; 105 bool temp_en; 106 }; 107 108 struct inv_icm42600_suspended { 109 enum inv_icm42600_sensor_mode gyro; 110 enum inv_icm42600_sensor_mode accel; 111 bool temp; 112 }; 113 114 /** 115 * struct inv_icm42600_state - driver state variables 116 * @lock: lock for serializing multiple registers access. 117 * @chip: chip identifier. 118 * @name: chip name. 119 * @map: regmap pointer. 120 * @vdd_supply: VDD voltage regulator for the chip. 121 * @vddio_supply: I/O voltage regulator for the chip. 122 * @orientation: sensor chip orientation relative to main hardware. 123 * @conf: chip sensors configurations. 124 * @suspended: suspended sensors configuration. 125 * @indio_gyro: gyroscope IIO device. 126 * @indio_accel: accelerometer IIO device. 127 * @buffer: data transfer buffer aligned for DMA. 128 * @fifo: FIFO management structure. 129 * @timestamp: interrupt timestamps. 130 */ 131 struct inv_icm42600_state { 132 struct mutex lock; 133 enum inv_icm42600_chip chip; 134 const char *name; 135 struct regmap *map; 136 struct regulator *vdd_supply; 137 struct regulator *vddio_supply; 138 struct iio_mount_matrix orientation; 139 struct inv_icm42600_conf conf; 140 struct inv_icm42600_suspended suspended; 141 struct iio_dev *indio_gyro; 142 struct iio_dev *indio_accel; 143 uint8_t buffer[2] ____cacheline_aligned; 144 struct inv_icm42600_fifo fifo; 145 struct { 146 int64_t gyro; 147 int64_t accel; 148 } timestamp; 149 }; 150 151 /* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */ 152 153 /* Bank selection register, available in all banks */ 154 #define INV_ICM42600_REG_BANK_SEL 0x76 155 #define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0) 156 157 /* User bank 0 (MSB 0x00) */ 158 #define INV_ICM42600_REG_DEVICE_CONFIG 0x0011 159 #define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0) 160 161 #define INV_ICM42600_REG_DRIVE_CONFIG 0x0013 162 #define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3) 163 #define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \ 164 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_I2C_MASK, (_rate)) 165 #define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0) 166 #define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \ 167 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_SPI_MASK, (_rate)) 168 169 #define INV_ICM42600_REG_INT_CONFIG 0x0014 170 #define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5) 171 #define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4) 172 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3) 173 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00 174 #define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2) 175 #define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1) 176 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0) 177 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00 178 179 #define INV_ICM42600_REG_FIFO_CONFIG 0x0016 180 #define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6) 181 #define INV_ICM42600_FIFO_CONFIG_BYPASS \ 182 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 0) 183 #define INV_ICM42600_FIFO_CONFIG_STREAM \ 184 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 1) 185 #define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \ 186 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2) 187 188 /* all sensor data are 16 bits (2 registers wide) in big-endian */ 189 #define INV_ICM42600_REG_TEMP_DATA 0x001D 190 #define INV_ICM42600_REG_ACCEL_DATA_X 0x001F 191 #define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021 192 #define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023 193 #define INV_ICM42600_REG_GYRO_DATA_X 0x0025 194 #define INV_ICM42600_REG_GYRO_DATA_Y 0x0027 195 #define INV_ICM42600_REG_GYRO_DATA_Z 0x0029 196 #define INV_ICM42600_DATA_INVALID -32768 197 198 #define INV_ICM42600_REG_INT_STATUS 0x002D 199 #define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6) 200 #define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5) 201 #define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4) 202 #define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3) 203 #define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2) 204 #define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1) 205 #define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0) 206 207 /* 208 * FIFO access registers 209 * FIFO count is 16 bits (2 registers) big-endian 210 * FIFO data is a continuous read register to read FIFO content 211 */ 212 #define INV_ICM42600_REG_FIFO_COUNT 0x002E 213 #define INV_ICM42600_REG_FIFO_DATA 0x0030 214 215 #define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B 216 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6) 217 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5) 218 #define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3) 219 #define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2) 220 #define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1) 221 222 /* default configuration: all data big-endian and fifo count in bytes */ 223 #define INV_ICM42600_REG_INTF_CONFIG0 0x004C 224 #define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7) 225 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6) 226 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5) 227 #define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4) 228 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0) 229 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \ 230 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 2) 231 #define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \ 232 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 3) 233 234 #define INV_ICM42600_REG_INTF_CONFIG1 0x004D 235 #define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3) 236 237 #define INV_ICM42600_REG_PWR_MGMT0 0x004E 238 #define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5) 239 #define INV_ICM42600_PWR_MGMT0_IDLE BIT(4) 240 #define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \ 241 FIELD_PREP(GENMASK(3, 2), (_mode)) 242 #define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \ 243 FIELD_PREP(GENMASK(1, 0), (_mode)) 244 245 #define INV_ICM42600_REG_GYRO_CONFIG0 0x004F 246 #define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \ 247 FIELD_PREP(GENMASK(7, 5), (_fs)) 248 #define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \ 249 FIELD_PREP(GENMASK(3, 0), (_odr)) 250 251 #define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050 252 #define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \ 253 FIELD_PREP(GENMASK(7, 5), (_fs)) 254 #define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \ 255 FIELD_PREP(GENMASK(3, 0), (_odr)) 256 257 #define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052 258 #define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \ 259 FIELD_PREP(GENMASK(7, 4), (_f)) 260 #define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \ 261 FIELD_PREP(GENMASK(3, 0), (_f)) 262 263 #define INV_ICM42600_REG_TMST_CONFIG 0x0054 264 #define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0) 265 #define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4) 266 #define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3) 267 #define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2) 268 #define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1) 269 #define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0) 270 271 #define INV_ICM42600_REG_FIFO_CONFIG1 0x005F 272 #define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6) 273 #define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5) 274 #define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3) 275 #define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2) 276 #define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1) 277 #define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0) 278 279 /* FIFO watermark is 16 bits (2 registers wide) in little-endian */ 280 #define INV_ICM42600_REG_FIFO_WATERMARK 0x0060 281 #define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \ 282 cpu_to_le16((_wm) & GENMASK(11, 0)) 283 /* FIFO is 2048 bytes, let 12 samples for reading latency */ 284 #define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16) 285 286 #define INV_ICM42600_REG_INT_CONFIG1 0x0064 287 #define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6) 288 #define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5) 289 #define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4) 290 291 #define INV_ICM42600_REG_INT_SOURCE0 0x0065 292 #define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6) 293 #define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5) 294 #define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4) 295 #define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3) 296 #define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2) 297 #define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1) 298 #define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0) 299 300 #define INV_ICM42600_REG_WHOAMI 0x0075 301 #define INV_ICM42600_WHOAMI_ICM42600 0x40 302 #define INV_ICM42600_WHOAMI_ICM42602 0x41 303 #define INV_ICM42600_WHOAMI_ICM42605 0x42 304 #define INV_ICM42600_WHOAMI_ICM42622 0x46 305 306 /* User bank 1 (MSB 0x10) */ 307 #define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003 308 #define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5) 309 #define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4) 310 #define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3) 311 #define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2) 312 #define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1) 313 #define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0) 314 315 /* Timestamp value is 20 bits (3 registers) in little-endian */ 316 #define INV_ICM42600_REG_TMSTVAL 0x1062 317 #define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0) 318 319 #define INV_ICM42600_REG_INTF_CONFIG4 0x107A 320 #define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6) 321 #define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1) 322 323 #define INV_ICM42600_REG_INTF_CONFIG6 0x107C 324 #define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0) 325 #define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4) 326 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3) 327 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2) 328 #define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1) 329 #define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0) 330 331 /* User bank 4 (MSB 0x40) */ 332 #define INV_ICM42600_REG_INT_SOURCE8 0x404F 333 #define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5) 334 #define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4) 335 #define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3) 336 #define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2) 337 #define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1) 338 #define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0) 339 340 #define INV_ICM42600_REG_OFFSET_USER0 0x4077 341 #define INV_ICM42600_REG_OFFSET_USER1 0x4078 342 #define INV_ICM42600_REG_OFFSET_USER2 0x4079 343 #define INV_ICM42600_REG_OFFSET_USER3 0x407A 344 #define INV_ICM42600_REG_OFFSET_USER4 0x407B 345 #define INV_ICM42600_REG_OFFSET_USER5 0x407C 346 #define INV_ICM42600_REG_OFFSET_USER6 0x407D 347 #define INV_ICM42600_REG_OFFSET_USER7 0x407E 348 #define INV_ICM42600_REG_OFFSET_USER8 0x407F 349 350 /* Sleep times required by the driver */ 351 #define INV_ICM42600_POWER_UP_TIME_MS 100 352 #define INV_ICM42600_RESET_TIME_MS 1 353 #define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20 354 #define INV_ICM42600_GYRO_STARTUP_TIME_MS 60 355 #define INV_ICM42600_GYRO_STOP_TIME_MS 150 356 #define INV_ICM42600_TEMP_STARTUP_TIME_MS 14 357 #define INV_ICM42600_SUSPEND_DELAY_MS 2000 358 359 typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *); 360 361 extern const struct regmap_config inv_icm42600_regmap_config; 362 extern const struct dev_pm_ops inv_icm42600_pm_ops; 363 364 const struct iio_mount_matrix * 365 inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev, 366 const struct iio_chan_spec *chan); 367 368 uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr); 369 370 int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st, 371 struct inv_icm42600_sensor_conf *conf, 372 unsigned int *sleep_ms); 373 374 int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st, 375 struct inv_icm42600_sensor_conf *conf, 376 unsigned int *sleep_ms); 377 378 int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable, 379 unsigned int *sleep_ms); 380 381 int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg, 382 unsigned int writeval, unsigned int *readval); 383 384 int inv_icm42600_core_probe(struct regmap *regmap, int chip, int irq, 385 inv_icm42600_bus_setup bus_setup); 386 387 struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st); 388 389 int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev); 390 391 struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st); 392 393 int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev); 394 395 #endif 396