1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Invensense, Inc. 4 */ 5 6 #ifndef INV_MPU_IIO_H_ 7 #define INV_MPU_IIO_H_ 8 9 #include <linux/i2c.h> 10 #include <linux/i2c-mux.h> 11 #include <linux/mutex.h> 12 #include <linux/iio/iio.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/regmap.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/kfifo_buf.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/platform_data/invensense_mpu6050.h> 21 22 /** 23 * struct inv_mpu6050_reg_map - Notable registers. 24 * @sample_rate_div: Divider applied to gyro output rate. 25 * @lpf: Configures internal low pass filter. 26 * @accel_lpf: Configures accelerometer low pass filter. 27 * @user_ctrl: Enables/resets the FIFO. 28 * @fifo_en: Determines which data will appear in FIFO. 29 * @gyro_config: gyro config register. 30 * @accl_config: accel config register 31 * @fifo_count_h: Upper byte of FIFO count. 32 * @fifo_r_w: FIFO register. 33 * @raw_gyro: Address of first gyro register. 34 * @raw_accl: Address of first accel register. 35 * @temperature: temperature register 36 * @int_enable: Interrupt enable register. 37 * @int_status: Interrupt status register. 38 * @pwr_mgmt_1: Controls chip's power state and clock source. 39 * @pwr_mgmt_2: Controls power state of individual sensors. 40 * @int_pin_cfg; Controls interrupt pin configuration. 41 * @accl_offset: Controls the accelerometer calibration offset. 42 * @gyro_offset: Controls the gyroscope calibration offset. 43 * @i2c_if: Controls the i2c interface 44 */ 45 struct inv_mpu6050_reg_map { 46 u8 sample_rate_div; 47 u8 lpf; 48 u8 accel_lpf; 49 u8 user_ctrl; 50 u8 fifo_en; 51 u8 gyro_config; 52 u8 accl_config; 53 u8 fifo_count_h; 54 u8 fifo_r_w; 55 u8 raw_gyro; 56 u8 raw_accl; 57 u8 temperature; 58 u8 int_enable; 59 u8 int_status; 60 u8 pwr_mgmt_1; 61 u8 pwr_mgmt_2; 62 u8 int_pin_cfg; 63 u8 accl_offset; 64 u8 gyro_offset; 65 u8 i2c_if; 66 }; 67 68 /*device enum */ 69 enum inv_devices { 70 INV_MPU6050, 71 INV_MPU6500, 72 INV_MPU6515, 73 INV_MPU6000, 74 INV_MPU9150, 75 INV_MPU9250, 76 INV_MPU9255, 77 INV_ICM20608, 78 INV_ICM20602, 79 INV_NUM_PARTS 80 }; 81 82 /** 83 * struct inv_mpu6050_chip_config - Cached chip configuration data. 84 * @fsr: Full scale range. 85 * @lpf: Digital low pass filter frequency. 86 * @accl_fs: accel full scale range. 87 * @accl_fifo_enable: enable accel data output 88 * @gyro_fifo_enable: enable gyro data output 89 * @magn_fifo_enable: enable magn data output 90 * @divider: chip sample rate divider (sample rate divider - 1) 91 */ 92 struct inv_mpu6050_chip_config { 93 unsigned int fsr:2; 94 unsigned int lpf:3; 95 unsigned int accl_fs:2; 96 unsigned int accl_fifo_enable:1; 97 unsigned int gyro_fifo_enable:1; 98 unsigned int magn_fifo_enable:1; 99 u8 divider; 100 u8 user_ctrl; 101 }; 102 103 /** 104 * struct inv_mpu6050_hw - Other important hardware information. 105 * @whoami: Self identification byte from WHO_AM_I register 106 * @name: name of the chip. 107 * @reg: register map of the chip. 108 * @config: configuration of the chip. 109 * @fifo_size: size of the FIFO in bytes. 110 * @temp: offset and scale to apply to raw temperature. 111 */ 112 struct inv_mpu6050_hw { 113 u8 whoami; 114 u8 *name; 115 const struct inv_mpu6050_reg_map *reg; 116 const struct inv_mpu6050_chip_config *config; 117 size_t fifo_size; 118 struct { 119 int offset; 120 int scale; 121 } temp; 122 }; 123 124 /* 125 * struct inv_mpu6050_state - Driver state variables. 126 * @lock: Chip access lock. 127 * @trig: IIO trigger. 128 * @chip_config: Cached attribute information. 129 * @reg: Map of important registers. 130 * @hw: Other hardware-specific information. 131 * @chip_type: chip type. 132 * @plat_data: platform data (deprecated in favor of @orientation). 133 * @orientation: sensor chip orientation relative to main hardware. 134 * @map regmap pointer. 135 * @irq interrupt number. 136 * @irq_mask the int_pin_cfg mask to configure interrupt type. 137 * @chip_period: chip internal period estimation (~1kHz). 138 * @it_timestamp: timestamp from previous interrupt. 139 * @data_timestamp: timestamp for next data sample. 140 * @vdd_supply: VDD voltage regulator for the chip. 141 * @vddio_supply I/O voltage regulator for the chip. 142 * @magn_disabled: magnetometer disabled for backward compatibility reason. 143 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. 144 * @magn_orient: magnetometer sensor chip orientation if available. 145 */ 146 struct inv_mpu6050_state { 147 struct mutex lock; 148 struct iio_trigger *trig; 149 struct inv_mpu6050_chip_config chip_config; 150 const struct inv_mpu6050_reg_map *reg; 151 const struct inv_mpu6050_hw *hw; 152 enum inv_devices chip_type; 153 struct i2c_mux_core *muxc; 154 struct i2c_client *mux_client; 155 unsigned int powerup_count; 156 struct inv_mpu6050_platform_data plat_data; 157 struct iio_mount_matrix orientation; 158 struct regmap *map; 159 int irq; 160 u8 irq_mask; 161 unsigned skip_samples; 162 s64 chip_period; 163 s64 it_timestamp; 164 s64 data_timestamp; 165 struct regulator *vdd_supply; 166 struct regulator *vddio_supply; 167 bool magn_disabled; 168 s32 magn_raw_to_gauss[3]; 169 struct iio_mount_matrix magn_orient; 170 }; 171 172 /*register and associated bit definition*/ 173 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 174 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 175 176 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 177 #define INV_MPU6050_REG_CONFIG 0x1A 178 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 179 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 180 181 #define INV_MPU6050_REG_FIFO_EN 0x23 182 #define INV_MPU6050_BIT_SLAVE_0 0x01 183 #define INV_MPU6050_BIT_SLAVE_1 0x02 184 #define INV_MPU6050_BIT_SLAVE_2 0x04 185 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 186 #define INV_MPU6050_BITS_GYRO_OUT 0x70 187 188 #define INV_MPU6050_REG_I2C_MST_CTRL 0x24 189 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D 190 #define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10 191 #define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20 192 #define INV_MPU6050_BIT_WAIT_FOR_ES 0x40 193 #define INV_MPU6050_BIT_MULT_MST_EN 0x80 194 195 /* control I2C slaves from 0 to 3 */ 196 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x)) 197 #define INV_MPU6050_BIT_I2C_SLV_RNW 0x80 198 199 #define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x)) 200 201 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x)) 202 #define INV_MPU6050_BIT_SLV_GRP 0x10 203 #define INV_MPU6050_BIT_SLV_REG_DIS 0x20 204 #define INV_MPU6050_BIT_SLV_BYTE_SW 0x40 205 #define INV_MPU6050_BIT_SLV_EN 0x80 206 207 /* I2C master delay register */ 208 #define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34 209 #define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F) 210 211 #define INV_MPU6050_REG_I2C_MST_STATUS 0x36 212 #define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01 213 #define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02 214 #define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04 215 #define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08 216 217 #define INV_MPU6050_REG_INT_ENABLE 0x38 218 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 219 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 220 221 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 222 #define INV_MPU6050_REG_TEMPERATURE 0x41 223 #define INV_MPU6050_REG_RAW_GYRO 0x43 224 225 #define INV_MPU6050_REG_INT_STATUS 0x3A 226 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 227 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 228 229 #define INV_MPU6050_REG_EXT_SENS_DATA 0x49 230 231 /* I2C slaves data output from 0 to 3 */ 232 #define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x)) 233 234 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 235 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01 236 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02 237 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04 238 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08 239 #define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80 240 241 #define INV_MPU6050_REG_USER_CTRL 0x6A 242 #define INV_MPU6050_BIT_FIFO_RST 0x04 243 #define INV_MPU6050_BIT_DMP_RST 0x08 244 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 245 #define INV_MPU6050_BIT_FIFO_EN 0x40 246 #define INV_MPU6050_BIT_DMP_EN 0x80 247 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 248 249 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 250 #define INV_MPU6050_BIT_H_RESET 0x80 251 #define INV_MPU6050_BIT_SLEEP 0x40 252 #define INV_MPU6050_BIT_CLK_MASK 0x7 253 254 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 255 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 256 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 257 258 /* ICM20602 register */ 259 #define INV_ICM20602_REG_I2C_IF 0x70 260 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40 261 262 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 263 #define INV_MPU6050_REG_FIFO_R_W 0x74 264 265 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 266 #define INV_MPU6050_FIFO_COUNT_BYTE 2 267 268 /* MPU9X50 9-axis magnetometer */ 269 #define INV_MPU9X50_BYTES_MAGN 7 270 271 /* ICM20602 FIFO samples include temperature readings */ 272 #define INV_ICM20602_BYTES_PER_TEMP_SENSOR 2 273 274 /* mpu6500 registers */ 275 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 276 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 277 278 /* delay time in milliseconds */ 279 #define INV_MPU6050_POWER_UP_TIME 100 280 #define INV_MPU6050_TEMP_UP_TIME 100 281 #define INV_MPU6050_SENSOR_UP_TIME 30 282 283 /* delay time in microseconds */ 284 #define INV_MPU6050_REG_UP_TIME_MIN 5000 285 #define INV_MPU6050_REG_UP_TIME_MAX 10000 286 287 #define INV_MPU6050_TEMP_OFFSET 12420 288 #define INV_MPU6050_TEMP_SCALE 2941176 289 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 290 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 291 #define INV_MPU6050_THREE_AXIS 3 292 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 293 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 294 295 #define INV_MPU6500_TEMP_OFFSET 7011 296 #define INV_MPU6500_TEMP_SCALE 2995178 297 298 #define INV_ICM20608_TEMP_OFFSET 8170 299 #define INV_ICM20608_TEMP_SCALE 3059976 300 301 /* 6 + 6 + 7 (for MPU9x50) = 19 round up to 24 and plus 8 */ 302 #define INV_MPU6050_OUTPUT_DATA_SIZE 32 303 304 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 305 #define INV_MPU6050_ACTIVE_HIGH 0x00 306 #define INV_MPU6050_ACTIVE_LOW 0x80 307 /* enable level triggering */ 308 #define INV_MPU6050_LATCH_INT_EN 0x20 309 #define INV_MPU6050_BIT_BYPASS_EN 0x2 310 311 /* Allowed timestamp period jitter in percent */ 312 #define INV_MPU6050_TS_PERIOD_JITTER 4 313 314 /* init parameters */ 315 #define INV_MPU6050_INIT_FIFO_RATE 50 316 #define INV_MPU6050_MAX_FIFO_RATE 1000 317 #define INV_MPU6050_MIN_FIFO_RATE 4 318 319 /* chip internal frequency: 1KHz */ 320 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000 321 /* return the frequency divider (chip sample rate divider + 1) */ 322 #define INV_MPU6050_FREQ_DIVIDER(st) \ 323 ((st)->chip_config.divider + 1) 324 /* chip sample rate divider to fifo rate */ 325 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ 326 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) 327 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ 328 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) 329 330 #define INV_MPU6050_REG_WHOAMI 117 331 332 #define INV_MPU6000_WHOAMI_VALUE 0x68 333 #define INV_MPU6050_WHOAMI_VALUE 0x68 334 #define INV_MPU6500_WHOAMI_VALUE 0x70 335 #define INV_MPU9150_WHOAMI_VALUE 0x68 336 #define INV_MPU9250_WHOAMI_VALUE 0x71 337 #define INV_MPU9255_WHOAMI_VALUE 0x73 338 #define INV_MPU6515_WHOAMI_VALUE 0x74 339 #define INV_ICM20608_WHOAMI_VALUE 0xAF 340 #define INV_ICM20602_WHOAMI_VALUE 0x12 341 342 /* scan element definition for generic MPU6xxx devices */ 343 enum inv_mpu6050_scan { 344 INV_MPU6050_SCAN_ACCL_X, 345 INV_MPU6050_SCAN_ACCL_Y, 346 INV_MPU6050_SCAN_ACCL_Z, 347 INV_MPU6050_SCAN_GYRO_X, 348 INV_MPU6050_SCAN_GYRO_Y, 349 INV_MPU6050_SCAN_GYRO_Z, 350 INV_MPU6050_SCAN_TIMESTAMP, 351 352 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1, 353 INV_MPU9X50_SCAN_MAGN_Y, 354 INV_MPU9X50_SCAN_MAGN_Z, 355 INV_MPU9X50_SCAN_TIMESTAMP, 356 }; 357 358 /* scan element definition for ICM20602, which includes temperature */ 359 enum inv_icm20602_scan { 360 INV_ICM20602_SCAN_ACCL_X, 361 INV_ICM20602_SCAN_ACCL_Y, 362 INV_ICM20602_SCAN_ACCL_Z, 363 INV_ICM20602_SCAN_TEMP, 364 INV_ICM20602_SCAN_GYRO_X, 365 INV_ICM20602_SCAN_GYRO_Y, 366 INV_ICM20602_SCAN_GYRO_Z, 367 INV_ICM20602_SCAN_TIMESTAMP, 368 }; 369 370 enum inv_mpu6050_filter_e { 371 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 372 INV_MPU6050_FILTER_188HZ, 373 INV_MPU6050_FILTER_98HZ, 374 INV_MPU6050_FILTER_42HZ, 375 INV_MPU6050_FILTER_20HZ, 376 INV_MPU6050_FILTER_10HZ, 377 INV_MPU6050_FILTER_5HZ, 378 INV_MPU6050_FILTER_2100HZ_NOLPF, 379 NUM_MPU6050_FILTER 380 }; 381 382 /* IIO attribute address */ 383 enum INV_MPU6050_IIO_ATTR_ADDR { 384 ATTR_GYRO_MATRIX, 385 ATTR_ACCL_MATRIX, 386 }; 387 388 enum inv_mpu6050_accl_fs_e { 389 INV_MPU6050_FS_02G = 0, 390 INV_MPU6050_FS_04G, 391 INV_MPU6050_FS_08G, 392 INV_MPU6050_FS_16G, 393 NUM_ACCL_FSR 394 }; 395 396 enum inv_mpu6050_fsr_e { 397 INV_MPU6050_FSR_250DPS = 0, 398 INV_MPU6050_FSR_500DPS, 399 INV_MPU6050_FSR_1000DPS, 400 INV_MPU6050_FSR_2000DPS, 401 NUM_MPU6050_FSR 402 }; 403 404 enum inv_mpu6050_clock_sel_e { 405 INV_CLK_INTERNAL = 0, 406 INV_CLK_PLL, 407 NUM_CLK 408 }; 409 410 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 411 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 412 int inv_reset_fifo(struct iio_dev *indio_dev); 413 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 414 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 415 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 416 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 417 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 418 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 419 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 420 extern const struct dev_pm_ops inv_mpu_pmops; 421 422 #endif 423