1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Invensense, Inc. 4 */ 5 6 #ifndef INV_MPU_IIO_H_ 7 #define INV_MPU_IIO_H_ 8 9 #include <linux/i2c.h> 10 #include <linux/i2c-mux.h> 11 #include <linux/mutex.h> 12 #include <linux/iio/iio.h> 13 #include <linux/iio/buffer.h> 14 #include <linux/regmap.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/kfifo_buf.h> 17 #include <linux/iio/trigger.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/trigger_consumer.h> 20 #include <linux/platform_data/invensense_mpu6050.h> 21 22 /** 23 * struct inv_mpu6050_reg_map - Notable registers. 24 * @sample_rate_div: Divider applied to gyro output rate. 25 * @lpf: Configures internal low pass filter. 26 * @accel_lpf: Configures accelerometer low pass filter. 27 * @user_ctrl: Enables/resets the FIFO. 28 * @fifo_en: Determines which data will appear in FIFO. 29 * @gyro_config: gyro config register. 30 * @accl_config: accel config register 31 * @fifo_count_h: Upper byte of FIFO count. 32 * @fifo_r_w: FIFO register. 33 * @raw_gyro: Address of first gyro register. 34 * @raw_accl: Address of first accel register. 35 * @temperature: temperature register 36 * @int_enable: Interrupt enable register. 37 * @int_status: Interrupt status register. 38 * @pwr_mgmt_1: Controls chip's power state and clock source. 39 * @pwr_mgmt_2: Controls power state of individual sensors. 40 * @int_pin_cfg; Controls interrupt pin configuration. 41 * @accl_offset: Controls the accelerometer calibration offset. 42 * @gyro_offset: Controls the gyroscope calibration offset. 43 * @i2c_if: Controls the i2c interface 44 */ 45 struct inv_mpu6050_reg_map { 46 u8 sample_rate_div; 47 u8 lpf; 48 u8 accel_lpf; 49 u8 user_ctrl; 50 u8 fifo_en; 51 u8 gyro_config; 52 u8 accl_config; 53 u8 fifo_count_h; 54 u8 fifo_r_w; 55 u8 raw_gyro; 56 u8 raw_accl; 57 u8 temperature; 58 u8 int_enable; 59 u8 int_status; 60 u8 pwr_mgmt_1; 61 u8 pwr_mgmt_2; 62 u8 int_pin_cfg; 63 u8 accl_offset; 64 u8 gyro_offset; 65 u8 i2c_if; 66 }; 67 68 /*device enum */ 69 enum inv_devices { 70 INV_MPU6050, 71 INV_MPU6500, 72 INV_MPU6515, 73 INV_MPU6000, 74 INV_MPU9150, 75 INV_MPU9250, 76 INV_MPU9255, 77 INV_ICM20608, 78 INV_ICM20602, 79 INV_NUM_PARTS 80 }; 81 82 /** 83 * struct inv_mpu6050_chip_config - Cached chip configuration data. 84 * @fsr: Full scale range. 85 * @lpf: Digital low pass filter frequency. 86 * @accl_fs: accel full scale range. 87 * @accl_fifo_enable: enable accel data output 88 * @gyro_fifo_enable: enable gyro data output 89 * @temp_fifo_enable: enable temp data output 90 * @magn_fifo_enable: enable magn data output 91 * @divider: chip sample rate divider (sample rate divider - 1) 92 */ 93 struct inv_mpu6050_chip_config { 94 unsigned int fsr:2; 95 unsigned int lpf:3; 96 unsigned int accl_fs:2; 97 unsigned int accl_fifo_enable:1; 98 unsigned int gyro_fifo_enable:1; 99 unsigned int temp_fifo_enable:1; 100 unsigned int magn_fifo_enable:1; 101 u8 divider; 102 u8 user_ctrl; 103 }; 104 105 /** 106 * struct inv_mpu6050_hw - Other important hardware information. 107 * @whoami: Self identification byte from WHO_AM_I register 108 * @name: name of the chip. 109 * @reg: register map of the chip. 110 * @config: configuration of the chip. 111 * @fifo_size: size of the FIFO in bytes. 112 * @temp: offset and scale to apply to raw temperature. 113 */ 114 struct inv_mpu6050_hw { 115 u8 whoami; 116 u8 *name; 117 const struct inv_mpu6050_reg_map *reg; 118 const struct inv_mpu6050_chip_config *config; 119 size_t fifo_size; 120 struct { 121 int offset; 122 int scale; 123 } temp; 124 }; 125 126 /* 127 * struct inv_mpu6050_state - Driver state variables. 128 * @lock: Chip access lock. 129 * @trig: IIO trigger. 130 * @chip_config: Cached attribute information. 131 * @reg: Map of important registers. 132 * @hw: Other hardware-specific information. 133 * @chip_type: chip type. 134 * @plat_data: platform data (deprecated in favor of @orientation). 135 * @orientation: sensor chip orientation relative to main hardware. 136 * @map regmap pointer. 137 * @irq interrupt number. 138 * @irq_mask the int_pin_cfg mask to configure interrupt type. 139 * @chip_period: chip internal period estimation (~1kHz). 140 * @it_timestamp: timestamp from previous interrupt. 141 * @data_timestamp: timestamp for next data sample. 142 * @vdd_supply: VDD voltage regulator for the chip. 143 * @vddio_supply I/O voltage regulator for the chip. 144 * @magn_disabled: magnetometer disabled for backward compatibility reason. 145 * @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss. 146 * @magn_orient: magnetometer sensor chip orientation if available. 147 */ 148 struct inv_mpu6050_state { 149 struct mutex lock; 150 struct iio_trigger *trig; 151 struct inv_mpu6050_chip_config chip_config; 152 const struct inv_mpu6050_reg_map *reg; 153 const struct inv_mpu6050_hw *hw; 154 enum inv_devices chip_type; 155 struct i2c_mux_core *muxc; 156 struct i2c_client *mux_client; 157 unsigned int powerup_count; 158 struct inv_mpu6050_platform_data plat_data; 159 struct iio_mount_matrix orientation; 160 struct regmap *map; 161 int irq; 162 u8 irq_mask; 163 unsigned skip_samples; 164 s64 chip_period; 165 s64 it_timestamp; 166 s64 data_timestamp; 167 struct regulator *vdd_supply; 168 struct regulator *vddio_supply; 169 bool magn_disabled; 170 s32 magn_raw_to_gauss[3]; 171 struct iio_mount_matrix magn_orient; 172 }; 173 174 /*register and associated bit definition*/ 175 #define INV_MPU6050_REG_ACCEL_OFFSET 0x06 176 #define INV_MPU6050_REG_GYRO_OFFSET 0x13 177 178 #define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19 179 #define INV_MPU6050_REG_CONFIG 0x1A 180 #define INV_MPU6050_REG_GYRO_CONFIG 0x1B 181 #define INV_MPU6050_REG_ACCEL_CONFIG 0x1C 182 183 #define INV_MPU6050_REG_FIFO_EN 0x23 184 #define INV_MPU6050_BIT_SLAVE_0 0x01 185 #define INV_MPU6050_BIT_SLAVE_1 0x02 186 #define INV_MPU6050_BIT_SLAVE_2 0x04 187 #define INV_MPU6050_BIT_ACCEL_OUT 0x08 188 #define INV_MPU6050_BITS_GYRO_OUT 0x70 189 #define INV_MPU6050_BIT_TEMP_OUT 0x80 190 191 #define INV_MPU6050_REG_I2C_MST_CTRL 0x24 192 #define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D 193 #define INV_MPU6050_BIT_I2C_MST_P_NSR 0x10 194 #define INV_MPU6050_BIT_SLV3_FIFO_EN 0x20 195 #define INV_MPU6050_BIT_WAIT_FOR_ES 0x40 196 #define INV_MPU6050_BIT_MULT_MST_EN 0x80 197 198 /* control I2C slaves from 0 to 3 */ 199 #define INV_MPU6050_REG_I2C_SLV_ADDR(_x) (0x25 + 3 * (_x)) 200 #define INV_MPU6050_BIT_I2C_SLV_RNW 0x80 201 202 #define INV_MPU6050_REG_I2C_SLV_REG(_x) (0x26 + 3 * (_x)) 203 204 #define INV_MPU6050_REG_I2C_SLV_CTRL(_x) (0x27 + 3 * (_x)) 205 #define INV_MPU6050_BIT_SLV_GRP 0x10 206 #define INV_MPU6050_BIT_SLV_REG_DIS 0x20 207 #define INV_MPU6050_BIT_SLV_BYTE_SW 0x40 208 #define INV_MPU6050_BIT_SLV_EN 0x80 209 210 /* I2C master delay register */ 211 #define INV_MPU6050_REG_I2C_SLV4_CTRL 0x34 212 #define INV_MPU6050_BITS_I2C_MST_DLY(_x) ((_x) & 0x1F) 213 214 #define INV_MPU6050_REG_I2C_MST_STATUS 0x36 215 #define INV_MPU6050_BIT_I2C_SLV0_NACK 0x01 216 #define INV_MPU6050_BIT_I2C_SLV1_NACK 0x02 217 #define INV_MPU6050_BIT_I2C_SLV2_NACK 0x04 218 #define INV_MPU6050_BIT_I2C_SLV3_NACK 0x08 219 220 #define INV_MPU6050_REG_INT_ENABLE 0x38 221 #define INV_MPU6050_BIT_DATA_RDY_EN 0x01 222 #define INV_MPU6050_BIT_DMP_INT_EN 0x02 223 224 #define INV_MPU6050_REG_RAW_ACCEL 0x3B 225 #define INV_MPU6050_REG_TEMPERATURE 0x41 226 #define INV_MPU6050_REG_RAW_GYRO 0x43 227 228 #define INV_MPU6050_REG_INT_STATUS 0x3A 229 #define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10 230 #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01 231 232 #define INV_MPU6050_REG_EXT_SENS_DATA 0x49 233 234 /* I2C slaves data output from 0 to 3 */ 235 #define INV_MPU6050_REG_I2C_SLV_DO(_x) (0x63 + (_x)) 236 237 #define INV_MPU6050_REG_I2C_MST_DELAY_CTRL 0x67 238 #define INV_MPU6050_BIT_I2C_SLV0_DLY_EN 0x01 239 #define INV_MPU6050_BIT_I2C_SLV1_DLY_EN 0x02 240 #define INV_MPU6050_BIT_I2C_SLV2_DLY_EN 0x04 241 #define INV_MPU6050_BIT_I2C_SLV3_DLY_EN 0x08 242 #define INV_MPU6050_BIT_DELAY_ES_SHADOW 0x80 243 244 #define INV_MPU6050_REG_USER_CTRL 0x6A 245 #define INV_MPU6050_BIT_FIFO_RST 0x04 246 #define INV_MPU6050_BIT_DMP_RST 0x08 247 #define INV_MPU6050_BIT_I2C_MST_EN 0x20 248 #define INV_MPU6050_BIT_FIFO_EN 0x40 249 #define INV_MPU6050_BIT_DMP_EN 0x80 250 #define INV_MPU6050_BIT_I2C_IF_DIS 0x10 251 252 #define INV_MPU6050_REG_PWR_MGMT_1 0x6B 253 #define INV_MPU6050_BIT_H_RESET 0x80 254 #define INV_MPU6050_BIT_SLEEP 0x40 255 #define INV_MPU6050_BIT_CLK_MASK 0x7 256 257 #define INV_MPU6050_REG_PWR_MGMT_2 0x6C 258 #define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38 259 #define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07 260 261 /* ICM20602 register */ 262 #define INV_ICM20602_REG_I2C_IF 0x70 263 #define INV_ICM20602_BIT_I2C_IF_DIS 0x40 264 265 #define INV_MPU6050_REG_FIFO_COUNT_H 0x72 266 #define INV_MPU6050_REG_FIFO_R_W 0x74 267 268 #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6 269 #define INV_MPU6050_FIFO_COUNT_BYTE 2 270 271 /* MPU9X50 9-axis magnetometer */ 272 #define INV_MPU9X50_BYTES_MAGN 7 273 274 /* FIFO temperature sample size */ 275 #define INV_MPU6050_BYTES_PER_TEMP_SENSOR 2 276 277 /* mpu6500 registers */ 278 #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D 279 #define INV_MPU6500_REG_ACCEL_OFFSET 0x77 280 281 /* delay time in milliseconds */ 282 #define INV_MPU6050_POWER_UP_TIME 100 283 #define INV_MPU6050_TEMP_UP_TIME 100 284 #define INV_MPU6050_SENSOR_UP_TIME 30 285 286 /* delay time in microseconds */ 287 #define INV_MPU6050_REG_UP_TIME_MIN 5000 288 #define INV_MPU6050_REG_UP_TIME_MAX 10000 289 290 #define INV_MPU6050_TEMP_OFFSET 12420 291 #define INV_MPU6050_TEMP_SCALE 2941176 292 #define INV_MPU6050_MAX_GYRO_FS_PARAM 3 293 #define INV_MPU6050_MAX_ACCL_FS_PARAM 3 294 #define INV_MPU6050_THREE_AXIS 3 295 #define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3 296 #define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3 297 298 #define INV_MPU6500_TEMP_OFFSET 7011 299 #define INV_MPU6500_TEMP_SCALE 2995178 300 301 #define INV_ICM20608_TEMP_OFFSET 8170 302 #define INV_ICM20608_TEMP_SCALE 3059976 303 304 /* 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8 */ 305 #define INV_MPU6050_OUTPUT_DATA_SIZE 32 306 307 #define INV_MPU6050_REG_INT_PIN_CFG 0x37 308 #define INV_MPU6050_ACTIVE_HIGH 0x00 309 #define INV_MPU6050_ACTIVE_LOW 0x80 310 /* enable level triggering */ 311 #define INV_MPU6050_LATCH_INT_EN 0x20 312 #define INV_MPU6050_BIT_BYPASS_EN 0x2 313 314 /* Allowed timestamp period jitter in percent */ 315 #define INV_MPU6050_TS_PERIOD_JITTER 4 316 317 /* init parameters */ 318 #define INV_MPU6050_INIT_FIFO_RATE 50 319 #define INV_MPU6050_MAX_FIFO_RATE 1000 320 #define INV_MPU6050_MIN_FIFO_RATE 4 321 322 /* chip internal frequency: 1KHz */ 323 #define INV_MPU6050_INTERNAL_FREQ_HZ 1000 324 /* return the frequency divider (chip sample rate divider + 1) */ 325 #define INV_MPU6050_FREQ_DIVIDER(st) \ 326 ((st)->chip_config.divider + 1) 327 /* chip sample rate divider to fifo rate */ 328 #define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate) \ 329 ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1) 330 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \ 331 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1)) 332 333 #define INV_MPU6050_REG_WHOAMI 117 334 335 #define INV_MPU6000_WHOAMI_VALUE 0x68 336 #define INV_MPU6050_WHOAMI_VALUE 0x68 337 #define INV_MPU6500_WHOAMI_VALUE 0x70 338 #define INV_MPU9150_WHOAMI_VALUE 0x68 339 #define INV_MPU9250_WHOAMI_VALUE 0x71 340 #define INV_MPU9255_WHOAMI_VALUE 0x73 341 #define INV_MPU6515_WHOAMI_VALUE 0x74 342 #define INV_ICM20608_WHOAMI_VALUE 0xAF 343 #define INV_ICM20602_WHOAMI_VALUE 0x12 344 345 /* scan element definition for generic MPU6xxx devices */ 346 enum inv_mpu6050_scan { 347 INV_MPU6050_SCAN_ACCL_X, 348 INV_MPU6050_SCAN_ACCL_Y, 349 INV_MPU6050_SCAN_ACCL_Z, 350 INV_MPU6050_SCAN_TEMP, 351 INV_MPU6050_SCAN_GYRO_X, 352 INV_MPU6050_SCAN_GYRO_Y, 353 INV_MPU6050_SCAN_GYRO_Z, 354 INV_MPU6050_SCAN_TIMESTAMP, 355 356 INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1, 357 INV_MPU9X50_SCAN_MAGN_Y, 358 INV_MPU9X50_SCAN_MAGN_Z, 359 INV_MPU9X50_SCAN_TIMESTAMP, 360 }; 361 362 enum inv_mpu6050_filter_e { 363 INV_MPU6050_FILTER_256HZ_NOLPF2 = 0, 364 INV_MPU6050_FILTER_188HZ, 365 INV_MPU6050_FILTER_98HZ, 366 INV_MPU6050_FILTER_42HZ, 367 INV_MPU6050_FILTER_20HZ, 368 INV_MPU6050_FILTER_10HZ, 369 INV_MPU6050_FILTER_5HZ, 370 INV_MPU6050_FILTER_2100HZ_NOLPF, 371 NUM_MPU6050_FILTER 372 }; 373 374 /* IIO attribute address */ 375 enum INV_MPU6050_IIO_ATTR_ADDR { 376 ATTR_GYRO_MATRIX, 377 ATTR_ACCL_MATRIX, 378 }; 379 380 enum inv_mpu6050_accl_fs_e { 381 INV_MPU6050_FS_02G = 0, 382 INV_MPU6050_FS_04G, 383 INV_MPU6050_FS_08G, 384 INV_MPU6050_FS_16G, 385 NUM_ACCL_FSR 386 }; 387 388 enum inv_mpu6050_fsr_e { 389 INV_MPU6050_FSR_250DPS = 0, 390 INV_MPU6050_FSR_500DPS, 391 INV_MPU6050_FSR_1000DPS, 392 INV_MPU6050_FSR_2000DPS, 393 NUM_MPU6050_FSR 394 }; 395 396 enum inv_mpu6050_clock_sel_e { 397 INV_CLK_INTERNAL = 0, 398 INV_CLK_PLL, 399 NUM_CLK 400 }; 401 402 irqreturn_t inv_mpu6050_read_fifo(int irq, void *p); 403 int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type); 404 int inv_reset_fifo(struct iio_dev *indio_dev); 405 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask); 406 int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val); 407 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on); 408 int inv_mpu_acpi_create_mux_client(struct i2c_client *client); 409 void inv_mpu_acpi_delete_mux_client(struct i2c_client *client); 410 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, 411 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type); 412 extern const struct dev_pm_ops inv_mpu_pmops; 413 414 #endif 415