1 /* 2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/module.h> 34 #include <linux/moduleparam.h> 35 #include <rdma/ib_umem.h> 36 #include <linux/atomic.h> 37 #include <rdma/ib_user_verbs.h> 38 39 #include "iw_cxgb4.h" 40 41 int use_dsgl = 1; 42 module_param(use_dsgl, int, 0644); 43 MODULE_PARM_DESC(use_dsgl, "Use DSGL for PBL/FastReg (default=1) (DEPRECATED)"); 44 45 #define T4_ULPTX_MIN_IO 32 46 #define C4IW_MAX_INLINE_SIZE 96 47 #define T4_ULPTX_MAX_DMA 1024 48 #define C4IW_INLINE_THRESHOLD 128 49 50 static int inline_threshold = C4IW_INLINE_THRESHOLD; 51 module_param(inline_threshold, int, 0644); 52 MODULE_PARM_DESC(inline_threshold, "inline vs dsgl threshold (default=128)"); 53 54 static int mr_exceeds_hw_limits(struct c4iw_dev *dev, u64 length) 55 { 56 return (is_t4(dev->rdev.lldi.adapter_type) || 57 is_t5(dev->rdev.lldi.adapter_type)) && 58 length >= 8*1024*1024*1024ULL; 59 } 60 61 static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, 62 u32 len, dma_addr_t data, 63 struct sk_buff *skb, 64 struct c4iw_wr_wait *wr_waitp) 65 { 66 struct ulp_mem_io *req; 67 struct ulptx_sgl *sgl; 68 u8 wr_len; 69 int ret = 0; 70 71 addr &= 0x7FFFFFF; 72 73 if (wr_waitp) 74 c4iw_init_wr_wait(wr_waitp); 75 wr_len = roundup(sizeof(*req) + sizeof(*sgl), 16); 76 77 if (!skb) { 78 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); 79 if (!skb) 80 return -ENOMEM; 81 } 82 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 83 84 req = __skb_put_zero(skb, wr_len); 85 INIT_ULPTX_WR(req, wr_len, 0, 0); 86 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 87 (wr_waitp ? FW_WR_COMPL_F : 0)); 88 req->wr.wr_lo = wr_waitp ? (__force __be64)(unsigned long)wr_waitp : 0L; 89 req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 90 req->cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE) | 91 T5_ULP_MEMIO_ORDER_V(1) | 92 T5_ULP_MEMIO_FID_V(rdev->lldi.rxq_ids[0])); 93 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V(len>>5)); 94 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 16)); 95 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr)); 96 97 sgl = (struct ulptx_sgl *)(req + 1); 98 sgl->cmd_nsge = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 99 ULPTX_NSGE_V(1)); 100 sgl->len0 = cpu_to_be32(len); 101 sgl->addr0 = cpu_to_be64(data); 102 103 if (wr_waitp) 104 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, __func__); 105 else 106 ret = c4iw_ofld_send(rdev, skb); 107 return ret; 108 } 109 110 static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, 111 void *data, struct sk_buff *skb, 112 struct c4iw_wr_wait *wr_waitp) 113 { 114 struct ulp_mem_io *req; 115 struct ulptx_idata *sc; 116 u8 wr_len, *to_dp, *from_dp; 117 int copy_len, num_wqe, i, ret = 0; 118 __be32 cmd = cpu_to_be32(ULPTX_CMD_V(ULP_TX_MEM_WRITE)); 119 120 if (is_t4(rdev->lldi.adapter_type)) 121 cmd |= cpu_to_be32(ULP_MEMIO_ORDER_F); 122 else 123 cmd |= cpu_to_be32(T5_ULP_MEMIO_IMM_F); 124 125 addr &= 0x7FFFFFF; 126 pr_debug("addr 0x%x len %u\n", addr, len); 127 num_wqe = DIV_ROUND_UP(len, C4IW_MAX_INLINE_SIZE); 128 c4iw_init_wr_wait(wr_waitp); 129 for (i = 0; i < num_wqe; i++) { 130 131 copy_len = len > C4IW_MAX_INLINE_SIZE ? C4IW_MAX_INLINE_SIZE : 132 len; 133 wr_len = roundup(sizeof *req + sizeof *sc + 134 roundup(copy_len, T4_ULPTX_MIN_IO), 16); 135 136 if (!skb) { 137 skb = alloc_skb(wr_len, GFP_KERNEL | __GFP_NOFAIL); 138 if (!skb) 139 return -ENOMEM; 140 } 141 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0); 142 143 req = __skb_put_zero(skb, wr_len); 144 INIT_ULPTX_WR(req, wr_len, 0, 0); 145 146 if (i == (num_wqe-1)) { 147 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) | 148 FW_WR_COMPL_F); 149 req->wr.wr_lo = (__force __be64)(unsigned long)wr_waitp; 150 } else 151 req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR)); 152 req->wr.wr_mid = cpu_to_be32( 153 FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16))); 154 155 req->cmd = cmd; 156 req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN_V( 157 DIV_ROUND_UP(copy_len, T4_ULPTX_MIN_IO))); 158 req->len16 = cpu_to_be32(DIV_ROUND_UP(wr_len-sizeof(req->wr), 159 16)); 160 req->lock_addr = cpu_to_be32(ULP_MEMIO_ADDR_V(addr + i * 3)); 161 162 sc = (struct ulptx_idata *)(req + 1); 163 sc->cmd_more = cpu_to_be32(ULPTX_CMD_V(ULP_TX_SC_IMM)); 164 sc->len = cpu_to_be32(roundup(copy_len, T4_ULPTX_MIN_IO)); 165 166 to_dp = (u8 *)(sc + 1); 167 from_dp = (u8 *)data + i * C4IW_MAX_INLINE_SIZE; 168 if (data) 169 memcpy(to_dp, from_dp, copy_len); 170 else 171 memset(to_dp, 0, copy_len); 172 if (copy_len % T4_ULPTX_MIN_IO) 173 memset(to_dp + copy_len, 0, T4_ULPTX_MIN_IO - 174 (copy_len % T4_ULPTX_MIN_IO)); 175 if (i == (num_wqe-1)) 176 ret = c4iw_ref_send_wait(rdev, skb, wr_waitp, 0, 0, 177 __func__); 178 else 179 ret = c4iw_ofld_send(rdev, skb); 180 if (ret) 181 break; 182 skb = NULL; 183 len -= C4IW_MAX_INLINE_SIZE; 184 } 185 186 return ret; 187 } 188 189 static int _c4iw_write_mem_dma(struct c4iw_rdev *rdev, u32 addr, u32 len, 190 void *data, struct sk_buff *skb, 191 struct c4iw_wr_wait *wr_waitp) 192 { 193 u32 remain = len; 194 u32 dmalen; 195 int ret = 0; 196 dma_addr_t daddr; 197 dma_addr_t save; 198 199 daddr = dma_map_single(&rdev->lldi.pdev->dev, data, len, DMA_TO_DEVICE); 200 if (dma_mapping_error(&rdev->lldi.pdev->dev, daddr)) 201 return -1; 202 save = daddr; 203 204 while (remain > inline_threshold) { 205 if (remain < T4_ULPTX_MAX_DMA) { 206 if (remain & ~T4_ULPTX_MIN_IO) 207 dmalen = remain & ~(T4_ULPTX_MIN_IO-1); 208 else 209 dmalen = remain; 210 } else 211 dmalen = T4_ULPTX_MAX_DMA; 212 remain -= dmalen; 213 ret = _c4iw_write_mem_dma_aligned(rdev, addr, dmalen, daddr, 214 skb, remain ? NULL : wr_waitp); 215 if (ret) 216 goto out; 217 addr += dmalen >> 5; 218 data += dmalen; 219 daddr += dmalen; 220 } 221 if (remain) 222 ret = _c4iw_write_mem_inline(rdev, addr, remain, data, skb, 223 wr_waitp); 224 out: 225 dma_unmap_single(&rdev->lldi.pdev->dev, save, len, DMA_TO_DEVICE); 226 return ret; 227 } 228 229 /* 230 * write len bytes of data into addr (32B aligned address) 231 * If data is NULL, clear len byte of memory to zero. 232 */ 233 static int write_adapter_mem(struct c4iw_rdev *rdev, u32 addr, u32 len, 234 void *data, struct sk_buff *skb, 235 struct c4iw_wr_wait *wr_waitp) 236 { 237 int ret; 238 239 if (!rdev->lldi.ulptx_memwrite_dsgl || !use_dsgl) { 240 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb, 241 wr_waitp); 242 goto out; 243 } 244 245 if (len <= inline_threshold) { 246 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb, 247 wr_waitp); 248 goto out; 249 } 250 251 ret = _c4iw_write_mem_dma(rdev, addr, len, data, skb, wr_waitp); 252 if (ret) { 253 pr_warn_ratelimited("%s: dma map failure (non fatal)\n", 254 pci_name(rdev->lldi.pdev)); 255 ret = _c4iw_write_mem_inline(rdev, addr, len, data, skb, 256 wr_waitp); 257 } 258 out: 259 return ret; 260 261 } 262 263 /* 264 * Build and write a TPT entry. 265 * IN: stag key, pdid, perm, bind_enabled, zbva, to, len, page_size, 266 * pbl_size and pbl_addr 267 * OUT: stag index 268 */ 269 static int write_tpt_entry(struct c4iw_rdev *rdev, u32 reset_tpt_entry, 270 u32 *stag, u8 stag_state, u32 pdid, 271 enum fw_ri_stag_type type, enum fw_ri_mem_perms perm, 272 int bind_enabled, u32 zbva, u64 to, 273 u64 len, u8 page_size, u32 pbl_size, u32 pbl_addr, 274 struct sk_buff *skb, struct c4iw_wr_wait *wr_waitp) 275 { 276 int err; 277 struct fw_ri_tpte tpt; 278 u32 stag_idx; 279 static atomic_t key; 280 281 if (c4iw_fatal_error(rdev)) 282 return -EIO; 283 284 stag_state = stag_state > 0; 285 stag_idx = (*stag) >> 8; 286 287 if ((!reset_tpt_entry) && (*stag == T4_STAG_UNSET)) { 288 stag_idx = c4iw_get_resource(&rdev->resource.tpt_table); 289 if (!stag_idx) { 290 mutex_lock(&rdev->stats.lock); 291 rdev->stats.stag.fail++; 292 mutex_unlock(&rdev->stats.lock); 293 return -ENOMEM; 294 } 295 mutex_lock(&rdev->stats.lock); 296 rdev->stats.stag.cur += 32; 297 if (rdev->stats.stag.cur > rdev->stats.stag.max) 298 rdev->stats.stag.max = rdev->stats.stag.cur; 299 mutex_unlock(&rdev->stats.lock); 300 *stag = (stag_idx << 8) | (atomic_inc_return(&key) & 0xff); 301 } 302 pr_debug("stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n", 303 stag_state, type, pdid, stag_idx); 304 305 /* write TPT entry */ 306 if (reset_tpt_entry) 307 memset(&tpt, 0, sizeof(tpt)); 308 else { 309 tpt.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F | 310 FW_RI_TPTE_STAGKEY_V((*stag & FW_RI_TPTE_STAGKEY_M)) | 311 FW_RI_TPTE_STAGSTATE_V(stag_state) | 312 FW_RI_TPTE_STAGTYPE_V(type) | FW_RI_TPTE_PDID_V(pdid)); 313 tpt.locread_to_qpid = cpu_to_be32(FW_RI_TPTE_PERM_V(perm) | 314 (bind_enabled ? FW_RI_TPTE_MWBINDEN_F : 0) | 315 FW_RI_TPTE_ADDRTYPE_V((zbva ? FW_RI_ZERO_BASED_TO : 316 FW_RI_VA_BASED_TO))| 317 FW_RI_TPTE_PS_V(page_size)); 318 tpt.nosnoop_pbladdr = !pbl_size ? 0 : cpu_to_be32( 319 FW_RI_TPTE_PBLADDR_V(PBL_OFF(rdev, pbl_addr)>>3)); 320 tpt.len_lo = cpu_to_be32((u32)(len & 0xffffffffUL)); 321 tpt.va_hi = cpu_to_be32((u32)(to >> 32)); 322 tpt.va_lo_fbo = cpu_to_be32((u32)(to & 0xffffffffUL)); 323 tpt.dca_mwbcnt_pstag = cpu_to_be32(0); 324 tpt.len_hi = cpu_to_be32((u32)(len >> 32)); 325 } 326 err = write_adapter_mem(rdev, stag_idx + 327 (rdev->lldi.vr->stag.start >> 5), 328 sizeof(tpt), &tpt, skb, wr_waitp); 329 330 if (reset_tpt_entry) { 331 c4iw_put_resource(&rdev->resource.tpt_table, stag_idx); 332 mutex_lock(&rdev->stats.lock); 333 rdev->stats.stag.cur -= 32; 334 mutex_unlock(&rdev->stats.lock); 335 } 336 return err; 337 } 338 339 static int write_pbl(struct c4iw_rdev *rdev, __be64 *pbl, 340 u32 pbl_addr, u32 pbl_size, struct c4iw_wr_wait *wr_waitp) 341 { 342 int err; 343 344 pr_debug("*pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n", 345 pbl_addr, rdev->lldi.vr->pbl.start, 346 pbl_size); 347 348 err = write_adapter_mem(rdev, pbl_addr >> 5, pbl_size << 3, pbl, NULL, 349 wr_waitp); 350 return err; 351 } 352 353 static int dereg_mem(struct c4iw_rdev *rdev, u32 stag, u32 pbl_size, 354 u32 pbl_addr, struct sk_buff *skb, 355 struct c4iw_wr_wait *wr_waitp) 356 { 357 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 358 pbl_size, pbl_addr, skb, wr_waitp); 359 } 360 361 static int allocate_window(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 362 struct c4iw_wr_wait *wr_waitp) 363 { 364 *stag = T4_STAG_UNSET; 365 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_MW, 0, 0, 0, 366 0UL, 0, 0, 0, 0, NULL, wr_waitp); 367 } 368 369 static int deallocate_window(struct c4iw_rdev *rdev, u32 stag, 370 struct sk_buff *skb, 371 struct c4iw_wr_wait *wr_waitp) 372 { 373 return write_tpt_entry(rdev, 1, &stag, 0, 0, 0, 0, 0, 0, 0UL, 0, 0, 0, 374 0, skb, wr_waitp); 375 } 376 377 static int allocate_stag(struct c4iw_rdev *rdev, u32 *stag, u32 pdid, 378 u32 pbl_size, u32 pbl_addr, 379 struct c4iw_wr_wait *wr_waitp) 380 { 381 *stag = T4_STAG_UNSET; 382 return write_tpt_entry(rdev, 0, stag, 0, pdid, FW_RI_STAG_NSMR, 0, 0, 0, 383 0UL, 0, 0, pbl_size, pbl_addr, NULL, wr_waitp); 384 } 385 386 static int finish_mem_reg(struct c4iw_mr *mhp, u32 stag) 387 { 388 u32 mmid; 389 390 mhp->attr.state = 1; 391 mhp->attr.stag = stag; 392 mmid = stag >> 8; 393 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 394 mhp->ibmr.length = mhp->attr.len; 395 mhp->ibmr.iova = mhp->attr.va_fbo; 396 mhp->ibmr.page_size = 1U << (mhp->attr.page_size + 12); 397 pr_debug("mmid 0x%x mhp %p\n", mmid, mhp); 398 return xa_insert_irq(&mhp->rhp->mrs, mmid, mhp, GFP_KERNEL); 399 } 400 401 static int register_mem(struct c4iw_dev *rhp, struct c4iw_pd *php, 402 struct c4iw_mr *mhp, int shift) 403 { 404 u32 stag = T4_STAG_UNSET; 405 int ret; 406 407 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, mhp->attr.pdid, 408 FW_RI_STAG_NSMR, mhp->attr.len ? 409 mhp->attr.perms : 0, 410 mhp->attr.mw_bind_enable, mhp->attr.zbva, 411 mhp->attr.va_fbo, mhp->attr.len ? 412 mhp->attr.len : -1, shift - 12, 413 mhp->attr.pbl_size, mhp->attr.pbl_addr, NULL, 414 mhp->wr_waitp); 415 if (ret) 416 return ret; 417 418 ret = finish_mem_reg(mhp, stag); 419 if (ret) { 420 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 421 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp); 422 mhp->dereg_skb = NULL; 423 } 424 return ret; 425 } 426 427 static int alloc_pbl(struct c4iw_mr *mhp, int npages) 428 { 429 mhp->attr.pbl_addr = c4iw_pblpool_alloc(&mhp->rhp->rdev, 430 npages << 3); 431 432 if (!mhp->attr.pbl_addr) 433 return -ENOMEM; 434 435 mhp->attr.pbl_size = npages; 436 437 return 0; 438 } 439 440 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc) 441 { 442 struct c4iw_dev *rhp; 443 struct c4iw_pd *php; 444 struct c4iw_mr *mhp; 445 int ret; 446 u32 stag = T4_STAG_UNSET; 447 448 pr_debug("ib_pd %p\n", pd); 449 php = to_c4iw_pd(pd); 450 rhp = php->rhp; 451 452 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 453 if (!mhp) 454 return ERR_PTR(-ENOMEM); 455 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL); 456 if (!mhp->wr_waitp) { 457 ret = -ENOMEM; 458 goto err_free_mhp; 459 } 460 c4iw_init_wr_wait(mhp->wr_waitp); 461 462 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 463 if (!mhp->dereg_skb) { 464 ret = -ENOMEM; 465 goto err_free_wr_wait; 466 } 467 468 mhp->rhp = rhp; 469 mhp->attr.pdid = php->pdid; 470 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 471 mhp->attr.mw_bind_enable = (acc&IB_ACCESS_MW_BIND) == IB_ACCESS_MW_BIND; 472 mhp->attr.zbva = 0; 473 mhp->attr.va_fbo = 0; 474 mhp->attr.page_size = 0; 475 mhp->attr.len = ~0ULL; 476 mhp->attr.pbl_size = 0; 477 478 ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid, 479 FW_RI_STAG_NSMR, mhp->attr.perms, 480 mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0, 481 NULL, mhp->wr_waitp); 482 if (ret) 483 goto err_free_skb; 484 485 ret = finish_mem_reg(mhp, stag); 486 if (ret) 487 goto err_dereg_mem; 488 return &mhp->ibmr; 489 err_dereg_mem: 490 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 491 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp); 492 err_free_skb: 493 kfree_skb(mhp->dereg_skb); 494 err_free_wr_wait: 495 c4iw_put_wr_wait(mhp->wr_waitp); 496 err_free_mhp: 497 kfree(mhp); 498 return ERR_PTR(ret); 499 } 500 501 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 502 u64 virt, int acc, struct ib_udata *udata) 503 { 504 __be64 *pages; 505 int shift, n, i; 506 int err = -ENOMEM; 507 struct sg_dma_page_iter sg_iter; 508 struct c4iw_dev *rhp; 509 struct c4iw_pd *php; 510 struct c4iw_mr *mhp; 511 512 pr_debug("ib_pd %p\n", pd); 513 514 if (length == ~0ULL) 515 return ERR_PTR(-EINVAL); 516 517 if ((length + start) < start) 518 return ERR_PTR(-EINVAL); 519 520 php = to_c4iw_pd(pd); 521 rhp = php->rhp; 522 523 if (mr_exceeds_hw_limits(rhp, length)) 524 return ERR_PTR(-EINVAL); 525 526 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 527 if (!mhp) 528 return ERR_PTR(-ENOMEM); 529 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL); 530 if (!mhp->wr_waitp) 531 goto err_free_mhp; 532 533 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 534 if (!mhp->dereg_skb) 535 goto err_free_wr_wait; 536 537 mhp->rhp = rhp; 538 539 mhp->umem = ib_umem_get(udata, start, length, acc, 0); 540 if (IS_ERR(mhp->umem)) 541 goto err_free_skb; 542 543 shift = PAGE_SHIFT; 544 545 n = ib_umem_num_pages(mhp->umem); 546 err = alloc_pbl(mhp, n); 547 if (err) 548 goto err_umem_release; 549 550 pages = (__be64 *) __get_free_page(GFP_KERNEL); 551 if (!pages) { 552 err = -ENOMEM; 553 goto err_pbl_free; 554 } 555 556 i = n = 0; 557 558 for_each_sg_dma_page(mhp->umem->sg_head.sgl, &sg_iter, mhp->umem->nmap, 0) { 559 pages[i++] = cpu_to_be64(sg_page_iter_dma_address(&sg_iter)); 560 if (i == PAGE_SIZE / sizeof(*pages)) { 561 err = write_pbl(&mhp->rhp->rdev, pages, 562 mhp->attr.pbl_addr + (n << 3), i, 563 mhp->wr_waitp); 564 if (err) 565 goto pbl_done; 566 n += i; 567 i = 0; 568 } 569 } 570 571 if (i) 572 err = write_pbl(&mhp->rhp->rdev, pages, 573 mhp->attr.pbl_addr + (n << 3), i, 574 mhp->wr_waitp); 575 576 pbl_done: 577 free_page((unsigned long) pages); 578 if (err) 579 goto err_pbl_free; 580 581 mhp->attr.pdid = php->pdid; 582 mhp->attr.zbva = 0; 583 mhp->attr.perms = c4iw_ib_to_tpt_access(acc); 584 mhp->attr.va_fbo = virt; 585 mhp->attr.page_size = shift - 12; 586 mhp->attr.len = length; 587 588 err = register_mem(rhp, php, mhp, shift); 589 if (err) 590 goto err_pbl_free; 591 592 return &mhp->ibmr; 593 594 err_pbl_free: 595 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 596 mhp->attr.pbl_size << 3); 597 err_umem_release: 598 ib_umem_release(mhp->umem); 599 err_free_skb: 600 kfree_skb(mhp->dereg_skb); 601 err_free_wr_wait: 602 c4iw_put_wr_wait(mhp->wr_waitp); 603 err_free_mhp: 604 kfree(mhp); 605 return ERR_PTR(err); 606 } 607 608 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 609 struct ib_udata *udata) 610 { 611 struct c4iw_dev *rhp; 612 struct c4iw_pd *php; 613 struct c4iw_mw *mhp; 614 u32 mmid; 615 u32 stag = 0; 616 int ret; 617 618 if (type != IB_MW_TYPE_1) 619 return ERR_PTR(-EINVAL); 620 621 php = to_c4iw_pd(pd); 622 rhp = php->rhp; 623 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 624 if (!mhp) 625 return ERR_PTR(-ENOMEM); 626 627 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL); 628 if (!mhp->wr_waitp) { 629 ret = -ENOMEM; 630 goto free_mhp; 631 } 632 633 mhp->dereg_skb = alloc_skb(SGE_MAX_WR_LEN, GFP_KERNEL); 634 if (!mhp->dereg_skb) { 635 ret = -ENOMEM; 636 goto free_wr_wait; 637 } 638 639 ret = allocate_window(&rhp->rdev, &stag, php->pdid, mhp->wr_waitp); 640 if (ret) 641 goto free_skb; 642 mhp->rhp = rhp; 643 mhp->attr.pdid = php->pdid; 644 mhp->attr.type = FW_RI_STAG_MW; 645 mhp->attr.stag = stag; 646 mmid = (stag) >> 8; 647 mhp->ibmw.rkey = stag; 648 if (xa_insert_irq(&rhp->mrs, mmid, mhp, GFP_KERNEL)) { 649 ret = -ENOMEM; 650 goto dealloc_win; 651 } 652 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag); 653 return &(mhp->ibmw); 654 655 dealloc_win: 656 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb, 657 mhp->wr_waitp); 658 free_skb: 659 kfree_skb(mhp->dereg_skb); 660 free_wr_wait: 661 c4iw_put_wr_wait(mhp->wr_waitp); 662 free_mhp: 663 kfree(mhp); 664 return ERR_PTR(ret); 665 } 666 667 int c4iw_dealloc_mw(struct ib_mw *mw) 668 { 669 struct c4iw_dev *rhp; 670 struct c4iw_mw *mhp; 671 u32 mmid; 672 673 mhp = to_c4iw_mw(mw); 674 rhp = mhp->rhp; 675 mmid = (mw->rkey) >> 8; 676 xa_erase_irq(&rhp->mrs, mmid); 677 deallocate_window(&rhp->rdev, mhp->attr.stag, mhp->dereg_skb, 678 mhp->wr_waitp); 679 kfree_skb(mhp->dereg_skb); 680 c4iw_put_wr_wait(mhp->wr_waitp); 681 pr_debug("ib_mw %p mmid 0x%x ptr %p\n", mw, mmid, mhp); 682 kfree(mhp); 683 return 0; 684 } 685 686 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 687 u32 max_num_sg, struct ib_udata *udata) 688 { 689 struct c4iw_dev *rhp; 690 struct c4iw_pd *php; 691 struct c4iw_mr *mhp; 692 u32 mmid; 693 u32 stag = 0; 694 int ret = 0; 695 int length = roundup(max_num_sg * sizeof(u64), 32); 696 697 php = to_c4iw_pd(pd); 698 rhp = php->rhp; 699 700 if (mr_type != IB_MR_TYPE_MEM_REG || 701 max_num_sg > t4_max_fr_depth(rhp->rdev.lldi.ulptx_memwrite_dsgl && 702 use_dsgl)) 703 return ERR_PTR(-EINVAL); 704 705 mhp = kzalloc(sizeof(*mhp), GFP_KERNEL); 706 if (!mhp) { 707 ret = -ENOMEM; 708 goto err; 709 } 710 711 mhp->wr_waitp = c4iw_alloc_wr_wait(GFP_KERNEL); 712 if (!mhp->wr_waitp) { 713 ret = -ENOMEM; 714 goto err_free_mhp; 715 } 716 c4iw_init_wr_wait(mhp->wr_waitp); 717 718 mhp->mpl = dma_alloc_coherent(&rhp->rdev.lldi.pdev->dev, 719 length, &mhp->mpl_addr, GFP_KERNEL); 720 if (!mhp->mpl) { 721 ret = -ENOMEM; 722 goto err_free_wr_wait; 723 } 724 mhp->max_mpl_len = length; 725 726 mhp->rhp = rhp; 727 ret = alloc_pbl(mhp, max_num_sg); 728 if (ret) 729 goto err_free_dma; 730 mhp->attr.pbl_size = max_num_sg; 731 ret = allocate_stag(&rhp->rdev, &stag, php->pdid, 732 mhp->attr.pbl_size, mhp->attr.pbl_addr, 733 mhp->wr_waitp); 734 if (ret) 735 goto err_free_pbl; 736 mhp->attr.pdid = php->pdid; 737 mhp->attr.type = FW_RI_STAG_NSMR; 738 mhp->attr.stag = stag; 739 mhp->attr.state = 0; 740 mmid = (stag) >> 8; 741 mhp->ibmr.rkey = mhp->ibmr.lkey = stag; 742 if (xa_insert_irq(&rhp->mrs, mmid, mhp, GFP_KERNEL)) { 743 ret = -ENOMEM; 744 goto err_dereg; 745 } 746 747 pr_debug("mmid 0x%x mhp %p stag 0x%x\n", mmid, mhp, stag); 748 return &(mhp->ibmr); 749 err_dereg: 750 dereg_mem(&rhp->rdev, stag, mhp->attr.pbl_size, 751 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp); 752 err_free_pbl: 753 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 754 mhp->attr.pbl_size << 3); 755 err_free_dma: 756 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 757 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 758 err_free_wr_wait: 759 c4iw_put_wr_wait(mhp->wr_waitp); 760 err_free_mhp: 761 kfree(mhp); 762 err: 763 return ERR_PTR(ret); 764 } 765 766 static int c4iw_set_page(struct ib_mr *ibmr, u64 addr) 767 { 768 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 769 770 if (unlikely(mhp->mpl_len == mhp->attr.pbl_size)) 771 return -ENOMEM; 772 773 mhp->mpl[mhp->mpl_len++] = addr; 774 775 return 0; 776 } 777 778 int c4iw_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 779 unsigned int *sg_offset) 780 { 781 struct c4iw_mr *mhp = to_c4iw_mr(ibmr); 782 783 mhp->mpl_len = 0; 784 785 return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, c4iw_set_page); 786 } 787 788 int c4iw_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 789 { 790 struct c4iw_dev *rhp; 791 struct c4iw_mr *mhp; 792 u32 mmid; 793 794 pr_debug("ib_mr %p\n", ib_mr); 795 796 mhp = to_c4iw_mr(ib_mr); 797 rhp = mhp->rhp; 798 mmid = mhp->attr.stag >> 8; 799 xa_erase_irq(&rhp->mrs, mmid); 800 if (mhp->mpl) 801 dma_free_coherent(&mhp->rhp->rdev.lldi.pdev->dev, 802 mhp->max_mpl_len, mhp->mpl, mhp->mpl_addr); 803 dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size, 804 mhp->attr.pbl_addr, mhp->dereg_skb, mhp->wr_waitp); 805 if (mhp->attr.pbl_size) 806 c4iw_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr, 807 mhp->attr.pbl_size << 3); 808 if (mhp->kva) 809 kfree((void *) (unsigned long) mhp->kva); 810 if (mhp->umem) 811 ib_umem_release(mhp->umem); 812 pr_debug("mmid 0x%x ptr %p\n", mmid, mhp); 813 c4iw_put_wr_wait(mhp->wr_waitp); 814 kfree(mhp); 815 return 0; 816 } 817 818 void c4iw_invalidate_mr(struct c4iw_dev *rhp, u32 rkey) 819 { 820 struct c4iw_mr *mhp; 821 unsigned long flags; 822 823 xa_lock_irqsave(&rhp->mrs, flags); 824 mhp = xa_load(&rhp->mrs, rkey >> 8); 825 if (mhp) 826 mhp->attr.state = 0; 827 xa_unlock_irqrestore(&rhp->mrs, flags); 828 } 829